74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity
at 125
C
description
The 74AC11646 consists of bus transceiver
circuits, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of
the appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental bus-
management functions that can be performed with
the 74AC11646.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74AC11646 is characterized for operation from 40
C to 85
C.
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
DIR
CLKAB
SAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CLKBA
SBA
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
1
L
14
DIR
L
28
CLKAB
X
16
CLKBA
X
27
SAB
X
15
SBA
L
REAL-TIME TRANSFER
BUS B TO BUS A
1
L
14
DIR
H
28
CLKAB
X
16
CLKBA
X
27
SAB
L
15
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
1
X
14
DIR
X
28
CLKAB
16
CLKBA
X
27
SAB
X
15
SBA
X
STORAGE FROM
A, B, OR A AND B
1
L
14
DIR
L
28
CLKAB
X
16
CLKBA
L
27
SAB
X
15
SBA
H
TRANSFER STORED DATA
TO A AND/OR B
X
H
X
X
X
X
X
X
X
L
H
L
X
H
X
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE
OE
OE
OE
Figure 1. Bus-Management Functions
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1 THRU A8
B1 THRU B8
OPERATION OR FUNCTION
X
X
X
X
X
Input
Unspecified
Store A, B unspecified
X
X
X
X
X
Unspecified
Input
,
Store B, A unspecified
H
X
X
X
Input
Input
Store A and B data
H
X
L
L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
L
X
H
X
Input
Output
Stored A data to B bus
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.
logic symbol
OE
G3
1
3 EN2 [AB]
G5
15
SBA
A1
2
B1
20
4D
3 EN1 [BA]
14
DIR
16
CLKBA
28
CLKAB
G7
27
SAB
5
7
7
5
1
1
6D
1
1
1
2
C6
C4
B2
25
A2
3
B3
24
A3
4
B4
23
A4
5
B5
20
A5
10
B6
19
A6
11
B7
18
A7
12
B8
17
A8
13
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
logic diagram (positive logic)
A1
B1
1D
C1
1D
C1
One of Eight
Channels
26
2
27
28
15
16
1
14
SAB
CLKAB
SBA
CLKBA
DIR
OE
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
t /
v
Input transition rise or fall rate
0
10
ns/ V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
I
24
A
4.5 V
3.94
3.8
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
Control pins
VI = VCC or GND
5.5 V
0.1
1
A
IOZ
A or B ports
VO = VCC or GND
5.5 V
0.5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
A
Ci
OE or DIR
VI = VCC or GND
5 V
4.5
pF
Cio
A or B ports
VO = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter IOZ includes the input leakage current.
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
26
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 2)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
65
0
65
MHz
tw
Pulse duration, CLK high or low
7.7
7.7
ns
tsu
Setup time, A or B before CLKAB
or CLKBA
6.5
6.5
ns
th
Hold time, A or B after CLKAB
or CLKBA
1
1
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 2)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
100
0
100
MHz
tw
Pulse duration, CLK high or low
5
5
ns
tsu
Setup time, A or B before CLKAB
or CLKBA
4.5
4.5
ns
th
Hold time, A or B after CLKAB
or CLKBA
1
1
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
65
65
MHz
tPLH
A or B
B or A
1.5
9.1
12.1
1.5
13.8
ns
tPHL
A or B
B or A
1.5
10.7
13.4
1.5
14.5
ns
tPZH
OE
A or B
1.5
13
16.4
1.5
18.7
ns
tPZL
OE
A or B
1.5
16.1
20.4
1.5
21.8
ns
tPHZ
OE
A or B
1.5
7.9
9.6
1.5
10.3
ns
tPLZ
OE
A or B
1.5
7.2
8.9
1.5
9.6
ns
tPLH
CLKBA or CLKAB
A or B
1.5
11.8
15
1.5
17
ns
tPHL
CLKBA or CLKAB
A or B
1.5
13.7
16.8
1.5
18.3
ns
tPLH
SBA or SAB
A or B
1.5
9.8
12.9
1.5
14.4
ns
tPHL
(A or B high)
A or B
1.5
12
14.5
1.5
15.8
ns
tPLH
SBA or SAB
A or B
1.5
10.7
13.8
1.5
15.4
ns
tPHL
(A or B low)
A or B
1.5
12.4
15
1.5
16.4
ns
tPZH
DIR
A or B
1.5
13.7
17.1
1.5
19.4
ns
tPZL
DIR
A or B
1.5
16.8
21
1.5
23.6
ns
tPHZ
DIR
A or B
1.5
7.9
9.7
1.5
10.5
ns
tPLZ
DIR
A or B
1.5
7.3
9.1
1.5
9.9
ns
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
27
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
100
100
MHz
tPLH
A or B
B or A
1.5
5.5
7.9
1.5
8.8
ns
tPHL
A or B
B or A
1.5
6.3
8.9
1.5
9.8
ns
tPZH
OE
A or B
1.5
7.8
10.7
1.5
12
ns
tPZL
OE
A or B
1.5
8.5
11.9
1.5
13.1
ns
tPHZ
OE
A or B
1.5
5.9
8.4
1.5
8.9
ns
tPLZ
OE
A or B
1.5
5.9
7.7
1.5
8.3
ns
tPLH
CLKBA or CLKAB
A or B
1.5
7
9.7
1.5
11
ns
tPHL
CLKBA or CLKAB
A or B
1.5
8.2
11
1.5
12.2
ns
tPLH
SBA or SAB
A or B
1.5
5.9
8.4
1.5
9.4
ns
tPHL
(A or B high)
A or B
1.5
7.2
9.8
1.5
10.7
ns
tPLH
SBA or SAB
A or B
1.5
6.3
8.9
1.5
9.9
ns
tPHL
(A or B low)
A or B
1.5
7.3
9.9
1.5
11
ns
tPZH
DIR
A or B
1.5
8.4
11.2
1.5
12.6
ns
tPZL
DIR
A or B
1.5
9.1
12.3
1.5
13.7
ns
tPHZ
DIR
A or B
1.5
6.3
8.2
1.5
8.7
ns
tPLZ
DIR
A or B
1.5
5.7
7.5
1.5
8.1
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per transceiver
Outputs enabled
CL = 50 pF
f = 1 MHz
59
pF
Cpd
Power dissipation capacitance per transceiver
Outputs disabled
CL = 50 pF,
f = 1 MHz
15
pF
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
28
PARAMETER MEASUREMENT INFORMATION
50% VCC
50%
50%
50%
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
50%
50%
VCC
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
50%
50%
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
VCC
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
VCC
0 V
50%
50%
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
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Copyright
1998, Texas Instruments Incorporated
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