74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Independent Registers and Enables for A
and B Buses
D
Multiplexed Real-Time and Stored Data
D
Inverting Data Paths
D
Flow-Through Architecture Optimizes PCB
Layout
D
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
D
500-mA Typical Latch-Up Immunity at
125
C
description
The 74AC11652 consists of bus transceiver
circuits, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions.
The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred.
A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four
fundamental bus-management functions that can be performed with the 74AC11652.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when
all other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
The 74AC11652 is characterized for operation from 40
C to 85
C.
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OEAB
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
OEBA
CLKAB
SAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CLKBA
SBA
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OEAB
1
X
L
L
OEAB
1
L
14
L
28
CLKAB
X
16
CLKBA
X
27
SAB
X
15
SBA
L
28
CLKAB
X
16
CLKBA
X
27
SAB
L
15
SBA
X
14
H
28
CLKAB
16
CLKBA
X
27
SAB
X
15
SBA
X
28
CLKAB
16
CLKBA
27
SAB
15
SBA
X
H
X
X
X
X
X
H
L
L
H
H
OEBA
OEBA
1
H
14
H
OEAB OEBA
1
14
OEAB
OEBA
L
Figure 1. Bus-Management Functions
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1 THRU A8
B1 THRU B8
OPERATION OR FUNCTION
L
H
L
L
X
X
Input
Input
Isolation
L
H
X
X
Input
Input
Store A and B data
X
H
L
X
X
Input
Unspecified
Store A, hold B
H
H
X
X
Input
Output
Store A in both registers
L
X
L
X
X
Unspecified
Input
Hold A, store B
L
L
X
X
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
L
X
H
X
Input
Output
Stored A data to B bus
H
L
L
L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
logic symbol
1
1
2
A1
2
B1
1
4D
6D
1
7
26
OEBA
7
5
5
1
EN1 [BA]
14
G7
27
SAB
C4
28
CLKAB
G5
15
SBA
16
CLKBA
EN2 [AB]
1
OEAB
C6
A2
3
B2
25
A3
4
B3
24
A4
5
B4
23
A5
10
B5
20
A6
11
B6
19
A7
12
B7
18
A8
13
B8
17
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
A1
B1
1D
C1
1D
C1
One of Eight
Channels
26
2
27
28
15
16
14
1
SAB
CLKAB
SBA
CLKBA
OEAB
OEBA
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air) (see Note 2)
1.7 W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
_
C and a board trace length of 750 mils.
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
t /
v
Input transition rise or fall rate
Control pins
0
5
ns/ V
t /
v
Input transition rise or fall rate
Data
0
10
ns/ V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
I
24
A
4.5 V
3.94
3.8
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
Control inputs
VI = VCC or GND
5.5 V
0.1
1
A
IOZ
A or B ports
VO = VCC or GND
5.5 V
0.5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
A
Ci
Control inputs
VI = VCC or GND
5 V
4.5
pF
Cio
A or B ports
VO = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter IOZ includes the input leakage current.
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 2)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
65
0
65
MHz
tw
Pulse duration, CLK high or low
7.7
7.7
ns
tsu
Setup time, A or B before CLKAB
or CLKBA
6
6
ns
th
Hold time, A or B after CLKAB
or CLKBA
1
1
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 2)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
105
0
105
MHz
tw
Pulse duration, CLK high or low
4.8
4.8
ns
tsu
Setup time, A or B before CLKAB
or CLKBA
4.5
4.5
ns
th
Hold time, A or B after CLKAB
or CLKBA
1
1
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
65
65
MHz
tPLH
A or B
B or A
2.9
8.5
11.1
2.9
12.9
ns
tPHL
A or B
B or A
3.9
10.3
12.9
3.9
14.2
ns
tPLH
CLKBA or CLKAB
A or B
4.3
11.2
14.3
4.3
16.2
ns
tPHL
CLKBA or CLKAB
A or B
5.3
13.1
16.2
5.3
17.8
ns
tPLH
SBA or SAB
A or B
3.4
9.4
12
3.4
13.7
ns
tPHL
(A or B high)
A or B
4.7
11.5
14.3
4.7
15.6
ns
tPLH
SBA or SAB
A or B
3.9
10.5
13.3
3.9
14.9
ns
tPHL
(A or B low)
A or B
4.8
12.1
16.3
4.8
17.7
ns
tPZH
OEBA
A
4.3
11.1
14.5
4.3
16.5
ns
tPZL
OEBA
A
5.2
14.4
19.8
5.2
22
ns
tPHZ
OEBA
A
3.7
6.4
8.1
3.7
8.5
ns
tPLZ
OEBA
A
3.5
6
7.8
3.5
8.2
ns
tPZH
OEAB
B
4.7
11.6
15
4.7
16.9
ns
tPZL
OEAB
B
5.6
14.8
19.9
5.6
21.9
ns
tPHZ
OEAB
B
4
6.6
8.2
4
8.6
ns
tPLZ
OEAB
B
3.5
6.1
7.7
3.5
8
ns
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
105
105
MHz
tPLH
A or B
B or A
2.4
5.2
7.6
2.4
8.6
ns
tPHL
A or B
B or A
3.1
6
8.7
3.1
9.6
ns
tPLH
CLKBA or CLKAB
A or B
3.6
6.7
9.5
3.6
10.7
ns
tPHL
CLKBA or CLKAB
A or B
4.4
7.8
10.8
4.4
12
ns
tPLH
SBA or SAB
A or B
2.9
5.6
8.1
2.9
9.1
ns
tPHL
(A or B high)
A or B
3.8
6.9
9.6
3.8
10.7
ns
tPLH
SBA or SAB
A or B
3.3
6.2
8.8
3.3
9.9
ns
tPHL
(A or B low)
A or B
4
7.1
9.9
4
10.9
ns
tPZH
OEBA
A
3.3
6.6
9.6
3.3
10.9
ns
tPZL
OEBA
A
4.2
7.4
10.9
4.2
12.2
ns
tPHZ
OEBA
A
3.6
5.5
7.2
3.6
7.6
ns
tPLZ
OEBA
A
3.3
5
6.7
3.3
7.1
ns
tPZH
OEAB
B
4.1
7.2
10.1
4.1
11.3
ns
tPZL
OEAB
B
4.6
7.9
11.1
4.6
12.3
ns
tPHZ
OEAB
B
3.9
5.6
7.3
3.9
7.6
ns
tPLZ
OEAB
B
3.4
5.2
6.8
3.4
7.2
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per transceiver
Outputs enabled
CL = 50 pF
f = 1 MHz
60
pF
Cpd
Power dissipation capacitance per transceiver
Outputs disabled
CL = 50 pF, f = 1 MHz
14
pF
74AC11652
OCTAL BUS TRANSCEIVER AND REGISTERS
WITH 3-STATE OUTPUTS
SCAS088A - DECEMBER 1989 - REVISED APRIL 1996
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
50%
50%
50%
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
50%
50%
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
50%
50%
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
VCC
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
VCC
0 V
50%
50%
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
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Copyright
1998, Texas Instruments Incorporated
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