74AC11873
DUAL 4-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS095 JANUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Bus-Structured Pinout
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity
at 125
C
description
This dual 4-bit transparent D-type latch features
3-state outputs designed specifically for bus
driving. This makes these devices particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
When the latch-enable (1LE or 2LE) input is high, the Q outputs will follow the data (D) inputs in true form,
according to the function table. When LE is taken low, the outputs will be latched. When the clear (1CLR or
2CLR) input goes low, the Q outputs go low independently of LE. The outputs are in a high-impedance state
when the output-control (1OC or 2OC) input is at a high logic level.
The 74AC11873 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each 4-bit latch)
INPUTS
OUTPUT
OC
CLR
LE
D
Q
L
L
X
X
L
L
H
H
H
H
L
H
H
L
L
L
H
L
X
Q0
H
X
X
X
Z
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1LE
1Q1
1Q2
1Q3
1Q4
GND
GND
GND
GND
2Q1
2Q2
2Q3
2Q4
2LE
1OC
1CLR
1D1
1D2
1D3
1D4
V
CC
V
CC
2D1
2D2
2D3
2D4
2CLR
2OC
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74AC11873
DUAL 4-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS095 JANUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbol
logic diagram, each quad latch (positive logic)
EN
28
C1
1
1LE
1D
26
1D1
25
1D2
24
1D3
23
1D4
1Q1
2
1Q2
3
1Q3
4
1Q4
5
R
27
1OC
1CLR
EN
15
C1
14
2LE
1D
20
2D1
19
2D2
18
2D3
17
2D4
2Q1
10
2Q2
11
2Q3
12
2Q4
13
R
16
2OC
2CLR
R
C1
1D
OC
LE
CLR
D1
Q1
R
C1
1D
Q2
R
C1
1D
Q3
R
C1
1D
Q4
D2
D3
D4
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
74AC11873
DUAL 4-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS095 JANUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
t /
v
Input transition rise or fall rate
0
10
ns/ V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
I
24
A
4.5 V
3.94
3.8
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
A
IOZ
VO = VCC or GND
5.5 V
0.5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
A
Ci
VI = VCC or GND
5 V
4.5
pF
Co
VO = VCC or GND
5 V
13.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
74AC11873
DUAL 4-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS095 JANUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
CLR low
5
5
ns
tw
Pulse duration
LE high
5
5
ns
t
Setup time data before LE
HIgh
3
3
ns
tsu
Setup time, data before LE
Low
4
4
ns
th
Hold time data after LE
High
1
1
ns
th
Hold time, data after LE
Low
1
1
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
CLR low
5
5
ns
tw
Pulse duration
LE high
5
5
ns
t
Setup time data before LE
HIgh
2
2
ns
tsu
Setup time, data before LE
Low
3
3
ns
th
Hold time data after LE
High
1
1
ns
th
Hold time, data after LE
Low
1
1
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
D
Q
2.8
8.8
11.2
2.8
13
ns
tPHL
D
Q
2.8
9
11.2
2.8
12.7
ns
tPLH
LE
Q
3
9.4
11.8
3
13.6
ns
tPHL
LE
Q
2.9
9.4
11.7
2.9
13.2
ns
tPHL
CLR
Q
2.3
8.2
10.3
2.3
11.5
ns
tPZH
OC
Q
1.8
6.4
8.4
1.8
9.7
ns
tPZL
OC
Q
2.7
9.9
12.5
2.7
14.4
ns
tPHZ
OC
Q
3.8
6.8
8.4
3.8
9
ns
tPLZ
OC
Q
3.5
6.8
8.5
3.5
9.1
ns
74AC11873
DUAL 4-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS095 JANUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
D
Q
2.2
5.5
7.3
2.2
8.4
ns
tPHL
D
Q
2.1
5.5
7.2
2.1
8.2
ns
tPLH
LE
Q
2.4
5.9
7.8
2.4
8.9
ns
tPHL
LE
Q
2.2
5.8
7.6
2.2
8.7
ns
tPHL
CLR
Q
1.7
5.1
6.8
1.7
7.6
ns
tPZH
OC
Q
1.2
4.1
5.6
1.2
6.4
ns
tPZL
OC
Q
1.9
5.5
7.3
1.9
8.5
ns
tPHZ
OC
Q
3.5
5.9
7.4
3.5
7.9
ns
tPLZ
OC
Q
3.3
5.5
7
3.3
7.6
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per latch
Outputs enabled
CL = 50 pF
f = 1 MHz
43
pF
Cpd
Power dissipation capacitance per latch
Outputs disabled
CL = 50 pF,
f = 1 MHz
9
pF
74AC11873
DUAL 4-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS095 JANUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
26
PARAMETER MEASUREMENT INFORMATION
50% VCC
50%
50%
50%
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
50%
50%
VCC
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
50%
50%
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
VCC
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
VCC
0 V
50%
50%
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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1998, Texas Instruments Incorporated
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