74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B JUNE 1987 REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Eight Latches in a Single Package
D
3-State Bus Driving True Outputs
D
Full Parallel Access for Loading
D
Buffered Input and Output-Enable Pins
D
Inputs Are TTL-Voltage Compatible
D
Flow-Through Architecture Optimizes
PCB Layout
D
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
D
500-mA Typical Latch-Up Immunity at
125
C
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
description
This 8-bit latch features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight latches of the 74ACT11373 are transparent D-type latches. While the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When the enable is taken low, the Q outputs are latched at the levels
that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impendance third state and increased drive provide the capability to drive
the bus lines in a bus-organized system without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The 74ACT11373 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
DB, DW, OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
OE
1D
2D
3D
4D
V
CC
V
CC
5D
6D
7D
8D
LE
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B JUNE 1987 REVISED APRIL 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
8D
7D
6D
5D
4D
3D
2D
1D
LE
OE
14
16
17
20
21
22
23
13
24
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
12
11
10
9
4
3
2
1
1D
C1
EN
15
logic diagram (positive logic)
8D
7D
6D
5D
4D
3D
2D
1D
LE
OE
14
15
16
17
20
21
22
23
13
24
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
12
11
10
9
4
3
2
1
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B JUNE 1987 REVISED APRIL 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air) (see Note 2): DB package
0.65 W
. . . . . . . . . . . . . . . . . .
DW package
1.7 W
. . . . . . . . . . . . . . . . . .
NT package
1.3 W
. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
_
C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero.
recommended operating conditions
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
D
t/
D
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B JUNE 1987 REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
OH
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
{
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
OL
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
{
5.5 V
1.65
IOZ
VO = VCC or GND
5.5 V
0.5
5
m
A
II
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
m
A
D
ICC
}
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4
pF
Co
VO = VCC or GND
5 V
10
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
5
5
ns
tsu
Setup time, data before LE
3.5
3.5
ns
th
Hold time, data LE
3.5
3.5
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
D
Q
1.5
7.5
10.3
1.5
11.8
ns
tPHL
D
Q
1.5
6.5
9.3
1.5
10
ns
tPLH
LE
Any Q
1.5
8.5
11.3
1.5
13
ns
tPHL
LE
Any Q
1.5
8.5
10.9
1.5
12.2
ns
tPZH
OE
Any Q
1.5
7
10.7
1.5
12.5
ns
tPZL
OE
Any Q
1.5
7.5
10.9
1.5
12
ns
tPHZ
OE
Any Q
1.5
10
12.1
1.5
12.2
ns
tPLZ
OE
Any Q
1.5
7.5
9.5
1.5
10.1
ns
74ACT11373
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B JUNE 1987 REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per latch
Outputs enabled
CL = 50 pF
f = 1 MHz
65
pF
Cpd
Power dissipation capacitance per latch
Outputs disabled
CL = 50 pF,
f = 1 MHz
54
pF
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright
1998, Texas Instruments Incorporated
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