74ACT11620
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS060A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
1
Inputs Are TTL-Voltage Compatible
Local Bus-Latch Capability
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at
125
C
Package Options Include Plastic Small-
Outline Packages, and Standard Plastic
300-mil DIPs
description
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The
control function implementation allows for maximum flexibility in timing.
These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending
upon the logic levels at the enable inputs (GBA and GAB).
The enable inputs can be used to disable the device so that the buses are effectively isolated.
The dual-enable configuration gives these devices the capability to store data by simultaneous eanbling of GBA
and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16
in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be complementary
for the 74ACT11620.
The 74ACT11620 is characterized for operation from 40
C to 85
C.
GBA
L
H
H
GAB
L
H
L
B data to A bus
A data to B bus
Isolation
B data to A bus,
A data to B bus
OPERATION
ENABLE INPUTS
L
H
FUNCTION TABLE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
GAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
GBA
DW OR NT PACKAGE
(TOP VIEW)
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74ACT11620
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS060A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
logic symbol
logic diagram (positive logic)
2
1
EN2
EN1
A8
A7
A6
A5
A4
A3
A2
A1
GAB
GBA
12
11
10
9
4
3
2
1
24
13
B8
B7
B6
B5
B4
B3
B2
B1
14
15
16
17
20
21
22
23
To Other Six Transceivers
B2
B1
A2
A1
GAB
GBA
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74ACT11620
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS060A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
recommended operating conditions
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
D
t/
D
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
OH
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
OL
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
IOZ
A or B ports
VO = VCC or GND
5.5 V
0.5
5
m
A
II
GBA or GAB
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
8
m
A
D
I
One input at 3.4 V,
5 5 V
0 9
1
mA
D
ICC
,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
GBA or GAB
VI = VCC or GND
5 V
4
pF
Co
A or B ports
VO = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter IOZ includes the input leakage.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
74ACT11620
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS060A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
A or B
B or A
1.5
5.7
8.5
1.5
9.4
ns
tPHL
A or B
B or A
1.5
5.9
7.7
1.5
8.6
ns
tPZH
GBA
A
1.5
7.2
9.1
1.5
10.3
ns
tPZL
GBA
A
1.5
7.1
9.2
1.5
10.1
ns
tPHZ
GBA
A
1.5
7.9
9.6
1.5
10.4
ns
tPLZ
GBA
A
1.5
8.3
10
1.5
10.9
ns
tPZH
GAB
B
1.5
7.5
10.2
1.5
11.3
ns
tPZL
GAB
B
1.5
7.7
9.8
1.5
11
ns
tPHZ
GAB
B
1.5
7.2
8.9
1.5
9.4
ns
tPLZ
GAB
B
1.5
7.2
8.9
1.5
9.6
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per transceiver
Outputs enabled
CL = 50 pF
f = 1 MHz
54
pF
Cpd Power dissipation capacitance per transceiver
Outputs disabled
CL = 50 pF, f = 1 MHz
11
pF
74ACT11620
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS060A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 X VCC
Open
GND
500
500
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
OPEN
2 x VCC
GND
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0
50%
50%
Input
(see Note C)
Out-of-Phase
Output
In-Phase
Output
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
S1 at 2 x VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
0
50%
20%
50%
80%
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
3 V
50%
50%
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform
2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright
1998, Texas Instruments Incorporated
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