1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
G
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
DIR
CAB
SAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
CBA
SBA
DW PACKAGE
(TOP VIEW)
74ACT11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS061A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at 125
C
description
These devices consist of bus transceiver circuits,
3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of
data directly from the data bus or from the internal
storage registers. Data on the A or B bus will be
clocked into the registers on the low-to-high
transition of the appropriate clock pin (CAB or
CBA). Figure 1 illustrates the four fundamental
bus-management functions that can be performed
with the octal bus transceivers and registers.
Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode,
data present at the high-impedance port may be stored in either register or in both. The select controls (SAB
and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for select control will
eliminate the typical decoding glitch which occurs in a multiplexer during the transition between stored and
real-time data. The direction control determines which bus will receive data when enable G is active (low). In
the isolation mode (control G high), A data may be stored in one register and/or B data may be stored in the
other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74ACT11646 is characterized for operation from 40
C to 85
C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
74ACT11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS061A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
BUS A
BUS B
BUS A
BUS B
1
14
28
16
27
15
1
14
28
16
27
15
G
DIR
CAB
CBA
SAB
SBA
G
DIR
CAB
CBA
SAB
SBA
L
L
X
X
X
L
L
H
X
X
L
X
REAL-TIME TRANSFER BUS B TO BUS A
REAL-TIME TRANSFER BUS A TO BUS B
BUS A
BUS B
BUS A
BUS B
1
14
28
16
27
15
1
14
28
16
27
15
G
DIR
CAB
CBA
SAB
SBA
G
DIR
CAB
CBA
SAB
SBA
X
X
X
X
X
L
L
X
H or L
X
H
X
X
X
X
X
L
H
H or L
X
H
X
H
X
X
X
STORAGE FROM A, B, OR A AND B
TRANSFER STORED DATA TO A OR B
Figure 1. Bus-Management Functions
74ACT11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS061A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
G
DIR
CAB
CBA
SAB
SBA
A1 THRU A8
B1 THRU B8
OPERATION OR FUNCTION
X
X
X
X
X
Input
Unspecified
Store A, B unspecified
X
X
X
X
X
Unspecified
Input
,
Store B, A unspecified
H
X
X
X
Input
Input
Store A and B Data
H
X
H or L
H or L
X
X
Input
Input
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H or L
X
H
Output
Input
Stored B Data to A Bus
L
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
L
H
H or L
X
H
X
Input
Output
Stored A Data to B Bus
The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every low-to-high transition on the clock inputs.
logic symbol
functional block diagram (positive logic)
To Seven Other Channels
B1
26
A1
2
SAB
CAB
SBA
CBA
DIR
G1
27
28
15
16
14
1
Channels
1 of 8
1D
C1
C1
1D
5
5
B8
B7
B6
B5
B4
B3
B2
B1
17
18
19
20
23
24
25
26
A8
A7
A6
A5
A4
A3
A2
A1
SAB
CAB
SBA
CBA
DIR
G
13
12
11
10
5
4
3
2
27
28
15
16
14
1
1
6D
7
7
4D
G7
C6
G5
C4
3 EN2 [AB]
3 EN1 [BA]
G3
2
1
1
1
1
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
74ACT11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS061A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
D
t /
D
v
Input transition rise or fall rate
0
10
ns/ V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
IOZ
A or B ports
VO = VCC or GND
5.5 V
0.5
5
m
A
II
G or DIR
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
80
m
A
D
ICC
One input at 3.4 V, Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4.5
pF
Co
VO = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter IOZ includes the leakage current.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
74ACT11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS061A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
105
0
105
MHz
tw
Pulse duration, CAB or CBA high or low
4.8
4.8
ns
tsu
Setup time, A before CLK
or B before CBA
4.5
4.5
ns
th
Hold time, A after CAB
or B after CBA
2.5
2.5
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
105
105
MHz
tPLH
A or B
B or A
1.5
7.3
10.1
1.5
11.5
ns
tPHL
A or B
B or A
1.5
7.2
11
1.5
12
ns
tPZH
G
A or B
1.5
7.7
12.8
1.5
14.4
ns
tPZL
G
A or B
1.5
9.2
13.8
1.5
15.3
ns
tPHZ
G
A or B
1.5
8.6
10.7
1.5
11.6
ns
tPLZ
G
A or B
1.5
7.8
9.7
1.5
10.6
ns
tPLH
CBA or CAB
A or B
1.5
8.8
11.9
1.5
13.5
ns
tPHL
CBA or CAB
A or B
1.5
10
13.4
1.5
14.9
ns
tPZH
DIR
A or B
1.5
10.2
13.7
1.5
15.3
ns
tPZL
DIR
A or B
1.5
10.9
14.8
1.5
16.5
ns
tPHZ
DIR
A or B
1.5
7.9
10.5
1.5
11.3
ns
tPLZ
DIR
A or B
1.5
7.3
9.5
1.5
10.3
ns
tPLH
SBA or SAB
A or B
1.5
6.7
10.3
1.5
11.5
ns
tPHL
( A or B high)
A or B
1.5
9.1
12.1
1.5
13.5
ns
tPLH
SBA or SAB
A or B
1.5
8
10.9
1.5
12.4
ns
tPHL
( A or B low)
A or B
1.5
8.1
11.9
1.5
13.1
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per transceiver
Outputs enabled
CL = 50 pF
f = 1 MHz
63
pF
Cpd Power dissipation capacitance per transceiver
Outputs disabled
CL = 50 pF,
f = 1 MHz
14
pF
74ACT11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS061A D2957, JULY 1987 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
26
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
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In order to minimize risks associated with the customer's applications, adequate design and operating
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Copyright
1998, Texas Instruments Incorporated
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