SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Single Down / Up Count-Control Line
D
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
D
Fully Synchronous in Count Modes
D
Asynchronously Presettable With Load
Control
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The 'ALS191A are synchronous 4-bit reversible
up/down binary counters. Synchronous counting
operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincidentally with each other when
instructed by the steering logic. This mode of
operation eliminates the output counting spikes
normally associated with asynchronous
(ripple-clock) counters.
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock (CLK)
input if the count enable (CTEN) input is low. A
high at CTEN inhibits counting. The direction of
the count is determined by the level of the
down/up (D/U) input. When D/U is low, the counter
counts up, and when D/U is high, the counter
counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter is dictated solely by the conditions meeting the stable setup and hold times.
These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD
input and entering the desired data at the data inputs. The output changes to agree with the data inputs
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers
by simply modifying the count length with the preset inputs.
CLK, D/U, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on
(current required by) clock drivers, for long parallel words.
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
B
Q
B
Q
A
CTEN
D/U
Q
C
Q
D
GND
V
CC
A
CLK
RCO
MAX/MIN
LOAD
C
D
SN54ALS191A . . . J PACKAGE
SN74ALS191A . . . D OR N PACKAGE
(TOP VIEW)
SN54ALS191A . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
CLK
RCO
NC
MAX/MIN
LOAD
Q
A
CTEN
NC
D/U
Q
C
B
NC
D
C
A
Q
GND
NC
D
Q
B
V
CC
NC No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The
latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of
the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output
(RCO) produces a low-level output pulse under those same conditions, but only while the clock input is low. The
counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter
if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count
(MAX/MIN) output can be used to accomplish look ahead for high-speed operation.
The SN54ALS191A is characterized for operation over the full military temperature range of 55
C to 125
C.
The SN74ALS191A is characterized for operation from 0
C to 70
C.
logic symbol
1,2 / 1,3+
CTRDIV16
M2 [DOWN]
5
M3 [UP]
14
CLK
G4
C5
11
MAX/MIN
12
2(CT=0)Z6
3(CT=15)Z6
13
6,1,4
3
2
6
7
5D
15
A
1
B
10
C
9
D
G1
4
[1]
[2]
[4]
[8]
CTEN
D/U
QA
QB
QC
QD
LOAD
RCO
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
15
4
11
14
5
CLK
A
1
10
9
B
C
D
CTEN
D/U
LOAD
QB
QC
QD
2
6
7
MAX/
MIN
QA
12
13
3
RCO
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
Pin numbers shown are for the D, J, and N packages.
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical load, count, and inhibit sequences
The following sequence is illustrated below:
1.
Load (preset) to binary 13
2.
Count up to 14, 15 (maximum), 0, 1, and 2
3.
Inhibit
4.
Count down to 1, 0 (minimum), 15, 14, and 13
2
A
B
C
D
CLK
D/U
MAX/MIN
QA
QD
QC
QB
Load
Count Up
Inhibit
Count Down
13
14
15
0
1
2
2
1
0
15
14
13
Data
Inputs
RCO
CTEN
LOAD
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS191A
55
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS191A
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS191A
SN74ALS191A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.7
0.8
V
IOH
High-level output current
0.4
0.4
mA
IOL
Low-level output current
4
8
mA
fclock
Clock frequency
0
20
0
30
MHz
t
Pulse duration
CLK high or low
20
16.5
ns
tw
Pulse duration
LOAD low
25
20
ns
Data before LOAD
25
20
t
Setup time
CTEN before CLK
45
20
ns
tsu
Setup time
D/U before CLK
30
20
ns
LOAD inactive before CLK
20
20
Data after LOAD
5
5
th
Hold time
CTEN after CLK
0
0
ns
D/U after CLK
0
0
TA
Operating free-air temperature
55
125
0
70
C
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS191A
SN74ALS191A
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.5
1.5
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = 0.4 mA
VCC 2
VCC 2
VOL
VCC = 4 5 V
IOL = 4 mA
0.25
0.4
0.25
0.4
V
VOL
VCC = 4.5 V
IOL = 8 mA
0.35
0.5
II
VCC = 5.5 V,
VI = 7 V
0.2
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
CTEN or CLK
VCC = 5 5 V
VI = 0 4 V
0.2
0.2
mA
IIL
All others
VCC = 5.5 V,
VI = 0.4 V
0.2
0.1
mA
IO
VCC = 5.5 V,
VO = 2.25 V
20
112
30
112
mA
ICC
VCC = 5.5 V,
All inputs at 0
12
22
12
22
mA
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
switching characteristics (see Figure 1)
PARAMETER
FROM
(OUTPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
(OUTPUT)
(OUTPUT)
SN54ALS191A
SN74ALS191A
MIN
MAX
MIN
MAX
fmax
20
30
MHz
tPLH
LOAD
Any Q
7
37
7
30
ns
tPHL
LOAD
Any Q
8
34
8
30
ns
tPLH
A B C D
Any Q
3
25
3
21
ns
tPHL
A, B, C, D
Any Q
4
25
4
21
ns
tPLH
CLK
RCO
5
24
5
20
ns
tPHL
CLK
RCO
5
25
5
20
ns
tPLH
CLK
Any Q
3
26
3
18
ns
tPHL
CLK
Any Q
3
22
3
18
ns
tPLH
CLK
MAX/MIN
8
37
8
31
ns
tPHL
CLK
MAX/MIN
8
34
8
31
ns
tPLH
D/U
RCO
8
45
8
37
ns
tPHL
D/U
RCO
10
36
10
28
ns
tPLH
D/U
MAX/MIN
8
35
8
25
ns
tPHL
D/U
MAX/MIN
8
30
8
25
ns
tPLH
CTEN
RCO
4
21
4
18
ns
tPHL
CTEN
RCO
4
23
4
18
ns
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS191A, SN74ALS191A
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS
SDAS210C DECEMBER 1982 REVISED JULY 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/ 74ALS AND 54AS/ 74AS DEVICES
tPHZ
tPLZ
tPHL
tPLH
0.3 V
tPZL
tPZH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
VOH
VOL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
CL
(see Note A)
RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
PDF 
ZIP