SN54ALVTH16374, SN74ALVTH16374

2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCES068F JUNE 1996 REVISED JANUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

State-of-the-Art Advanced BiCMOS
Technology (ABT)

Widebus

Design for

2.5-V and 3.3-V Operation and Low Static
Power Dissipation

Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V

)

Typical V

OLP

(Output Ground Bounce)

< 0.8 V at V

= 3.3 V, T

= 25

High Drive (24/24 mA at 2.5-V and
32/64 mA at 3.3-V V

)

Power Off Disables Outputs, Permitting
Live Insertion

High-Impedance State During Power Up
and Power Down Prevents Driver Conflict

Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating

Auto3-State Eliminates Bus Current
Loading When Output Exceeds V

+ 0.5 V

Latch-Up Performance Exceeds 250 mA Per
JESD 17

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method

Flow-Through Architecture Facilitates
Printed Circuit Board Layout

Distributed V

and GND Pin Configuration

Minimizes High-Speed Switching Noise

Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package

description

The 'ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V
or 3.3-V V

operation, but with the capability to provide a TTL interface to a 5-V system environment. These

devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK), the flip-flops store the logic levels set up at the data (D) inputs.

1999, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

SN54ALVTH16374 . . . WD PACKAGE

SN74ALVTH16374 . . . DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1OE

1Q1
1Q2

GND

1Q3
1Q4

1Q5
1Q6

GND

1Q7
1Q8
2Q1
2Q2

GND

2Q3
2Q4

2Q5
2Q6

GND

2Q7
2Q8

2OE

1CLK
1D1
1D2
GND
1D3
1D4
V

1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V

2D5
2D6
GND
2D7
2D8
2CLK

SN54ALVTH16374, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCES068F JUNE 1996 REVISED JANUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

description (continued)

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When V

is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.2 V, OE should be tied to V

through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ALVTH16374 is characterized for operation over the full military temperature range of 55

C to

125

C. The SN74ALVTH16374 is characterized for operation from 40

C to 85

FUNCTION TABLE

(each 8-bit section)

INPUTS

OUTPUT

CLK

H or L

SN54ALVTH16374, SN74ALVTH16374

2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCES068F JUNE 1996 REVISED JANUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

logic diagram (positive logic)

1OE

1CLK

1D1

To Seven Other Channels

1Q1

2OE

2CLK

2D1

2Q1

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(see Note 1)

0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in

the high-impedance

or power-off state, V

(see Note 1)

0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state, V

(see Note 1)

0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . .

Output current in the low state, I

: SN54ALVTH16374 96

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ALVTH16374 128

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current in the high state, I

: SN54ALVTH16374 48

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ALVTH16374 64

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

< 0)

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

< 0)

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

(see Note 2): DGG package

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions, V

= 2.5 V

0.2 V (see Note 3)

SN54ALVTH16374

SN74ALVTH16374

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

VCC

Supply voltage

2.3

2.7

2.3

2.7

VIH

High-level input voltage

1.7

VIL

Low-level input voltage

0.7

Input voltage

VCC

5.5

VCC

5.5

IOH

High-level output current

IOL

Low-level output current

IOL

Low-level output current; current duty cycle

50%; f

1 kHz

Input transition rise or fall rate

Outputs enabled

ns/V

VCC

Power-up ramp rate

200

s/V

Operating free-air temperature

125

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

SN54ALVTH16374, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCES068F JUNE 1996 REVISED JANUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

recommended operating conditions, V

= 3.3 V

0.3 V (see Note 3)

SN54ALVTH16374

SN74ALVTH16374

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

VCC

Supply voltage

3.6

VIH

High-level input voltage

VIL

Low-level input voltage

0.8

Input voltage

VCC

5.5

VCC

5.5

IOH

High-level output current

IOL

Low-level output current

IOL

Low-level output current; current duty cycle

50%; f

1 kHz

Input transition rise or fall rate

Outputs enabled

ns/V

VCC

Power-up ramp rate

200

s/V

Operating free-air temperature

125

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SN54ALVTH16374, SN74ALVTH16374

2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCES068F JUNE 1996 REVISED JANUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,
V

= 2.5 V

0.2 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SN54ALVTH16374

SN74ALVTH16374

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

VIK

VCC = 2.3 V,

II = 18 mA

1.2

VCC = 2.3 V to 2.7 V,

IOH = 100

VCC0.2

VOH

VCC = 2 3 V

IOH = 6 mA

1.8

VCC = 2.3 V

IOH = 8 mA

1.8

VCC = 2.3 V to 2.7 V,

IOL = 100

0.2

IOL = 6 mA

0.4

VOL

VCC = 2 3 V

IOL = 8 mA

0.4

VCC = 2.3 V

IOL = 18 mA

0.5

IOL = 24 mA

0.5

Control inputs

VCC = 2.7 V,

VI = VCC or GND

Control inputs

VCC = 0 or 2.7 V,

VI = 5.5 V

Data inputs

VCC = 2.7 V

VI = VCC

VI = 0

Ioff

VCC = 0,

VI or VO = 0 to 4.5 V

100

IBHL

VCC = 2.3 V,

VI = 0.7 V

115

IBHH§

VCC = 2.3 V,

VI = 1.7 V

IBHLO¶

VCC = 2.7 V,

VI = 0 to VCC

300

IBHHO#

VCC = 2.7 V,

VI = 0 to VCC

300

IEX||

VCC = 2.3 V,

VO = 5.5 V

125

IOZ(PU/PD)

VCC

1.2 V, VO = 0.5 V to VCC,

VI = GND or VCC, OE = don't care

100

IOZH

VCC = 2 7 V

VO = 2.3 V,

IOZH

VCC = 2.7 V

VI = 0.7 V or 1.7 V

IOZL

VCC = 2 7 V

VO = 0.5 V,

IOZL

VCC = 2.7 V

VI = 0.7 V or 1.7 V

VCC = 2.7 V,

Outputs high

0.04

0.1

0.04

0.1

ICC

VCC = 2.7 V,
IO = 0,

Outputs low

2.3

4.5

2.3

4.5

VI = VCC or GND

Outputs disabled

0.04

0.1

0.04

0.1

VCC = 2.5 V,

VI = 2.5 V or 0

3.5

VCC = 2.5 V,

VO = 2.5 V or 0

All typical values are at VCC = 2.5 V, TA = 25

The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and

then raising it to VIL max.

§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and

then lowering it to VIH min.

¶ An external driver must source at least IBHLO to switch this node from low to high.

# An external driver must sink at least IBHHO to switch this node from high to low.

|| Current into an output in the high state when VO > VCC

High-impedance state during power up or power down

SN54ALVTH16374, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCES068F JUNE 1996 REVISED JANUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,
V

= 3.3 V

0.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SN54ALVTH16374

SN74ALVTH16374

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

VIK

VCC = 3 V,

II = 18 mA

1.2

VCC = 3 V to 3.6 V,

IOH = 100

VCC0.2

VOH

VCC = 3 V

IOH = 24 mA

VCC = 3 V

IOH = 32 mA

VCC = 3 V to 3.6 V,

IOL = 100

0.2

IOL = 16 mA

0.4

VOL

IOL = 24 mA

0.5

VOL

VCC = 3 V

IOL = 32 mA

0.5

IOL = 48 mA

0.55

IOL = 64 mA

0.55

Control inputs

VCC = 3.6 V,

VI = VCC or GND

Control inputs

VCC = 0 or 3.6 V,

VI = 5.5 V

Data inputs

VCC = 3.6 V

VI = VCC

VI = 0

Ioff

VCC = 0,

VI or VO = 0 to 4.5 V

100

IBHL

VCC = 3 V,

VI = 0.8 V

IBHH§

VCC = 3 V,

VI = 2 V

IBHLO¶

VCC = 3.6 V,

VI = 0 to VCC

500

IBHHO#

VCC = 3.6 V,

VI = 0 to VCC

500

IEX||

VCC = 3 V,

VO = 5.5 V

125

IOZ(PU/PD)

VCC

1.2 V, VO = 0.5 V to VCC,

VI = GND or VCC, OE = don't care

100

IOZH

VCC = 3 6 V

VO = 3 V,

IOZH

VCC = 3.6 V

VI = 0.8 V or 2 V

IOZL

VCC = 3 6 V

VO = 0.5 V,

IOZL

VCC = 3.6 V

VI = 0.8 V or 2 V

VCC = 3.6 V,

Outputs high

0.07

0.1

0.07

0.1

ICC

VCC = 3.6 V,
IO = 0,

Outputs low

3.2

VI = VCC or GND

Outputs disabled

0.07

0.1

0.07

0.1

ICC

VCC = 3 V to 3.6 V, One input at VCC 0.6 V,
Other inputs at VCC or GND

0.4

VCC = 3.3 V,

VI = 3.3 V or 0

3.5

VCC = 3.3 V,

VO = 3.3 V or 0

All typical values are at VCC = 3.3 V, TA = 25

The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and

then raising it to VIL max.

§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and

then lowering it to VIH min.

¶ An external driver must source at least IBHLO to switch this node from low to high.

# An external driver must sink at least IBHHO to switch this node from high to low.

|| Current into an output in the high state when VO > VCC

High-impedance state during power up or power down

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

SN54ALVTH16374, SN74ALVTH16374

2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCES068F JUNE 1996 REVISED JANUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range, V

= 2.5 V

0.2 V

(unless otherwise noted) (see Figure 1)

SN54ALVTH16374

SN74ALVTH16374

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

150

MHz

Pulse duration, CLK high or low

1.5

Setup time data before CLK

Data high

1.1

tsu

Setup time, data before CLK

Data low

1.4

1.3

Hold time data after CLK

Data high

0.6

0.5

Hold time, data after CLK

Data low

0.9

0.8

timing requirements over recommended operating free-air temperature range, V

= 3.3 V

0.3 V

(unless otherwise noted) (see Figure 2)

SN54ALVTH16374

SN74ALVTH16374

UNIT

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

250

MHz

Pulse duration, CLK high or low

1.5

Setup time data before CLK

Data high

1.1

tsu

Setup time, data before CLK

Data low

1.6

1.5

Hold time data after CLK

Data high

0.6

0.5

Hold time, data after CLK

Data low

1.1

switching characteristics over recommended operating free-air temperature range, C

= 30 pF,

= 2.5 V

0.2 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

SN54ALVTH16374

SN74ALVTH16374

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

MAX

MIN

MAX

UNIT

fmax

150

MHz

tPLH

CLK

1.4

3.9

1.5

3.8

tPHL

CLK

1.4

3.9

1.5

3.8

tPZH

4.2

4.1

tPZL

3.8

3.7

tPHZ

1.7

4.3

1.8

4.2

tPLZ

3.5

3.4

switching characteristics over recommended operating free-air temperature range, C

= 50 pF,

= 3.3 V

0.3 V (unless otherwise noted) (see Figure 2)

PARAMETER

FROM

SN54ALVTH16374

SN74ALVTH16374

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

MAX

MIN

MAX

UNIT

fmax

250

MHz

tPLH

CLK

3.4

3.2

tPHL

CLK

3.3

3.2

tPZH

3.9

3.8

tPZL

3.4

3.3

tPHZ

4.7

4.6

tPLZ

4.4

4.2

SN54ALVTH16374, SN74ALVTH16374
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCES068F JUNE 1996 REVISED JANUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 2.5 V

0.2 V

VCC/2

VOH

VOL

tsu

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Open

GND

500

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2

VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + 0.15 V

VOH 0.15 V

0 V

VCC

0 V

VCC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

VCC

GND

TEST

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, ZO = 50

, tr

2 ns, tf

2 ns.

D. The outputs are measured one at a time with one transition per measurement.

0 V

VCC

VCC/2

tPHL

VCC/2

VCC

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

tPLH

VCC

Figure 1. Load Circuit and Voltage Waveforms

SN54ALVTH16374, SN74ALVTH16374

2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCES068F JUNE 1996 REVISED JANUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 3.3 V

0.3 V

VOH

VOL

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Open

GND

500

tPLH

tPHL

Output Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

3 V

0 V

VOH

VOL

0 V

VOL + 0.3 V

VOH 0.3 V

0 V

3 V

0 V

Input

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Timing

Input

Data

Input

Output

Input

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

6 V

GND

TEST

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

10 MHz, ZO = 50

, tr

2.5 ns, tf

2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

6 V

1.5 V

0 V

3 V

1.5 V

Figure 2. Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

74ALVTH16374GRE4

ACTIVE

TSSOP

DGG

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

74ALVTH16374VRE4

ACTIVE

TVSOP

DGV

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

74ALVTH16374ZQLR

ACTIVE

VFBGA

ZQL

1000 Green (RoHS &

no Sb/Br)

SNAGCU

Level-1-260C-UNLIM

SN74ALVTH16374DL

ACTIVE

SSOP

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

SN74ALVTH16374DLR

ACTIVE

SSOP

1000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

SN74ALVTH16374GR

ACTIVE

TSSOP

DGG

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

SN74ALVTH16374KR

ACTIVE

VFBGA

GQL

1000

TBD

SNPB

Level-1-240C-UNLIM

SN74ALVTH16374VR

ACTIVE

TVSOP

DGV

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

4-Oct-2005

Addendum-Page 1

MECHANICAL DATA

MSSO001C JANUARY 1995 REVISED DECEMBER 2001

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

DL (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

4040048 / E 12/01

48 PINS SHOWN

0.730

(18,54)

0.720

(18,29)

0.370

(9,40)

(9,65)

0.380

Gage Plane

DIM

0.420 (10,67)
0.395 (10,03)

A MIN

A MAX

0.010 (0,25)

PINS **

0.630

(16,00)

(15,75)

0.620

0.010 (0,25)

Seating Plane

0.020 (0,51)

0.040 (1,02)

0.008 (0,203)

0.0135 (0,343)

0.008 (0,20) MIN

0.110 (2,79) MAX

0.299 (7,59)
0.291 (7,39)

0.004 (0,10)

0.005 (0,13)

0.025 (0,635)

 8

0.005 (0,13)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118

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2005, Texas Instruments Incorporated

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