www.ti.com
FEATURES
3
2
4
5
1
OE
V
CC
Y
A
GND
DBV PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
5
1
OE
V
CC
Y
A
GND
3
2
4
5
1
OE
V
CC
Y
A
GND
OE
GND
V
CC
Y
A
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
1
4
2
3
5
DESCRIPTION/ORDERING INFORMATION
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(
A)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time - ns
V
oltage - V
AUP1G08 data at C
L
= 15 pF
Output
Input
Switching Characteristics
at 25 MHz
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E JULY 2004 REVISED JULY 2005
Available in the Texas Instruments
Wide Operating V
CC
Range of 0.8 V to 3.6 V
NanoStarTM and NanoFreeTM Packages
Optimized for 3.3-V Operation
Low Static-Power Consumption
3.6-V I/O Tolerant to Support Mixed-Mode
(I
CC
= 0.0
A Max)
Signal Operation
Low Dynamic-Power Consumption
t
pd
= 4.6 ns Max at 3.3 V
(C
pd
= 4 pF Typ at 3.3 V)
Suitable for Point-to-Point Applications
Low Input Capacitance (C
i
= 1.5 pF Typ)
Latch-Up Performance Exceeds 100 mA Per
Low Noise Overshoot and Undershoot
JESD 78, Class II
<10% of V
CC
ESD Performance Tested Per JESD 22
Input-Disable Feature Allows Floating Input
2000-V Humna-Body Model
Conditions
(A114-B, Class II)
I
off
Supports Partial-Power-Down Mode
200-V Machine Model (A115-A)
Operation
1000-V Charged-Device Model (C101)
Input Hysteresis Allows Slow Input Transition
ESD Protection Exceeds
5000 V With
and Better Switching Noise Immunity at Input
Human-Body Model
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire V
CC
range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
xxxx
Figure 1. AUP The Lowest-Power Family
Figure 2. Excellent Signal Integrity
xxx
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20042005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
LOGIC DIAGRAM (POSITIVE LOGIC)
A
Y
OE
1
2
4
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E JULY 2004 REVISED JULY 2005
This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high. This device has the input-disable feature, which allows floating input signals.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
(2)
NanoStarTM WCSP (DSBGA)
SN74AUP1G125YEPR
0.23-mm Large Bump YEP
Reel of 3000
_ _ _ HM _
NanoStarTM WCSP (DSBGA)
0.23-mm Large Bump YZP
SN74AUP1G125YZPR
(Pb-free)
40
C to 85
C
Reel of 3000
SN74AUP1G125DBVR
SOT (SOT-23) DBV
H25_
Reel of 250
SN74AUP1G125DBVT
Reel of 3000
SN74AUP1G125DCKR
SOT (SC-70) DCK
Reel of 250
SN74AUP1G125DCKT
HM_
SOT (SOT-553) DRL
Reel of 4000
SN74AUP1G125DRLR
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
L
H
H
L
L
L
H
X
(1)
Z
(1)
Floating inputs allowed.
2
www.ti.com
Absolute Maximum Ratings
(1)
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E JULY 2004 REVISED JULY 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
0.5
4.6
V
V
I
Input voltage range
(2)
0.5
4.6
V
V
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
0.5
4.6
V
V
O
Output voltage range in the high or low state
(2)
0.5
V
CC
+ 0.5
V
I
IK
Input clamp current
V
I
< 0
50
mA
I
OK
Output clamp current
V
O
< 0
50
mA
I
O
Continuous output current
20
mA
Continuous current through V
CC
or GND
50
mA
DBV package
206
DCK package
252
JA
Package thermal impedance
(3)
C/W
DRL package
142
YEP/YZP package
132
T
stg
Storage temperature range
65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The package thermal impedance is calculated in accordance with JESD 51-7.
3
www.ti.com
Recommended Operating Conditions
(1)
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E JULY 2004 REVISED JULY 2005
MIN
MAX
UNIT
V
CC
Supply voltage
0.8
3.6
V
V
CC
= 0.8 V
V
CC
3.6
V
CC
= 1.1 V to 1.95 V
0.65
V
CC
3.6
V
IH
High-level input voltage
V
V
CC
= 2.3 V to 2.7 V
1.6
3.6
V
CC
= 3 V to 3.6 V
2
3.6
V
CC
= 0.8 V
0
V
CC
= 1.1 V to 1.95 V
0
0.35
V
CC
V
IL
Low-level input voltage
V
V
CC
= 2.3 V to 2.7 V
0
0.7
V
CC
= 3 V to 3.6 V
0
0.9
Active state
0
V
CC
V
O
Output voltage
V
3-state
0
3.6
V
CC
= 0.8 V
20
A
V
CC
= 1.1 V
1.1
V
CC
= 1.4 V
1.7
I
OH
High-level output current
V
CC
= 1.65 V
1.9
mA
V
CC
= 2.3 V
3.1
V
CC
= 3 V
4
V
CC
= 0.8 V
20
A
V
CC
= 1.1 V
1.1
V
CC
= 1.4 V
1.7
I
OL
Low-level output current
V
CC
= 1.65 V
1.9
mA
V
CC
= 2.3 V
3.1
V
CC
= 3 V
4
t/
v
Input transition rise or fall rate
V
CC
= 0.8 V to 3.6 V
200
ns/V
T
A
Operating free-air temperature
40
85
C
(1)
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow of Floating CMOS Inputs, literature number SCBA004.
4
www.ti.com
Electrical Characteristics
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E JULY 2004 REVISED JULY 2005
over recommended operating free-air temperature range (unless otherwise noted)
T
A
= 25
C
T
A
= 40
C to 85
C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
TYP
MAX
MIN
MAX
I
OH
= 20
A
0.8 V to 3.6 V
V
CC
0.1
V
CC
0.1
I
OH
= 1.1 mA
1.1 V
0.75
V
CC
0.7
V
CC
I
OH
= 1.7 mA
1.4 V
1.11
1.03
I
OH
= 1.9 mA
1.65 V
1.32
1.3
V
OL
V
I
OH
= 2.3 mA
2.05
1.97
2.3 V
I
OH
= 3.1 mA
1.9
1.85
I
OH
= 2.7 mA
2.72
2.67
3 V
I
OH
= 4 mA
2.6
2.55
I
OL
= 20
A
0.8 V to 3.6 V
0.1
0.1
I
OL
= 1.1 mA
1.1 V
0.3
V
CC
0.3
V
CC
I
OL
= 1.7 mA
1.4 V
0.31
0.37
I
OL
= 1.9 mA
1.65 V
0.31
0.35
V
OL
V
I
OL
= 2.3 mA
0.31
0.33
2.3 V
I
OL
= 3.1 mA
0.44
0.45
I
OL
= 2.7 mA
0.31
0.33
3 V
I
OL
= 4 mA
0.44
0.45
A or OE
I
I
V
I
= GND to 3.6 V
0 V to 3.6 V
0.1
0.5
A
input
I
off
V
I
or V
O
= 0 V to 3.6 V
0 V
0.2
0.6
A
I
off
V
I
or V
O
= 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
A
I
OZ
V
O
= V
CC
or GND
3.6 V
0.5
A
V
I
= GND or (V
CC
to 3.6 V),
I
CC
0.8 V to 3.6 V
0.5
0.9
A
OE = GND, I
O
= 0
A input
40
50
V
I
= V
CC
0.6 V
(1)
,
3.3 V
I
O
= 0
OE input
110
120
I
CC
A
V
I
= GND to 3.6 V,
All inputs
0.8 V to 3.6 V
0
0
OE = V
CC
(2)
0 V
1.5
C
i
V
I
= V
CC
or GND
pF
3.6 V
1.5
C
o
V
O
= V
CC
or GND
3.6 V
3
pF
(1)
One input at V
CC
0.6 V, other input at V
CC
or GND
(2)
To show I
CC
is very low when the input-disable feature is enabled
5
www.ti.com
Switching Characteristics
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E JULY 2004 REVISED JULY 2005
over recommended operating free-air temperature range, C
L
= 5 pF (unless otherwise noted) (see
Figure 3
and
Figure 4
)
T
A
= 40
C
T
A
= 25
C
FROM
TO
to 85
C
PARAMETER
V
CC
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
0.8 V
18.1
1.2 V
0.1 V
4.3
7.4
12.6
2.7
15.3
1.5 V
0.1 V
3.3
5.2
8.5
1
10.2
t
pd
A
Y
ns
1.8 V
0.15 V
2.6
4.1
6.8
1.3
8.3
2.5 V
0.2 V
2
2.9
4.7
1.1
5.8
3.3 V
0.3 V
1.7
2.4
3.8
1
4.6
0.8 V
19.1
1.2 V
0.1 V
5.1
9.3
15.9
3.6
19.2
1.5 V
0.1 V
4.1
6.6
10.5
2.5
12.7
t
en
OE
Y
ns
1.8 V
0.15 V
3.2
5.3
8.7
2.1
10.3
2.5 V
0.2 V
2.5
3.8
6
1.6
7.2
3.3 V
0.3 V
2.1
3.2
4.9
1.4
5.9
0.8 V
12.1
1.2 V
0.1 V
2.4
4.1
6.9
2.2
7.7
1.5 V
0.1 V
1.8
2.9
4.5
1.7
5.1
t
dis
OE
Y
ns
1.8 V
0.15 V
1
2.9
4.3
1.5
4.7
2.5 V
0.2 V
1
1.8
2.7
1
3.3
3.3 V
0.3 V
1.2
2.2
3.2
1.1
4
6
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Switching Characteristics
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E JULY 2004 REVISED JULY 2005
over recommended operating free-air temperature range, C
L
= 10 pF (unless otherwise noted) (see
Figure 3
and
Figure 4
)
T
A
= 40
C
T
A
= 25
C
FROM
TO
to 85
C
PARAMETER
V
CC
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
0.8 V
20.5
13.7
1.2 V
0.1 V
4.6
8.4
9.3
3.6
16.6
1.5 V
0.1 V
3.5
5.9
7.5
2.4
11.1
t
pd
A or B
Y
ns
1.8 V
0.15 V
3.9
4.7
5.3
1.3
9.1
2.5 V
0.2 V
2.3
3.4
4.3
1.6
6.4
3.3 V
0.3 V
2.1
2.8
1.4
5.2
0.8 V
21.8
16.8
1.2 V
0.1 V
4.9
10.2
11.2
4.4
20.2
1.5 V
0.1 V
3.9
7.3
9.2
3.3
13.5
t
en
OE
Y
ns
1.8 V
0.15 V
3.4
5.8
6.4
2.7
11
2.5 V
0.2 V
2.5
4.3
5.4
2.1
7.8
3.3 V
0.3 V
2.1
3.7
1.9
6.4
0.8 V
13
1.2 V
0.1 V
3.8
6.6
11.7
1.2
14
1.5 V
0.1 V
2.2
4.7
7.9
1.3
9.3
t
dis
OE
Y
ns
1.8 V
0.15 V
2.4
4.4
6.4
2.2
7.5
2.5 V
0.2 V
1.3
3.1
4.9
1.2
5.4
3.3 V
0.3 V
1.9
3.4
5
1.9
5.6
7
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
M
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
1 M
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
V
I
0 V
Input
Output
Output
NOTES: A. C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
, t
r
/t
f
= 3 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. t
PLH
and t
PHL
are the same as t
pd
.
E. All parameters and waveforms are not applicable to all devices.
V
M
V
M
V
M
V
M
V
M
5, 10, 15, 30 pF
V
CC
/2
V
CC
V
CC
= 1.2 V
0.1 V
V
CC
= 0.8 V
V
CC
= 1.5 V
0.1 V
V
CC
= 1.8 V
0.15 V
V
CC
= 2.5 V
0.2 V
V
CC
= 3.3 V
0.3 V
5, 10, 15, 30 pF
V
CC
/2
V
CC
5, 10, 15, 30 pF
V
CC
/2
V
CC
5, 10, 15, 30 pF
V
CC
/2
V
CC
C
L
V
M
V
I
5, 10, 15, 30 pF
V
CC
/2
V
CC
5, 10, 15, 30 pF
V
CC
/2
V
CC
t
h
t
su
Data Input
Timing Input
V
CC
0 V
V
CC
0 V
0 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
V
CC
/2
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E JULY 2004 REVISED JULY 2005
(Propagation Delays, Setup and Hold Times, and Pulse Duration)
Figure 3. Load Circuit and Voltage Waveforms
8
www.ti.com
PARAMETER MEASUREMENT INFORMATION
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
, t
r
/t
f
= 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. All parameters and waveforms are not applicable to all devices.
5, 10, 15, 30 pF
V
CC
/2
V
CC
0.15 V
V
CC
= 1.2 V
0.1 V
V
CC
= 0.8 V
V
CC
= 1.5 V
0.1 V
V
CC
= 1.8 V
0.15 V
V
CC
= 2.5 V
0.2 V
V
CC
= 3.3 V
0.3 V
5, 10, 15, 30 pF
V
CC
/2
V
CC
0.1 V
5, 10, 15, 30 pF
V
CC
/2
V
CC
0.1 V
5, 10, 15, 30 pF
V
CC
/2
V
CC
0.1 V
C
L
V
M
V
I
V
5, 10, 15, 30 pF
V
CC
/2
V
CC
0.15 V
5, 10, 15, 30 pF
V
CC
/2
V
CC
0.3 V
Output
Waveform 1
S1 at 2
V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CC
0 V
V
OL
+ V
V
OH
- V
0 V
V
CC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
/t
PZL
t
PHZ
/t
PZH
2
V
CC
GND
TEST
S1
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
GND
5 k
5 k
2
V
CC
SN74AUP1G125
LOW-POWER SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
SCES595E JULY 2004 REVISED JULY 2005
(Enable and Disable Times)
Figure 4. Load Circuit and Voltage Waveforms
9
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74AUP1G125DBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AUP1G125DBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AUP1G125DCKRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AUP1G125DCKTE4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AUP1G125DRLRG4
ACTIVE
SOP
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G125DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G125DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G125DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G125DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G125DRLR
ACTIVE
SOP
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G125YZPR
ACTIVE
WCSP
YZP
5
3000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
10-Oct-2005
Addendum-Page 1
MECHANICAL DATA
MPDS025C FEBRUARY 1997 REVISED FEBRUARY 2002
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,10
M
0,10
0,65
0
8
0,46
0,26
0,13 NOM
4093553-2/D 01/02
0,15
0,30
1,40
1,10
2,40
1,80
4
5
2,15
1,85
1
3
1,10
0,80
0,10
0,00
Seating Plane
0,15
Gage Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2005, Texas Instruments Incorporated
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