SN74CBT16210C
20 BIT FET BUS SWITCH
5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
SCDS115C - JANUARY 2003 - REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
Undershoot Protection for Off-Isolation on
A and B Ports Up To -2 V
D
Bidirectional Data Flow, With Near-Zero
Propagation Delay
D
Low ON-State Resistance (r
on
)
Characteristics (r
on
= 3
Typical)
D
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(C
io(OFF)
= 5.5 pF Typical)
D
Data and Control Inputs Provide
Undershoot Clamp Diodes
D
Low Power Consumption
(I
CC
= 3
A Max)
D
V
CC
Operating Range From 4 V to 5.5 V
D
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II)
- 1000-V Charged-Device Model (C101)
D
Supports Both Digital and Analog
Applications: PCI Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
description/ordering information
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP - DL
Tube
SN74CBT16210CDL
CBT16210C
SSOP - DL
Tape and reel
SN74CBT16210CDLR
CBT16210C
-40
C to 85
C
TSSOP - DGG
Tube
SN74CBT16210CDGG
CBT16210C
-40 C to 85 C
TSSOP - DGG
Tape and reel
SN74CBT16210CDGGR
CBT16210C
TVSOP - DGV
Tape and reel
SN74CBT16210CDGVR
CY210C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC - No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
1A1
1A2
1A3
1A4
1A5
1A6
GND
1A7
1A8
1A9
1A10
2A1
2A2
V
CC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments.
SN74CBT16210C
20 BIT FET BUS SWITCH
5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
SCDS115C - JANUARY 2003 - REVISED OCTOBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The SN74CBT16210C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r
on
),
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT16210C provides protection for undershoot up to -2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT16210C is organized as two 10-bit bus switches with separate output-enable (1OE, 2OE) inputs.
It can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE is low, the associated 10-bit
bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 10-bit bus switch is OFF, and the high-impedance state exists between the A and
B ports.
This device is fully specified for partial-power-down applications using I
off
. The I
off
feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each 10-bit bus switch)
INPUT
INPUT/OUTPUT
FUNCTION
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
logic diagram (positive logic)
1A1
SW
1B1
1A10
1OE
SW
1B10
2A1
SW
2B1
2A10
2OE
SW
2B10
2
12
48
13
24
47
46
36
35
25
SN74CBT16210C
20 BIT FET BUS SWITCH
5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
SCDS115C - JANUARY 2003 - REVISED OCTOBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simplified schematic, each FET switch (SW)
A
EN
B
EN is the internal enable signal applied to the switch.
Undershoot
Protection Circuit
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input voltage range, V
IN
(see Notes 1 and 2)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, V
I/O
(see Notes 1, 2, and 3)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input clamp current, I
IK
(V
IN
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port clamp current, I
I/OK
(V
I/O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-state switch current, I
I/O
(see Note 4)
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND terminals
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 5): DGG package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
63
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
MAX
UNIT
VCC
Supply voltage
4
5.5
V
VIH
High-level control input voltage
2
5.5
V
VIL
Low-level control input voltage
0
0.8
V
VI/O
Data input/output voltage
0
5.5
V
TA
Operating free-air temperature
-40
85
C
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74CBT16210C
20 BIT FET BUS SWITCH
5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
SCDS115C - JANUARY 2003 - REVISED OCTOBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
Control inputs
VCC = 4.5 V,
IIN = -18 mA
-1.8
V
VIKU
Data inputs
VCC = 5 V,
0 mA
>
II
-50 mA,
VIN = VCC or GND,
Switch OFF
-2
V
IIN
Control inputs
VCC = 5.5 V,
VIN = VCC or GND
1
A
IOZ
VCC = 5.5 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
10
A
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0
10
A
ICC
VCC = 5.5 V,
II/O = 0,
VIN = VCC or GND,
Switch ON or OFF
3
A
ICC
Control inputs
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
2.5
mA
Cin
Control inputs
VIN = 3 V or 0
4.5
pF
Cio(OFF)
VI/O = 3 V or 0,
Switch OFF,
VIN = VCC or GND
5.5
pF
Cio(ON)
VI/O = 3 V or 0,
Switch ON,
VIN = VCC or GND
14.5
pF
VCC = 4 V,
TYP at VCC = 4 V
VI = 2.4 V,
IO = -15 mA
8
12
ron
VI = 0
IO = 64 mA
3
6
ron
VCC = 4.5 V
VI = 0
IO = 30 mA
3
6
VCC = 4.5 V
VI = 2.4 V,
IO = -15 mA
5
10
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25
C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4 V
VCC = 5 V
0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
tpd#
A or B
B or A
0.24
0.15
ns
ten
OE
A or B
6.5
1.5
6
ns
tdis
OE
A or B
6.5
1.5
6
ns
# The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
SN74CBT16210C
20 BIT FET BUS SWITCH
5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
SCDS115C - JANUARY 2003 - REVISED OCTOBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
undershoot characteristics (see Figures 1 and 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOUTU
VCC = 5.5 V,
Switch OFF,
VIN = VCC or GND
2
VOH-0.3
V
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25
C.
Figure 1. Device Test Setup
50
VS
VCC
11 V
100 k
100 k
10 pF
DUT
Input
Generator
Ax
Bx
Figure 2. Transient Input Voltage (V
I
) and Output
Voltage (V
OUTU
) Waveforms
(Switch OFF)
-2 V
5.5 V
10 %
20 ns
10 %
90 %
90 %
2 ns
2 ns
VOH - 0.3
VOH
Output
(VOUTU)
Input
(Open
Socket)
SN74CBT16210C
20 BIT FET BUS SWITCH
5 V BUS SWITCH WITH 2 V UNDERSHOOT PROTECTION
SCDS115C - JANUARY 2003 - REVISED OCTOBER 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
CL
(see Note A)
TEST CIRCUIT
S1
7 V
Open
GND
RL
RL
tPLH
tPHL
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + V
VOH - V
0 V
Output
Control
(VIN)
3 V
3.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
50
VG1
VCC
DUT
50
VIN
50
VG2
50
VI
TEST
RL
S1
V
CL
5 V
0.5 V
4 V
VCC
VI
tPHZ/tPZH
tPLZ/tPZL
tpd(s)
5 V
0.5 V
4 V
5 V
0.5 V
4 V
Open
Open
7 V
7 V
Open
Open
500
500
500
500
500
500
VCC or GND
VCC or GND
GND
GND
VCC
VCC
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
0.3 V
0.3 V
0.3 V
0.3 V
Output
Control
(VIN)
Input Generator
Input Generator
VO
Figure 3. Test Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74CBT16210CDGGRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74CBT16210CDGVRE4
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CBT16210CDGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CBT16210CDGVR
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CBT16210CDL
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CBT16210CDLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
Addendum-Page 1
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50
4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1
12
24
13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
38
24
16
4,90
5,10
3,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins MO-153
14/16/20/56 Pins MO-194
MECHANICAL DATA
MSSO001C JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040048 / E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
48
28
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0
8
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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www.ti.com/audio
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dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2005, Texas Instruments Incorporated
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