18-Bit Registered Transceivers
CY74FCT16500T
CY74FCT162500T
SCCS056 - August 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
FCT-C speed at 4.6 ns
Power-off disable outputs permits live insertion
Edge-rate control circuitry for significantly improved
noise characteristics
Typical output skew < 250 ps
ESD > 2000V
TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
Industrial temperature range of
-
40C to +85C
V
CC
= 5V
10%
CY74FCT16500T Features:
64 mA sink current, 32 mA source current
Typical V
OLP
(ground bounce) <1.0V at V
CC
= 5V,
T
A
= 25C
CY74FCT162500T Features:
Balanced 24 mA output drivers
Reduced system switching noise
Typical V
OLP
(ground bounce) <0.6V at V
CC
= 5V,
T
A
= 25C
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched, or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
HIGH-to-LOW transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with power-off
disable feature that allows live insertion of boards.
The
CY74FCT16500T
is
ideally
suited
for
driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162500T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162500T is ideal for driving transmission lines.
GND
Logic Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
36
35
OEAB
34
SSOP/TSSOP
Top View
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
LEAB
A
1
A
2
A
3
B
1
B
2
B
3
GND
GND
GND
V
CC
A
6
A
7
A
4
A
5
B
4
B
5
B
6
B
7
V
CC
GND
A
10
A
11
A
8
A
9
B
8
B
9
B
11
B
12
GND
A
12
V
CC
A
16
GND
A
14
V
CC
A
15
A
17
FCT16500-1
TO 17 OTHER CHANNELS
LEAB
OEBA
LEBA
CLKAB
CLKBA
OEAB
C
D
C
D
C
D
C
D
A
1
B
1
25
26
27
28
49
52
51
50
A
13
OEBA
LEBA
GND
A
18
CLKAB
53
56
55
54
B
10
GND
B
14
B
15
B
13
B
16
B
17
GND
B
18
CLKBA
FCT16500-2
CY74FCT16500T
CY74FCT162500T
2
Maximum Ratings
[5, 6]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ....................... Com'l
-
55
C to +125
C
Ambient Temperature with
Power Applied................................... Com'l
-
55
C to +125
C
DC Input Voltage
.................................................-
0.5V to +7.0V
DC Output Voltage
..............................................-
0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)
...........................-
60 to +120 mA
Power Dissipation .......................................................... 1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Pin Summary
Name
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input (Active LOW)
CLKBA
B-to-A Clock Input (Active LOW)
A
A-to-B Data Inputs or B-to-A Three-State Outputs
B
B-to-A Data Inputs or A-to-B Three-State Outputs
Function Table
[1, 2]
Inputs
Outputs
OEAB
LEAB
CLKAB
A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
H
X
B
[3]
H
L
L
X
B
[4]
Operating Range
Range
Ambient
Temperature
V
CC
Industrial
-
40
C to +85
C
5V
10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
[7]
Max.
Unit
V
IH
Input HIGH Voltage
2.0
V
V
IL
Input LOW Voltage
0.8
V
V
H
Input Hysteresis
[8]
100
mV
V
IK
Input Clamp Diode Voltage
V
CC
=Min., I
IN
=
-
18 mA
-
0.7
-
1.2
V
I
IH
Input HIGH Current
V
CC
=Max., V
I
=V
CC
1
A
I
IL
Input LOW Current
V
CC
=Max., V
I
=GND.
1
A
I
OZH
High Impedance Output Current
(Three-State Output pins)
V
CC
=Max., V
OUT
=2.7V
1
A
I
OZL
High Impedance Output Current
(Three-State Output pins)
V
CC
=Max., V
OUT
=0.5V
1
A
I
OS
Short Circuit Current
[9]
V
CC
=Max., V
OUT
=GND
-
80
-
140
-
200
mA
I
O
Output Drive Current
[9]
V
CC
=Max., V
OUT
=2.5V
-
50
-
180
mA
I
OFF
Power-Off Disable
V
CC
=0V, V
OUT
4.5V
[10]
1
A
Notes:
1.
H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care. Z = HIGH Impedance.
= HIGH-to-LOW Transition.
2.
A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3.
Output level before the indicated steady-state input conditions were established.
4.
Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.
5.
Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
6.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
7.
Typical values are at V
CC
= 5.0V, T
A
= +25C ambient.
8.
This parameter is specified but not tested.
9.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
10. Tested at +25C.
CY74FCT16500T
CY74FCT162500T
3
Output Drive Characteristics for CY74FCT16500T
Parameter
Description
Test Conditions
Min.
Typ.
[7]
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
=Min., I
OH
=
-
3 mA
2.5
3.5
V
V
CC
=Min., I
OH
=
-
15 mA
2.4
3.5
V
CC
=Min., I
OH
=
-
32 mA
2.0
3.0
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
=64 mA
0.2
0.55
V
Output Drive Characteristics for CY74FCT162500T
Parameter
Description
Test Conditions
Min.
Typ.
[7]
Max.
Unit
I
ODL
Output LOW Current
[9]
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
60
115
150
mA
I
ODH
Output HIGH Current
[9]
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
-
60
-
115
-
150
mA
V
OH
Output HIGH Voltage
V
CC
=Min., I
OH
=
-
24 mA
2.4
3.3
V
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
=24 mA
0.3
0.55
V
Capacitance
[8]
(T
A
= +25C, f = 1.0 MHz)
Parameter
Description
Test Conditions
Typ.
[7]
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
4.5
6.0
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8.0
pF
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.
[7]
Max.
Unit
I
CC
Quiescent Power Supply Current V
CC
=Max.
V
IN
0.2V,
V
IN
V
CC
-
0.2V
5
500
A
I
CC
Quiescent Power Supply Current
(TTL inputs HIGH)
V
CC
=Max.
V
IN
=3.4V
[11]
0.5
1.5
mA
I
CCD
Dynamic Power Supply
Current
[12]
V
CC
=Max., One Input Toggling,
50%DutyCycle,OutputsOpen,
OEAB=OEBA=V
CC
or GND
V
IN
=V
CC
or
V
IN
=GND
75
120
A/MHz
I
C
Total Power Supply Current
[13]
V
CC
=Max., f
0
=10 MHz
(CLKAB), f
1
=5 MHz, 50% Duty
Cycle, Outputs Open,
One Bit Toggling,
OEAB=OEBA=V
CC
LEAB=GND
V
IN
=V
CC
or
V
IN
=GND
0.8
1.7
mA
V
IN
=3.4V or
V
IN
=GND
1.3
3.2
mA
V
CC
=Max., f
0
=10 MHz,
f
1
=2.5 MHz, 50% Duty
Cycle, Outputs Open,
Eighteen Bits Toggling,
OEAB=OEBA=V
CC
LEAB=GND
V
IN
=V
CC
or
V
IN
=GND
3.8
6.5
[14]
mA
V
IN
=3.4V or
V
IN
=GND
8.5
20.8
[14]
mA
Notes:
11. Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
13. I
C
=
I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
=
I
CC
+
I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
=
Quiescent Current with CMOS input levels
I
CC
=
Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
=
Duty Cycle for TTL inputs HIGH
N
T
=
Number of TTL inputs at D
H
I
CCD
=
Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
=
Clock frequency for registered devices, otherwise zero
f
1
=
Input signal frequency
N
1
=
Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
14. Values for these conditions are examples of the I
CC
formula. These limits are specified but not tested.
CY74FCT16500T
CY74FCT162500T
4
Switching Characteristics
Over the Operating Range
[15]
CY74FCT162500AT
CY74FCT16500CT/
CY74FCT162500CT
Fig.
No.
[16]
Parameter
Description
Min.
Max.
Min.
Max.
Unit
f
MAX
CLKAB or CLKBA frequency
150
150
MHz
t
PLH
t
PHL
Propagation Delay
A to B or B to A
1.5
5.1
1.5
4.6
ns
1, 3
t
PLH
t
PHL
Propagation Delay
LEBA to A, LEAB to B
1.5
5.6
1.5
5.3
ns
1, 5
t
PLH
t
PHL
Propagation Delay
CLKBA to A, CLKAB to B
1.5
5.6
1.5
5.3
ns
1, 5
t
PZH
t
PZL
Output Enable Time
OEBA to A, OEAB to B
1.5
6.0
1.5
5.4
ns
1, 7, 8
t
PHZ
t
PLZ
Output Disable Time
OEBA to A, OEAB to B
1.5
5.6
1.5
5.2
ns
1, 7, 8
t
SU
Set-Up Time, HIGH or LOW
A to CLKAB, B to CLKBA
3.0
3.0
ns
9
t
H
Hold Time, HIGH or LOW
A to CLKAB, B to CLKBA
0
0
ns
9
t
SU
Set-Up Time, HIGH or LOW
A to LEAB, B to LEBA
Clock HIGH
3.0
3.0
ns
4
Clock LOW
1.5
1.5
ns
4
t
H
Hold Time, HIGH or LOW
A to LEAB, B to LEBA
1.5
1.5
ns
4
t
W
LEAB or LEBA Pulse Width HIGH
3.0
2.5
ns
5
t
W
CLKAB or CLKBA Pulse Width HIGH or LOW
3.0
3.0
ns
5
t
SK(O)
Output Skew
[17]
0.5
0.5
ns
Ordering Information CY74FCT16500T
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
4.6
CY74FCT16500CTPACT
Z56
56-Lead (240-Mil) TSSOP
Industrial
CY74FCT16500CTPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Ordering Information CY74FCT162500T
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
4.6
CY74FCT162500CTPVC
O56
56-Lead (300-Mil) SSOP
Industrial
74FCT162500CTPVCT
O56
56-Lead (300-Mil) SSOP
5.1
CT74FCT162500ATPVC
O56
56-Lead (300-Mil) SSOP
Industrial
74FCT162500ATPVCT
O56
56-Lead (300-Mil) SSOP
Notes:
15. Minimum limits are specified but not tested on Propagation Delays.
16. See "Parameter Measurement Information" in the General Information section.
17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
CY74FCT16500T
CY74FCT162500T
5
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
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Copyright
2000, Texas Instruments Incorporated
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