18-Bit Registered Transceivers
CY74FCT163501
CY74FCT163H501
SCCS047 - January 1998 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Low power, pin-compatible replacement for LCX and
LPT families
5V tolerant inputs and outputs
24 mA balanced drive outputs
Power-off disable outputs permits live insertion
Edge-rate control circuitry for reduced noise
FCT-C speed at 4.6 ns
Latch-up performance exceeds JEDEC standard no. 17
ESD > 2000V per MIL-STD-883D, Method 3015
Typical output skew < 250ps
Industrial temperature range of 40C to +85C
TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
Typical V
olp
(ground bounce) performance exceeds Mil
Std 883D
V
CC
= 2.7V to 3.6V
CY74FCT163501 Features:
Balanced output drivers: 24 mA
Reduced system switching noise
Typical V
OLP
(ground bounce) <0.6V at V
CC
= 3.3V,
T
A
= 25C
CY74FCT163H501 Features:
Bus hold retains the last active state
Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
Eliminates the need for external pull-up or pull-down
resistors
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with a power-off
disable feature to allow live insertion of boards.
THE CY74FCT163501 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors, as well as provides for
minimal undershoot and reduced ground bounce. The
CY74FCT163501 is ideal for driving transmission lines.
The CY74FCT163H501 is a 24-mA balanced output part, that
has "bus hold" on the data inputs. The device retains the
input's last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
GND
Functional Block Diagram; CY74FCT163501, CY74FCT163H501
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
OEAB
SSOP/TSSOP
Top View
13
14
15
16
17
18
19
20
21
22
23
24
LEAB
A
1
GND
GND
V
CC
GND
GND
FCT163501-1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
GND
25
26
27
28
GND
A
10
A
11
A
12
V
CC
A
13
A
14
A
15
A
16
A
17
A
18
OEBA
LEBA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
B
13
B
14
B
15
V
CC
B
16
B
17
B
18
CLKBA
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
D
C
D
C
D
A
1
B
1
C
D
TO 17 OTHER CHANNELS
FCT163501-2
CY74FCT163501
CY74FCT163H501
2
Maximum Ratings
[6, 7]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature
.....................................-
55
C to +125
C
Ambient Temperature with
Power Applied
..................................................-
55
C to +125
C
DC Input Voltage
.................................................-
0.5V to +7.0V
DC Output Voltage
..............................................-
0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)
...........................-
60 to +120 mA
Power Dissipation .......................................................... 1.0W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
1.
On the 74FCT163H501 these pins have bus hold.
2.
A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
= LOW-to-HIGH Transition
4.
Output level before the indicated steady-state input conditions were established.
5.
Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
6.
Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
7.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
Pin Description
Name
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
A
A-to-B Data Inputs or B-to-A Three-State
Outputs
[1]
B
B-to-A Data Inputs or A-to-B Three-State
Outputs
[1]
Function Table
[2, 3]
Inputs
Outputs
OEAB
LEAB
CLKAB
A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
L
X
B
[4]
H
L
H
X
B
[5]
Operating Range
Range
Ambient
Temperature
V
CC
Industrial
-
40
C to +85
C
2.7V to 3.6V
CY74FCT163501
CY74FCT163H501
3
Electrical Characteristics for Non Bus Hold Devices
Over the Operating Range V
CC
= 2.7V to 3.6V
Parameter
Description
Test Conditions
Min.
Typ.
[8]
Max.
Unit
V
IH
Input HIGH Voltage
All Inputs
2.0
5.5
V
V
IL
Input LOW Voltage
0.8
V
V
H
Input Hysteresis
[9]
100
mV
V
IK
Input Clamp Diode Voltage
V
CC
=Min., I
IN
=18 mA
0.7
1.2
V
I
IH
Input HIGH Current
V
CC
=Max., V
I
=5.5
1
A
I
IL
Input LOW Current
V
CC
=Max., V
I
=GND
1
A
I
OZH
High Impedance Output Current
(Three-State Output pins)
V
CC
=Max., V
OUT
=5.5V
1
A
I
OZL
High Impedance Output Current
(Three-State Output pins)
V
CC
=Max., V
OUT
=GND
1
A
I
OS
Short Circuit Current
[10]
V
CC
=Max., V
OUT
=GND
60
135
240
mA
I
OFF
Power-Off Disable
V
CC
=0V, V
OUT
4.5V
100
A
I
CC
Quiescent Power Supply Current
V
IN
0.2V,
V
IN
>V
CC
0.2V
V
CC
=Max.
0.1
10
A
I
CC
Quiescent Power Supply Current
(TTL inputs HIGH)
V
IN
=V
CC
0.6V
[11]
V
CC
=Max.
2.0
30
A
Notes:
8.
Typical values are at V
CC
=3.3V, T
A
= +25C ambient.
9.
This parameter is specified but not tested.
10. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
11. Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
CY74FCT163501
CY74FCT163H501
4
Electrical Characteristics For Bus Hold Devices
Over the Operating Range V
CC
=2.7V to 3.6V
Parameter
Description
Test Conditions
Min.
Typ.
[8]
Max.
Unit
V
IH
Input HIGH Voltage
All Inputs
2.0
V
CC
V
V
IL
Input LOW Voltage
0.8
V
V
H
Input Hysteresis
[9]
100
mV
V
IK
Input Clamp Diode Voltage
V
CC
=Min., I
IN
=18 mA
0.7
1.2
V
I
IH
Input HIGH Current
V
CC
=Max., V
I
=V
CC
100
A
I
IL
Input LOW Current
V
CC
=Max., V
I
=GND
100
A
I
BBH
I
BBL
Bus Hold Sustain Current on Bus Hold Input
[12]
V
CC
=Min.
V
I
=2.0V
50
A
V
I
=0.8V
+50
A
I
BHHO
I
BHLO
Bus Hold Overdrive Current on Bus Hold Input
[12]
V
CC
=Max., V
I
=1.5V
500
A
I
OZH
High Impedance Output Current
(Three-State Output pins)
V
CC
=Max., V
OUT
=V
CC
1
A
I
OZL
High Impedance Output Current
(Three-State Output pins)
V
CC
=Max., V
OUT
=GND
1
A
I
OS
Short Circuit Current
[10]
V
CC
=Max., V
OUT
=GND
60
135
240
mA
I
OFF
Power-Off Disable
V
CC
=0V, V
OUT
4.5V
100
A
I
CC
Quiescent Power Supply Current
V
IN
0.2V,
V
IN
>V
CC
0.2V
V
CC
=Max.
+40
A
ICC
Quiescent Power supply Current
(TTL inputs HIGH)
V
IN
=V
CC
0.6V
[11]
V
CC
=Max.
+350
A
Electrical Characteristics For Balanced Drive Devices
Over the Operating Range V
CC
=2.7V to 3.6V
Parameter
Description
Test Conditions
Min.
Typ.
[8]
Max.
Unit
I
ODL
Output LOW Dynamic Current
[10]
V
CC
=3.3V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
45
180
mA
I
ODH
Output HIGH Dynamic Current
[10]
V
CC
=3.3V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
45
180
mA
V
OH
Output HIGH Voltage
V
CC
=Min., I
OH
= 0.1 mA
V
CC
0.2
V
V
CC
=3.0V, I
OH
= 8 mA
2.4
[13]
3.0
V
V
CC
=3.0V, I
OH
= 24 mA
2.0
3.0
V
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
= 0.1mA
0.2
V
V
CC
=Min., I
OL
= 24 mA
0.3
0.55
Capacitance
[9]
(T
A
= +25C, f = 1.0 MHz)
Parameter
Description
Test Conditions
Typ.
[8]
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
4.5
6.0
pF
C
OUT
Output Capacitance
V
OUT
= 0V
5.5
8.0
pF
Notes:
12. Pins with bus hold are described in Pin Description.
13. V
OH
=V
CC
0.6V at rated current.
CY74FCT163501
CY74FCT163H501
5
Power Supply Characteristics
Sym.
Parameter
Test Conditions
[14]
Min.
Typ.
[8]
Max.
Unit
I
CCD
Dynamic Power Supply
Current
[15]
V
CC
=Max., Outputs Open
OEAB=OEBA=V
CC
or GND
One Input Toggling,
50% Duty Cycle
V
IN
=V
CC
or
V
IN
=GND
--
75
120
A/
MHz
I
C
Total Power Supply
Current
[16]
V
CC
=Max., Outputs Open
f
0
=10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=V
CC
LEAB = GND, One Bit Toggling
f
1
= 5MHz, 50% Duty Cycle
V
IN
=V
CC
or
V
IN
=GND
--
0.8
1.7
mA
V
IN
=3.4V or
V
IN
=GND
--
1.3
3.2
V
CC
=Max., Outputs Open
f
0
= 10MHz (CLKAB)
50% Duty Cycle
OEAB=OEBA=V
CC
LEAB=GND
Eighteen Bits Toggling
f
1
=2.5MHz, 50% Duty Cycle
V
IN
=V
CC
or
V
IN
=GND
--
3.8
6.5
[17]
V
IN
=3.4V or
V
IN
=GND
--
8.5
20.8
[17]
Notes:
14. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
15. This parameter is not directly testable, but is derived for use in Total Power Supply Current.
16. I
C
=
I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
=
I
CC
+
I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
=
Quiescent Current with CMOS input levels
I
CC
=
Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
=
Duty Cycle for TTL inputs HIGH
N
T
=
Number of TTL inputs at D
H
I
CCD
=
Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
=
Clock frequency for registered devices, otherwise zero
f
1
=
Input signal frequency
N
1
=
Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
17. Values for these conditions are examples of the I
CC
formula. These limits are specified but not tested.
CY74FCT163501
CY74FCT163H501
6
Switching Characteristics
Over the Operating Range V
CC
=3.0V to 3.6V
[18]
CY74FCT163501C
CY74FCT163H501C
Fig.No.
[19]
Parameter
Description
Min.
Max.
Unit
f
MAX
CLKAB or CLKBA frequency
[9]
--
150
MHz
--
t
PLH
t
PHL
Propagation Delay
A to B or B to A
1.5
4.6
ns
1,3
t
PLH
t
PHL
Propagation Delay
LEBA to A, LEAB to B
1.5
5.3
ns
1,5
t
PLH
t
PHL
Propagation Delay
CLKBA to A,
CLKAB to B
1.5
5.3
ns
1,5
t
PZH
t
PZL
Output Enable Time
OEBA to A, OEAB to B
1.5
5.6
ns
1,7,8
t
PHZ
t
PLZ
Output Disable Time
OEBA to A, OEAB to B
1.5
5.2
ns
1,7,8
t
SU
Set-Up Time,
HIGH or LOW
A to CLKAB,
B to CLKBA
3.0
--
ns
4
t
H
Hold Time
HIGH or LOW
A to CLKAB,
B to CLKBA
0
--
ns
4
t
SU
Set-Up Time, HIGH or LOW
A to LEAB,
B to LEBA
Clock LOW
3.0
--
ns
4
Clock HIGH
1.5
--
ns
4
t
H
Hold Time, HIGH or LOW, A to LEAB,
B to LEBA
1.5
--
ns
4
t
W
LEAB or LEBA Pulse Width HIGH
[9]
3.0
--
ns
5
t
W
CLKAB or CLKBA Pulse Width HIGH or LOW
[9]
3.0
--
ns
5
t
SK(O)
Output Skew
[20]
--
0.5
ns
--
Notes:
18. Minimum limits are specified, but not tested, on propagation delays.
19. See "Parameter Measurement Information" in the General Information section.
20. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.
CY74FCT163501
CY74FCT163H501
7
Ordering Information CY74FCT163501T
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
4.6
CY74FCT163501CPACT
Z56
56-Lead (240-Mil) TSSOP
Industrial
CY74FCT163501CPVC/PVCT
O56
56-Lead (300-Mil) SSOP
Ordering Information CY74FCT163H501T
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
4.6
74FCT163H501CPACT
Z56
56-Lead (240-Mil) TSSOP
Industrial
CY74FCT163H501CPVC
O56
56-Lead (300-Mil) SSOP
74FCT163H501CPVCT
O56
56-Lead (300-Mil) SSOP
Package Diagrams
56-Lead Shrunk Small Outline Package O56
CY74FCT163501
CY74FCT163H501
8
Package Diagrams
(continued)
56-Lead Thin Shrunk Small Outline Package Z56
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright
2000, Texas Instruments Incorporated
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