SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Internal Look-Ahead Circuitry for Fast
Counting
D
Carry Output for n-Bit Cascading
D
Synchronous Counting
D
Synchronously Programmable
D
Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages, Ceramic Chip Carriers (FK),
Standard Plastic (N) and Ceramic (J) DIPs
description
These synchronous, presettable, 4-bit decade
and binary counters feature an internal carry
look-ahead circuitry for application in high-speed
counting designs. The SN54ALS162B is a 4-bit
decade counter. The 'ALS161B, 'ALS163B,
'AS161, and 'AS163 devices are 4-bit binary
counters. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that
the outputs change coincidentally with each other
when instructed by the count-enable (ENP, ENT)
inputs and internal gating. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of
the clock input waveform.
These counters are fully programmable; they can
be preset to any number between 0 and 9 or 15.
Because presetting is synchronous, setting up a
low level at the load (LOAD) input disables the
counter and causes the outputs to agree with the
setup data after the next clock pulse, regardless
of the levels of the enable inputs.
The clear function for the 'ALS161B and 'AS161 devices is asynchronous. A low level at the clear (CLR) input
sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear
function for the SN54ALS162B, 'ALS163B, and 'AS163 devices is synchronous, and a low level at CLR sets
all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 ( LLLL ).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ALS161B, SN54ALS162B, SN54ALS163B,
SN54AS161, SN54AS163 . . . J PACKAGE
SN74ALS161B, SN74AS161,
SN74AS163 . . . D OR N PACKAGE
SN74ALS163B . . . D, DB, OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Q
A
Q
B
NC
Q
C
Q
D
A
B
NC
C
D
SN54ALS161B, SN54ALS162B, SN54ALS163B,
SN54AS161, SN54AS163 . . . FK PACKAGE
(TOP VIEW)
CLK
CLR
NC
LOAD
ENT
RCO
ENP
GND
NC
NC No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
produces a high-level pulse while the count is maximum (9 or 15, with Q
A
high). The high-level overflow
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed,
regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for
operation over the full military temperature range of 55
C to 125
C. The SN74ALS161B, SN74ALS163B,
SN74AS161, and SN74AS163 are characterized for operation from 0
C to 70
C.
logic symbols
14
13
12
11
CTRDIV10
LOAD
1, 5D
3
A
4
B
5
C
6
D
5CT=0
1
M2
M1
9
C5/2,3,4+
G3
10
ENT
RCO
15
3CT=9
QA
QB
QC
QD
G4
7
ENP
2
CLK
CLR
SN54ALS162B DECADE COUNTER
WITH SYNCHRONOUS CLEAR
14
13
12
11
CTRDIV16
LOAD
1, 5D
3
A
4
B
5
C
6
D
CT=0
1
M2
M1
9
C5/2,3,4+
G3
10
ENT
RCO
15
3CT=15
QA
QB
QC
QD
G4
7
ENP
2
CLK
CLR
[1]
[2]
[4]
[8]
'ALS161B AND 'AS161 BINARY COUNTERS
WITH DIRECT CLEAR
14
13
12
11
CTRDIV16
LOAD
1, 5D
3
A
4
B
5
C
6
D
5CT=0
1
M2
M1
9
C5/2,3,4+
G3
10
ENT
RCO
15
3CT=15
QA
QB
QC
QD
G4
7
ENP
2
CLK
CLR
'ALS163B AND 'AS163 BINARY COUNTERS
WITH SYNCHRONOUS CLEAR
[1]
[2]
[4]
[8]
[1]
[2]
[4]
[8]
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, and N packages.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
1D
C1
1D
C1
1
9
10
7
2
3
4
5
15
14
13
12
CLR
LOAD
ENT
ENP
CLK
A
B
C
RCO
QA
QB
QC
SN54ALS162B
1D
C1
6
11
QD
D
Pin numbers shown are for the J package.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
1D
C1
1D
C1
1D
C1
1
9
10
7
2
3
4
5
6
15
14
13
12
11
CLR
LOAD
ENT
ENP
CLK
A
B
C
D
RCO
QA
QB
QC
QD
'ALS163B and 'AS163
Pin numbers shown are for the D, DB, J, and N packages.
'ALS161B and 'AS161 synchronous binary counters are similar; however, CLR is asynchronous.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequences
SN54ALS162B
The following sequence is illustrated below:
1.
Clear outputs to zero (SN54ALS162B is synchronous)
2.
Preset to BCD 7
3.
Count to 8, 9, 0, 1, 2, and 3
4.
Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Async
Clear
Sync
Clear
Preset
Count
Inhibit
7
8
9
0
1
2
3
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequences
'ALS161B, 'AS161, 'ALS163B, and 'AS163
The following sequence is illustrated below:
1.
Clear outputs to zero ('ALS161B and 'AS161 are asynchronous; 'ALS163B and 'AS163 are
synchronous.)
2.
Preset to binary 12
3.
Count to 13, 14, 15, 0, 1, and 2
4.
Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Async
Clear
Sync
Clear
Preset
Count
Inhibit
12
13
14
15
0
1
2
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 1): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package
82
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
SN54ALS161B
SN54ALS162B
SN54ALS163B
SN74ALS161B
SN74ALS163B
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.7
0.8
V
IOH
High-level output current
0.4
0.4
mA
IOL
Low-level output current
4
8
mA
TA
Operating free-air temperature
55
125
0
70
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS161B
SN54ALS162B
SN54ALS163B
SN74ALS161B
SN74ALS163B
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = 4.5 V,
II = 18 mA
1.5
1.5
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = 0.4 mA
VCC 2
VCC 2
V
VOL
VCC = 4 5 V
IOL = 4 mA
0.25
0.4
0.25
0.4
V
VOL
VCC = 4.5 V
IOL = 8 mA
0.35
0.5
V
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
VCC = 5.5 V,
VI = 0.4 V
0.2
0.2
mA
IO
VCC = 5.5 V,
VO = 2.25 V
20
112
30
112
mA
ICC
VCC = 5.5 V
12
21
12
21
mA
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating conditions (unless otherwise noted) (see
Figure 1)
SN54ALS161B
SN54ALS162B
SN54ALS163B
SN74ALS161B
SN74ALS163B
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
22
40
MHz
t
Pulse duration
CLR high or low
20
12.5
ns
tw
Pulse duration
'ALS161B
CLR low
20
15
ns
A, B, C, D
50
15
LOAD
20
15
'ALS161B
ENP ENT
25
15
tsu
Setup time, before CLK
SN54ALS162B, 'ALS163B
ENP, ENT
20
15
ns
'ALS161B
CLR inactive
10
10
SN54ALS162B 'ALS163B
CLR low
20
15
SN54ALS162B, 'ALS163B
CLR high
20
10
th
Hold time, all synchronous inputs after CLK
0
0
ns
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Figure 1)
PARAMETER
FROM
TO
SN54ALS161B
SN74ALS161B
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
fmax
22
40
MHz
tPLH
CLK
RCO
5
34
5
20
ns
tPHL
CLK
RCO
5
27
5
20
ns
tPLH
CLK
Any Q
4
19
4
15
ns
tPHL
CLK
Any Q
6
25
6
20
ns
tPLH
ENT
RCO
3
18
3
13
ns
tPHL
ENT
RCO
3
17
3
13
ns
tPHL
CLR
Any Q
8
27
8
24
ns
tPHL
CLR
RCO
11
32
11
23
ns
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
SN54ALS162B
SN54ALS163B
SN74ALS163B
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
fmax
22
40
MHz
tPLH
CLK
RCO
5
25
5
20
ns
tPHL
CLK
RCO
5
25
5
20
ns
tPLH
CLK
Any Q
4
18
4
15
ns
tPHL
CLK
Any Q
6
25
6
20
ns
tPLH
ENT
RCO
3
16
3
13
ns
tPHL
ENT
RCO
3
16
3
13
ns
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
SN54AS161
SN54AS163
SN74AS161
SN74AS163
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
2
2
mA
IOL
Low-level output current
20
20
mA
TA
Operating free-air temperature
55
125
0
70
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54AS161
SN54AS163
SN74AS161
SN74AS163
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = 2 mA
VCC 2
VCC 2
V
VOL
VCC = 4.5 V,
IOL = 20 mA
0.25
0.5
0.25
0.5
V
LOAD
0.3
0.3
II
ENT
VCC = 5.5 V,
VI = 7 V
0.2
0.2
mA
All others
0.1
0.1
LOAD
60
60
IIH
ENT
VCC = 5.5 V,
VI = 2.7 V
40
40
A
All others
20
20
LOAD
1.5
1.5
IIL
ENT
VCC = 5.5 V,
VI = 0.4 V
1
1
mA
All others
0.5
0.5
IO
VCC = 5.5 V,
VO = 2.25 V
30
112
30
112
mA
ICC
VCC = 5.5 V
35
53
35
53
mA
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating conditions (see Figure 1)
SN54AS161
SN54AS163
SN74AS161
SN74AS163
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
65
75
MHz
t
Pulse duration
CLR high or low
7.7
6.7
ns
tw
Pulse duration
'AS161
CLR low
10
8
ns
A, B, C, D
10
8
LOAD
10
8
t
Setup time before CLK
ENP, ENT
10
8
ns
tsu
Setup time, before CLK
'AS161
CLR inactive
10
8
ns
'AS163
CLR low
14
12
'AS163
CLR high (inactive)
10
9
th
Hold time, all synchronous inputs after CLK
2
0
ns
switching characteristics over recommended operating conditions (see Figure 1)
PARAMETER
FROM
TO
SN54AS161
SN74AS161
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
fmax
65*
75
MHz
tPLH
CLK
RCO (with LOAD high)
1
8.5
1
8
ns
tPLH
CLK
RCO (with LOAD low)
3
17.5
3
16.5
ns
tPHL
CLK
RCO
2
14
2
12.5
ns
tPLH
CLK
Any Q
1
7.5
1
7
ns
tPHL
CLK
Any Q
2
14
2
13
ns
tPLH
ENT
RCO
1.5
10
1.5
9
ns
tPHL
ENT
RCO
1
9.5
1
8.5
ns
tPHL
CLR
Any Q
2
14
2
13
ns
tPHL
CLR
RCO
2
14
2
12.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating conditions (see Figure 1)
PARAMETER
FROM
TO
SN54AS163
SN74AS163
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
fmax
65*
75
MHz
tPLH
CLK
RCO (with LOAD high)
1
8.5
1
8
ns
tPLH
CLK
RCO (with LOAD low)
3
17.5
3
16.5
ns
tPHL
CLK
RCO
2
14
2
12.5
ns
tPLH
CLK
Any Q
1
7.5
1
7
ns
tPHL
CLK
Any Q
2
14
2
13
ns
tPLH
ENT
RCO
1.5
10
1.5
9
ns
tPHL
ENT
RCO
1
9.5
1
8.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/ 74ALS AND 54AS/ 74AS DEVICES
tPLZ
tPHL
tPLH
0.3 V
tPZL
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
S1
CL = 50 pF
(see Note A)
7 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
3 V
0 V
0 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
3 V
3 V
0 V
0 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
0 V
VOH
VOL
3 V
In-Phase
Output
0.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VCC
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
500
500
500
500
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
tPHZ
tPZH
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276A DECEMBER 1994 REVISED JULY 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the ripple-mode carry circuit (see Figure 2) and the carry look-ahead circuit
(see Figure 3) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The
'ALS161B, 'AS161, 'ALS163B, and 'AS163 devices count in binary. When additional stages are added, the f
max
decreases in Figure 2, but remains unchanged in Figure 3.
Figure 2. Ripple-Mode Carry Circuit
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LSB
To More Significant Stages
Clear (L)
Count (H)
Disable (L)
Load (L)
Count (H)
Disable (L)
Clock
fmax = 1/(CLK to RCO tPLH) + (ENT to RCO tPLH) (N 2) + (ENT tsu)
Figure 3. Carry Look-Ahead Circuit
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LOAD
C5/T,3,4+
QA
QB
QC
QD
CLR
A
B
C
D
CTR
CT=0
M1
G3
G4
RCO
CLK
ENP
ENT
3CT=MAX
1,5D
LSB
To More Significant Stages
Clear (L)
Count (H)
Disable (L)
Load (L)
Clock
fmax = 1/(CLK to RCO tPLH) + (ENP tsu)
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Copyright
2000, Texas Instruments Incorporated
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