1
Data sheet acquired from Harris Semiconductor
SCHS121D
Features
Buffered Inputs
Typical Propagation Delay: 10ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Pinout
CD54HC30, CD54HCT30 (CERDIP)
CD74HC30 (PDIP, SOIC, SOP, TSSOP)
CD74HCT30 (PDIP, SOIC)
TOP VIEW
Description
The 'HC30 and 'HCT30 each contain an 8-input NAND gate
in one package. They provide the system designer with the
direct implementation of the positive logic 8-input NAND
function. Logic gates utilize silicon gate CMOS technology to
achieve operating speeds similar to LSTTL gates with the
low power consumption of standard CMOS integrated cir-
cuits. All devices have the ability to drive 10 LSTTL loads.
The HCT logic family is functionally pin compatible with the
standard LS logic family.
A
B
C
D
E
F
GND
VCC
NC
H
G
NC
NC
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC30F3A
-55 to 125
14 Ld CERDIP
CD54HCT30F3A
-55 to 125
14 Ld CERDIP
CD74HC30E
-55 to 125
14 Ld PDIP
CD74HC30M
-55 to 125
14 Ld SOIC
CD74HC30MT
-55 to 125
14 Ld SOIC
CD74HC30M96
-55 to 125
14 Ld SOIC
CD74HC30NSR
-55 to 125
14 Ld SOP
CD74HC30PW
-55 to 125
14 Ld TSSOP
CD74HC30PWR
-55 to 125
14 Ld TSSOP
CD74HC30PWT
-55 to 125
14 Ld TSSOP
CD74HCT30E
-55 to 125
14 Ld PDIP
CD74HCT30M
-55 to 125
14 Ld SOIC
CD74HCT30MT
-55 to 125
14 Ld SOIC
CD74HCT30M96
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated.
CD54/74HC30,
CD54/74HCT30
High Speed CMOS Logic
8-Input NAND Gate
[ /Title
(CD54H
C30,
CD74H
C30,
CD74H
CT30)
/Subject
(High
Speed
CMOS
Logic 8-
August 1997 - Revised September 2003
2
Functional Diagram
Logic Symbol
TRUTH TABLE
INPUTS
OUTPUT
A
B
C
D
E
F
G
H
L
X
X
X
X
X
X
X
H
X
L
X
X
X
X
X
X
H
X
X
L
X
X
X
X
X
H
X
X
X
L
X
X
X
X
H
X
X
X
X
L
X
X
X
H
X
X
X
X
X
L
X
X
H
X
X
X
X
X
X
L
X
H
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
L
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant
1
2
3
4
5
6
11
12
A
B
C
D
E
F
G
H
8
Y
Y = ABCDEFGH
8
Y
A
B
C
D
E
F
G
H
1
2
3
4
5
6
11
12
CD54/74HC30, CD54/74HCT30
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Package Thermal Impedance,
JA
(see Note 1)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
o
C/W
M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
o
C/W
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 113
o
C/W
Maximum Junction Temperature (Hermetic Package or Die) . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO +85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
CD54/74HC30, CD54/74HCT30
4
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
2
-
20
-
40
A
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
-0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
-
5.5
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
2
-
20
-
40
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 2)
I
CC
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO +85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HCT Input Loading Table
INPUT
UNIT LOADS
All
0.6
NOTE: Unit Load is
I
CC
limit specified in DC Electrical
Specifications table, e.g. 360
A max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay, Input to
Output (Figure 1)
t
PLH
, t
PHL
C
L
= 50pF
2
-
-
130
-
165
-
195
ns
4.5
-
-
26
-
33
-
39
ns
6
-
-
22
-
28
-
33
ns
Propagation Delay, Data Input to
Output Y
t
PLH
, t
PHL
C
L
= 15pF
5
-
10
-
-
-
-
-
ns
CD54/74HC30, CD54/74HCT30
5
Transition Times (Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C
I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
C
PD
-
5
-
25
-
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
t
RHL
, t
PHL
C
L
= 50pF
4.5
-
-
28
-
35
-
42
ns
Propagation Delay, Data Input to
Output Y
t
PLH
, t
PHL
C
L
= 15pF
5
-
11
-
-
-
-
-
ns
Transition Times (Figure 2)
t
TLH
, t
THL
C
L
= 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
C
I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 3, 4)
C
PD
-
5
-
26
-
-
-
-
-
pF
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per gate.
4. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Switching Specifications
Input t
r
, t
f
= 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Test Circuits and Waveforms
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns
t
f
= 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
t
r
= 6ns
t
f
= 6ns
90%
CD54/74HC30, CD54/74HCT30
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