SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 14 ns
D
4-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
Internal Look-Ahead for Fast Counting
D
Carry Output for n-Bit Cascading
D
Synchronous Counting
D
Synchronously Programmable
SN54HC161 . . . J OR W PACKAGE
SN74HC161 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Q
A
Q
B
NC
Q
C
Q
D
A
B
NC
C
D
SN54HC161 . . . FK PACKAGE
(TOP VIEW)
CLK
CLR
NC
LOAD
ENT
RCO
ENP
GND
NC
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
NC - No internal connection
description/ordering information
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. The 'HC161 devices are 4-bit binary counters. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed
by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output
counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK)
input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube of 25
SN74HC161N
SN74HC161N
Tube of 40
SN74HC161D
SOIC - D
Reel of 2500
SN74HC161DR
HC161
-40
C to 85
C
SOIC - D
Reel of 250
SN74HC161DT
HC161
-40
C to 85
C
SOP - NS
Reel of 2000
SN74HC161NSR
HC161
Tube of 90
SN74HC161PW
TSSOP - PW
Reel of 2000
SN74HC161PWR
HC161
TSSOP - PW
Reel of 250
SN74HC161PWT
HC161
CDIP - J
Tube of 25
SNJ54HC161J
SNJ54HC161J
-55
C to 125
C
CFP - W
Tube of 150
SNJ54HC161W
SNJ54HC161W
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54HC161FK
SNJ54HC161FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the 'HC161 devices is asynchronous. A low level at the clear (CLR) input sets all four of
the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q
A
high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1
9
10
7
3
15
14
CLR
LOAD
ENT
ENP
CLK
A
RCO
QA
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
M1
G2
G4
3D
4R
1, 2T/1C3
4
13
B
QB
M1
G2
G4
3D
4R
1, 2T/1C3
5
12
C
QC
M1
G2
G4
3D
4R
1, 2T/1C3
6
11
D
QD
M1
G2
G4
3D
4R
1, 2T/1C3
2
LD
CK
CK
R
LD
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol, each D/T flip-flop
M1
LD (Load)
Q (Output)
G2
TE (Toggle Enable)
CK (Clock)
G4
3D
4R
1, 2T/1C3
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
TG
TG
TG
TG
TG
TG
CK
LD
TE
LD
LD
D
R
CK
CK
CK
CK
Q
The origins of LD and CK are shown in the logic diagram of the overall device.
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1.
Clear outputs to zero (asynchronous)
2.
Preset to binary 12
3.
Count to 13, 14, 15, 0, 1, and 2
4.
Inhibit
Data
Inputs
Data
Outputs
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
RCO
QA
QB
QC
QD
Async
Clear
Sync
Clear
Preset
Count
Inhibit
12
13
14
15
0
1
2
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
108
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC161
SN74HC161
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VIH
High-level input voltage
VCC = 6 V
4.2
4.2
V
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VIL
Low-level input voltage
VCC = 6 V
1.8
1.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
1000
1000
t/
v
Input transition rise/fall time
VCC = 4.5 V
500
500
ns
t/
v
Input transition rise/fall time
VCC = 6 V
400
400
ns
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC161
SN74HC161
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
1.998
1.9
1.9
IOH = -20
A
4.5 V
4.4
4.499
4.4
4.4
VOH
VI = VIH or VIL
IOH = -20
A
6 V
5.9
5.999
5.9
5.9
V
VOH
VI = VIH or VIL
IOH = -4 mA
4.5 V
3.98
4.3
3.7
3.84
V
IOH = -5.2 mA
6 V
5.48
5.8
5.2
5.34
2 V
0.002
0.1
0.1
0.1
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
VOL
VI = VIH or VIL
IOL = 20
A
6 V
0.001
0.1
0.1
0.1
V
VOL
VI = VIH or VIL
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
V
IOL = 5.2 mA
6 V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
ICC
VI = VCC or 0,
IO = 0
6 V
8
160
80
A
Ci
2 V to 6 V
3
10
10
10
pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
SN54HC161
SN74HC161
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
6
4.2
5
fclock
Clock frequency
4.5 V
31
21
25
MHz
fclock
Clock frequency
6 V
36
25
29
MHz
2 V
80
120
100
CLK high or low
4.5 V
16
24
20
tw
Pulse duration
CLK high or low
6 V
14
20
17
ns
tw
Pulse duration
2 V
80
120
100
ns
CLR low
4.5 V
16
24
20
CLR low
6 V
14
20
17
2 V
150
225
190
A, B, C, or D
4.5 V
30
45
38
A, B, C, or D
6 V
26
38
32
2 V
135
205
170
LOAD low
4.5 V
27
41
34
tsu
Setup time before CLK
LOAD low
6 V
23
35
29
ns
tsu
Setup time before CLK
2 V
170
255
215
ns
ENP, ENT
4.5 V
34
51
43
ENP, ENT
6 V
29
43
37
2 V
125
190
155
CLR inactive
4.5 V
25
38
31
CLR inactive
6 V
21
32
26
2 V
0
0
0
th
Hold time, all synchronous inputs after CLK
4.5 V
0
0
0
ns
th
Hold time, all synchronous inputs after CLK
6 V
0
0
0
ns
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC161
SN74HC161
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
6
14
4.2
5
fmax
4.5 V
31
40
21
25
MHz
fmax
6 V
36
44
25
29
MHz
2 V
83
215
325
270
RCO
4.5 V
24
43
65
54
CLK
RCO
6 V
20
37
55
46
CLK
2 V
80
205
310
255
tpd
Any Q
4.5 V
25
41
62
51
ns
tpd
Any Q
6 V
21
35
53
43
ns
2 V
62
195
295
245
ENT
RCO
4.5 V
17
39
59
49
ENT
RCO
6 V
14
33
50
42
2 V
105
210
315
265
Any Q
4.5 V
21
42
63
53
tPHL
CLR
Any Q
6 V
18
36
54
45
ns
tPHL
CLR
2 V
110
220
330
275
ns
RCO
4.5 V
22
44
66
55
RCO
6 V
19
37
56
47
2 V
38
75
110
95
tt
Any
4.5 V
8
15
22
19
ns
tt
Any
6 V
6
13
19
16
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load
60
pF
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%
50%
10%
10%
90%
90%
VCC
VCC
0 V
0 V
tr
tf
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
VCC
0 V
50%
50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%
50%
10%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
50%
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit
counter. The 'HC161 devices count in binary. Virtually any count mode (modulo-N, N
1
-to-N
2
, N
1
-to-maximum)
can be used with this fast look-ahead circuit.
The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25
C and
4.5-V V
CC
). The reason for this is that there is a glitch that is produced on the second stage's RCO and every
succeeding stage's RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in
addition to the bipolar equivalents (LS, ALS, AS).
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
LOAD
1,5D
A
B
C
D
C5/2,3,4+
RCO
3CT=MAX
QA
QB
QC
QD
CLR
[1]
[2]
[3]
[4]
CTR
LSB
ENT
ENP
CLK
LOAD
1,5D
A
B
C
D
C5/2,3,4+
RCO
3CT=MAX
QA
QB
QC
QD
CLR
[1]
[2]
[3]
[4]
CTR
ENT
ENP
CLK
LOAD
1,5D
A
B
C
D
C5/2,3,4+
RCO
3CT=MAX
QA
QB
QC
QD
CLR
[1]
[2]
[3]
[4]
CTR
ENT
ENP
CLK
LOAD
1,5D
A
B
C
D
C5/2,3,4+
RCO
3CT=MAX
QA
QB
QC
QD
CLR
[1]
[2]
[3]
[4]
CTR
ENT
ENP
CLK
To More-Significant Stages
Clear (L)
Count (H)/
Disable (L)
Count (H)/
Disable (L)
Load (L)
Clock
CT=0
M1
G3
G4
CT=0
M1
G3
G4
CT=0
M1
G3
G4
CT=0
M1
G3
G4
Figure 2
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
The glitch on RCO is caused because the propagation delay of the rising edge of Q
A
of the second stage is
shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, Q
A
, Q
B
, Q
C
, and Q
D
(ENT
Q
A
Q
B
Q
C
Q
D
). The resulting glitch is about 7-12 ns in duration. Figure 3 shows the condition in
which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to
other stages. Q
B
, Q
C
, and Q
D
of the first and second stage are at logic one, and Q
A
of both stages are at logic
zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, Q
A
and RCO of the
first stage go high. On the rising edge of the third clock pulse, Q
A
and RCO of the first stage return to a low level,
and Q
A
of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears
because of the race condition inside the chip.
1
2
3
4
5
CLK
ENT1
QB1, QC1, QD1
QA1
RCO1, ENT2
QB2, QC2, QD2
QA2
RCO2
Glitch (7-12 ns)
Figure 3
The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock
edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the
inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (t
g
). In other words,
f
max
= 1/(t
pd
CLK-to-RCO + t
g
). For example, at 25
C at 4.5-V V
CC
, the clock-to-RCO propagation delay is
43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the
cascaded counters can use is 18 MHz. The following tables contain the f
clock
, t
w
, and f
max
specifications for
applications that use more than two 'HC161 devices cascaded together.
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D - JANUARY 1996 - REVISED SEPTEMBER 2003
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
SN54HC161
SN74HC161
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
3.6
2.5
2.9
fclock
Clock frequency
4.5 V
18
12
14
MHz
fclock
Clock frequency
6 V
21
14
17
MHz
2 V
140
200
170
tw
Pulse duration, CLK high or low
4.5 V
28
40
36
ns
tw
Pulse duration, CLK high or low
6 V
24
36
30
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Note 4)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC161
SN74HC161
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
3.6
2.5
2.9
fmax
4.5 V
18
12
14
MHz
fmax
6 V
21
14
17
MHz
NOTE 4: These limits apply only to applications that use more than two 'HC161 devices cascaded together.
If the 'HC161 devices are used as a single unit, or only two cascaded together, then the maximum clock
frequency that the device can use is not limited because of the glitch. In these situations, the device can be
operated at the maximum specifications.
A glitch can appear on RCO of a single 'HC161 device, depending on the relationship of ENT to CLK. Any
application that uses RCO to drive any input except an ENT of another cascaded 'HC161 device must take this
into consideration.
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
84075012A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
8407501EA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
8407501FA
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
JM38510/66302BEA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
JM38510/66302BFA
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
SN54HC161J
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SN74HC161D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161DBR
OBSOLETE
SSOP
DB
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161DE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161DRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161DT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161DTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74HC161N3
OBSOLETE
PDIP
N
16
TBD
Call TI
Call TI
SN74HC161NE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74HC161NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161PWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161PWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161PWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC161PWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54HC161FK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54HC161J
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SNJ54HC161W
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
Addendum-Page 1
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2005
Addendum-Page 2
MECHANICAL DATA
MLCC006B OCTOBER 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,90
7,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
20
16
6,50
6,50
14
0,05 MIN
5,90
5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0
8
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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amplifier.ti.com
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interface.ti.com
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www.ti.com/digitalcontrol
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logic.ti.com
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www.ti.com/military
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power.ti.com
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www.ti.com/wireless
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2005, Texas Instruments Incorporated
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