SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current 3-State Outputs Drive Bus
Lines Directly or Up To 15 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 21 ns
D
6-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
Bus-Structured Pinout
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q
V
1Q
8D
GND
LE
SN54HC573A . . . FK PACKAGE
(TOP VIEW)
CC
SN54HC573A . . . J OR W PACKAGE
SN74HC573A . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
description/ordering information
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the
outputs are latched to retain the data that was set up.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube of 25
SN74HC573AN
SN74HC573AN
SOIC - DW
Tube of 40
SN74HC573ADW
HC573A
-40
C to 85
C
SOIC - DW
Reel of 2500
SN74HC573ADWR
HC573A
-40
C to 85
C
SSOP - DB
Reel of 2000
SN74HC573ADBR
HC573A
TSSOP - PW
Reel of 2000
SN74HC573APWR
HC573A
TSSOP - PW
Reel of 250
SN74HC573APWT
HC573A
CDIP - J
Tube of 25
SNJ54HC573AJ
SNJ54HC573AJ
-55
C to 125
C
CFP - W
Tube of 150
SNJ54HC573AW
SNJ54HC573AW
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54HC573AFK
SNJ54HC573AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1D
1Q
1
11
2
19
To Seven Other Channels
C1
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HC573A
SN74HC573A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VIH
High-level input voltage
VCC = 6 V
4.2
4.2
V
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VIL
Low-level input voltage
VCC = 6 V
1.8
1.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
1000
1000
tt
Input transition (rise and fall) time
VCC = 4.5 V
500
500
ns
tt
Input transition (rise and fall) time
VCC = 6 V
400
400
ns
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC573A
SN74HC573A
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
1.998
1.9
1.9
IOH = -20
A
4.5 V
4.4
4.499
4.4
4.4
VOH
VI = VIH or VIL
IOH = -20
A
6 V
5.9
5.999
5.9
5.9
V
VOH
VI = VIH or VIL
IOH = -6 mA
4.5 V
3.98
4.3
3.7
3.84
V
IOH = -7.8 mA
6 V
5.48
5.8
5.2
5.34
2 V
0.002
0.1
0.1
0.1
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
VOL
VI = VIH or VIL
IOL = 20
A
6 V
0.001
0.1
0.1
0.1
V
VOL
VI = VIH or VIL
IOL = 6 mA
4.5 V
0.17
0.26
0.4
0.33
V
IOL = 7.8 mA
6 V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
IOZ
VO = VCC or 0
6 V
0.01
0.5
10
5
A
ICC
VI = VCC or 0,
IO = 0
6 V
8
160
80
A
Ci
2 V to 6 V
3
10
10
10
pF
SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
SN54HC573A
SN74HC573A
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
80
120
100
tw
Pulse duration, LE high
4.5 V
16
24
20
ns
tw
Pulse duration, LE high
6 V
14
20
17
ns
2 V
50
75
63
tsu
Setup time, data before LE
4.5 V
10
15
13
ns
tsu
Setup time, data before LE
6 V
9
13
11
ns
2 V
20
24
24
th
Hold time, data after LE
4.5 V
5
5
5
ns
th
Hold time, data after LE
6 V
5
5
5
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC573A
SN74HC573A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
77
175
265
220
D
Q
4.5 V
26
35
53
44
tpd
D
Q
6 V
23
30
45
38
ns
tpd
2 V
87
175
265
220
ns
LE
Any Q
4.5 V
27
35
53
44
LE
Any Q
6 V
23
30
45
38
2 V
68
150
225
190
ten
OE
Any Q
4.5 V
24
30
45
38
ns
ten
OE
Any Q
6 V
21
26
38
32
ns
2 V
47
150
225
190
tdis
OE
Any Q
4.5 V
23
30
45
38
ns
tdis
OE
Any Q
6 V
21
26
38
32
ns
2 V
28
60
90
75
tt
Any Q
4.5 V
8
12
18
15
ns
tt
Any Q
6 V
6
10
15
13
ns
SN54HC573A, SN74HC573A
OCTAL TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCLS147E - DECEMBER 1982 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HC573A
SN74HC573A
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
95
200
300
250
D
Q
4.5 V
33
40
60
50
tpd
D
Q
6 V
21
34
51
43
ns
tpd
2 V
103
225
335
285
ns
LE
Any Q
4.5 V
33
45
67
57
LE
Any Q
6 V
29
38
57
48
2 V
85
200
300
250
ten
OE
Any Q
4.5 V
29
40
60
50
ns
ten
OE
Any Q
6 V
26
34
51
43
ns
2 V
60
210
315
265
tt
Any Q
4.5 V
17
42
63
53
ns
tt
Any Q
6 V
14
36
53
45
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per latch
No load
50
pF
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