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SN54HCT374, SN74HCT374
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCLS005D - MARCH 1984 - REVISED AUGUST 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operating Voltage Range of 4.5 V to 5.5 V
D
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 22 ns
D
6-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
Inputs Are TTL-Voltage Compatible
D
Eight D-Type Flip-Flops in a Single Package
D
Full Parallel Access for Loading
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the 'HCT374 devices are
edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels that were set up at the
data (D) inputs.
An output-enable (OE) input places the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube of 20
SN74HCT374N
SN74HCT374N
SOIC - DW
Tube of 25
SN74HCT374DW
HCT374
SOIC - DW
Reel of 2000
SN74HCT374DWR
HCT374
-40
C to 85
C
SOP - NS
Reel of 2000
SN74HCT374NSR
HCT374
-40
C to 85
C
SSOP - DB
Reel of 2000
SN74HCT374DBR
HT374
Tube of 70
SN74HCT374PW
TSSOP - PW
Reel of 2000
SN74HCT374PWR
HT374
TSSOP - PW
Reel of 250
SN74HCT374PWT
HT374
CDIP - J
Tube of 20
SNJ54HCT374J
SNJ54HCT374J
-55
C to 125
C
CFP - W
Tube of 85
SNJ54HCT374W
SNJ54HCT374W
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54HCT374FK
SNJ54HCT374FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
OE
5Q
5D
V
8Q
4Q
GND
CLK
SN54HCT374 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HCT374 . . . J OR W PACKAGE
SN74HCT374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HCT374, SN74HCT374
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCLS005D - MARCH 1984 - REVISED AUGUST 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE
CLK
D
OUTPUT
Q
L
H
H
L
L
L
L
H or L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
3
2
CLK
1D
C1
1D
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HCT374, SN74HCT374
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCLS005D - MARCH 1984 - REVISED AUGUST 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HCT374
SN74HCT374
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
2
2
V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
t/
v
Input transition rise/fall time
500
500
ns
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HCT374
SN74HCT374
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
VI = VIH or VIL
IOH = -20
A
4.5 V
4.4
4.499
4.4
4.4
V
VOH
VI = VIH or VIL
IOH = -6 mA
4.5 V
3.98
4.3
3.7
3.84
V
VOL
VI = VIH or VIL
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
V
VOL
VI = VIH or VIL
IOL = 6 mA
4.5 V
0.17
0.26
0.4
0.33
V
II
VI = VCC or 0
5.5 V
0.1
100
1000
1000
nA
IOZ
VO = VCC or 0
5.5 V
0.01
0.5
10
5
A
ICC
VI = VCC or 0,
IO = 0
5.5 V
8
160
80
A
ICC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
5.5 V
1.4
2.4
3
2.9
mA
Ci
4.5 V
to 5.5 V
3
10
10
10
pF
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
SN54HCT374
SN74HCT374
UNIT
VCC
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
4.5 V
31
21
25
MHz
fclock
Clock frequency
5.5 V
36
23
28
MHz
tw
Pulse duration, CLK high or low
4.5 V
16
24
20
ns
tw
Pulse duration, CLK high or low
5.5 V
14
22
18
ns
tsu
Setup time, data before CLK
4.5 V
20
30
25
ns
tsu
Setup time, data before CLK
5.5 V
17
27
23
ns
th
Hold time, data after CLK
4.5 V
10
10
10
ns
th
Hold time, data after CLK
5.5 V
10
10
10
ns
SN54HCT374, SN74HCT374
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCLS005D - MARCH 1984 - REVISED AUGUST 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HCT374
SN74HCT374
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
4.5 V
31
36
21
25
MHz
fmax
5.5 V
36
40
23
28
MHz
tpd
CLK
Any Q
4.5 V
30
36
54
45
ns
tpd
CLK
Any Q
5.5 V
25
32
49
41
ns
ten
OE
Any Q
4.5 V
26
30
45
38
ns
ten
OE
Any Q
5.5 V
23
27
41
34
ns
tdis
OE
Any Q
4.5 V
23
30
45
38
ns
tdis
OE
Any Q
5.5 V
22
27
41
34
ns
tt
Any Q
4.5 V
10
12
18
15
ns
tt
Any Q
5.5 V
9
11
16
14
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HCT374
SN74HCT374
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tpd
CLK
Any Q
4.5 V
40
46
69
58
ns
tpd
CLK
Any Q
5.5 V
35
41
62
52
ns
ten
OE
Any Q
4.5 V
34
40
60
50
ns
ten
OE
Any Q
5.5 V
29
36
54
45
ns
tt
Any Q
4.5 V
18
42
63
53
ns
tt
Any Q
5.5 V
16
38
57
48
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per flip-flop
No load
85
pF
SN54HCT374, SN74HCT374
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCLS005D - MARCH 1984 - REVISED AUGUST 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.3 V
10%
90%
3 V
VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
1.3 V
tPZL
tPLZ
VOH
0 V
1.3 V
1.3 V
tPZH
tPHZ
Output
Waveform 2
(See Note B)
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
1.3 V
1.3 V
1.3 V
0.3 V
0.3 V
2.7 V
2.7 V
3 V
3 V
0 V
0 V
tr
tf
Reference
Input
Data
Input
1.3 V
High-Level
Pulse
1.3 V
3 V
0 V
1.3 V
1.3 V
3 V
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V
1.3 V
10%
10%
90%
90%
3 V
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
1.3 V
tPLH
tPHL
1.3 V
1.3 V
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-
Phase
Output
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
Test
Point
From Output
Under Test
RL
VCC
S1
S2
LOAD CIRCUIT
PARAMETER
CL
tPZH
tpd or tt
tdis
ten
tPZL
tPHZ
tPLZ
1 k
1 k
50 pF
or
150 pF
50 pF
Open
Closed
RL
S1
Closed
Open
S2
Open
Closed
Closed
Open
50 pF
or
150 pF
Open
Open
--
CL
(see Note A)
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms