1
Data sheet acquired from Harris Semiconductor
SCHS235
Features
Buffered Inputs
Typical Propagation Delay
- 5.4ns at V
CC
= 5V, T
A
= 25
o
C, C
L
= 50pF
Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
SCR-Latchup-Resistant CMOS Process and Circuit
Design
Speed of Bipolar FASTTM/AS/S with Significantly
Reduced Power Consumption
Balanced Propagation Delays
AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
24mA Output Drive Current
- Fanout to 15 FASTTM ICs
- Drives 50
Transmission Lines
Description
The CD74AC139 and CD74ACT139 are dual 2-to-4-line
decoders/demultiplexers that utilize the Harris Advanced
CMOS Logic technology. These devices contain two inde-
pendent binary to one-of-four decoders, each with a single
active LOW enable input (1E or 2E). Data on the select
inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four
normally HIGH outputs to go LOW.
If the enable input is HIGH, all four outputs remain HIGH. For
demultiplexer operation, the enable input is the data input.
The enable input also functions as a chip select when these
devices are cascaded.
Pinout
CD74AC139, CD74ACT139
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CD74AC139E
0 to 70
o
C, -40 to 85,
-55 to 125
16 Ld PDIP
E16.3
CD74ACT139E
0 to 70
o
C, -40 to 85,
-55 to 125
16 Ld PDIP
E16.3
CD74AC139M96
0 to 70
o
C, -40 to 85,
-55 to 125
16 Ld SOIC
M16.15
CD74ACT139M
0 to 70
o
C, -40 to 85,
-55 to 125
16 Ld SOIC
M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1E
1A0
1A1
1Y0
1Y1
1Y2
GND
1Y3
V
CC
2A0
2A1
2Y0
2Y1
2Y2
2Y3
2E
September 1998
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FASTTM is a Trademark of Fairchild Semiconductor.
Copyright
Harris Corporation 1998
CD74AC139,
CD74ACT139
Dual 2-to-4-Line Decoder/Demultiplexer
File Number
1953.1
[ /Title
(CD74
AC139
,
CD74
ACT13
9)
/Sub-
ject
(Dual
2-to-4-
Line
Decod
er/Dem
ulti-
plexer)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Advan
ced
CMOS
)
/Cre-
ator ()
/DOCI
NFO
2
Functional Diagram
TRUTH TABLE
INPUTS
OUTPUTS
ENABLE
SELECT
E
A1
A0
Y3
Y2
Y1
Y0
L
L
L
H
H
H
L
L
L
H
H
H
L
H
L
H
L
H
L
H
H
L
H
H
L
H
H
H
H
X
X
H
H
H
H
X = Don't Care
2
3
1A1
1A0
1E
GND = 8
V
CC
= 16
1Y2
6
7
1Y3
1Y1
5
1Y0
4
1
DECODER
14
13
2A1
2A0
2E
2Y2
10
9
2Y3
2Y1
11
2Y0
12
15
DECODER
1
2
CD74AC139, CD74ACT139
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
50mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
50mA
DC V
CC
or Ground Current, I
CC or
I
GND
(Note 3)
. . . . . . . . .
100mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
(Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
Thermal Resistance (Typical, Note 5)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add
25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5.
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
AC TYPES
High Level Input Voltage
V
IH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
3
2.1
-
2.1
-
2.1
-
V
5.5
3.85
-
3.85
-
3.85
-
V
Low Level Input Voltage
V
IL
-
-
1.5
-
0.3
-
0.3
-
0.3
V
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
High Level Output Voltage
V
OH
V
IH
or V
IL
-0.05
1.5
1.4
-
1.4
-
1.4
-
V
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
CD74AC139, CD74ACT139
4
Low Level Output Voltage
V
OL
V
IH
or V
IL
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
Input Leakage Current
I
I
V
CC
or
GND
-
5.5
-
0.1
-
1
-
1
A
Quiescent Supply Current
MSI
I
CC
V
CC
or
GND
0
5.5
-
8
-
80
-
160
A
ACT TYPES
High Level Input Voltage
V
IH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
V
IL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
V
OH
V
IH
or V
IL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
OL
V
IH
or V
IL
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
Input Leakage Current
I
I
V
CC
or
GND
-
5.5
-
0.1
-
1
-
1
A
Quiescent Supply Current
MSI
I
CC
V
CC
or
GND
0
5.5
-
8
-
80
-
160
A
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
I
CC
V
CC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50
transmission-line-drive capability at 85
o
C, 75
at 125
o
C.
ACT Input Load Table
INPUT
UNIT LOAD
A0, A1
1
E
0.67
NOTE: Unit load is
I
CC
limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25
o
C.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO
85
o
C
-55
o
C TO
125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
CD74AC139, CD74ACT139
5
Switching Specifications
Input t
r
, t
f
= 3ns, C
L
= 50pF (Worst Case)
PARAMETER
SYMBOL
V
CC
(V)
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
AC TYPES
Propagation Delay, A0, A1 to
Outputs
t
PLH
, t
PHL
1.5
-
-
119
-
-
131
ns
3.3
(Note 9)
3.9
-
13.4
3.7
-
14.7
ns
5
(Note 10)
2.8
-
9.5
2.6
-
10.5
ns
Propagation Delay,
E to Outputs
t
PLH
, t
PHL
1.5
-
-
119
-
-
131
ns
3.1
3.9
-
13.4
3.7
-
14.7
ns
5
2.8
-
9.5
2.6
-
10.5
ns
Input Capacitance
C
I
-
-
-
10
-
-
10
pF
Power Dissipation Capacitance
C
PD
(Note 11)
-
-
83
-
-
83
-
pF
ACT TYPES
Propagation Delay, A0, A1 to
Outputs
t
PLH
, t
PHL
5
(Note 10)
3.1
-
10.5
2.9
-
11.5
ns
Propagation Delay,
E to Outputs
t
PLH
, t
PHL
5
3.2
-
10.9
3
-
12
ns
Input Capacitance
C
I
-
-
-
10
-
-
10
pF
Power Dissipation Capacitance
C
PD
(Note 11)
-
-
83
-
-
83
-
pF
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. C
PD
is used to determine the dynamic power consumption per decoder/demultiplexer.
AC: P
D
= V
CC
2
f
i
(C
PD
+ C
L
)
ACT: P
D
= V
CC
2
f
i
(C
PD
+ C
L
) + V
CC
I
CC
where f
i
= input frequency, C
L
= output load capacitance, V
CC
= supply voltage.
FIGURE 1.
FIGURE 2.
t
r
= 3ns
90%
t
f
= 3ns
V
S
10%
t
PHL
V
S
INPUT E
t
PLH
INPUT Y3
INPUT
GND
LEVEL
INPUT
LEVEL
A1
GND
OUTPUT Y3
3ns
3ns
90%
10%
V
S
t
PHL
t
PLH
V
S
CD74AC139, CD74ACT139
6
DUT
OUTPUT
R
L
(NOTE)
OUTPUT
LOAD
500
C
L
50pF
NOTE: For AC Series Only: When V
CC
= 1.5V, R
L
= 1k
.
FIGURE 3. PROPAGATION DELAY TIMES
CD74AC
CD74ACT
Input Level
V
CC
3V
Input Switching Voltage, V
S
0.5 V
CC
1.5V
Output Switching Voltage, V
S
0.5 V
CC
0.5 V
CC
CD74AC139, CD74ACT139
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Copyright
1999, Texas Instruments Incorporated
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