CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A JULY 2000 REVISED JULY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
BiCMOS Technology With Low Quiescent
Power
D
Buffered Inputs
D
Noninverted Outputs
D
Input/Output Isolation From V
CC
D
Controlled Output Edge Rates
D
64-mA Output Sink Current
D
Output Voltage Swing Limited to 3.7 V
D
SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
D
Multiplexed Real-Time and Stored Data
D
Package Options Include Plastic
Small-Outline (M) Package and Standard
Plastic (EN) DIP
description
The CD74FCT652 is an octal bus transceiver and resistor with 3-state outputs. It consists of D-type flip-flops
and control circuitry, arranged for multiplexed transmission of data directly from the data bus or from the internal
storage registers. Output-enable (OEAB and OEBA) inputs control the transceiver functions. The select-control
(SAB and SBA) inputs select real-time-data or stored-data transfer. A low-input level selects real-time data, and
a high-input level selects stored data. The select-control circuitry eliminates the typical decoding glitch that
occurs in a multiplexer during the transition between stored data and real-time data.
The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS
transistors that limits the output high level to two diode drops below V
CC
. This resultant lowering of output swing
(0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V
CC
bounce and ground bounce and their effects during simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking 64 mA.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flop by low-to-high transitions at
the appropriate clock terminal (CLKAB and CLKBA), regardless of the state of the select or enable control
terminals. When SAB and SBA are in the real-time-transfer mode, it also is possible to store data without using
the internal D-type flip-flop by simultaneously enabling OEAB and OEBA. In this configuration, each output
reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each
set of bus lines remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).
The CD74FCT652 is characterized for operation from 0
C to 70
C.
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EN OR M PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLKAB
SAB
OEAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A JULY 2000 REVISED JULY 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR
OEAB
OEBA
CLKAB
CLKBA
SAB
SBA
A1A8
B1B8
FUNCTION
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
X
X
Input
Input
Store A and B data
X
H
H or L
X
X
Input
Unspecified
Store A, hold B
H
H
X
X
Input
Output
Store A in both registers
L
X
H or L
X
X
Unspecified
Input
Hold A, store B
L
L
X
X
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real-time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus and
stored B data to A bus
The data output functions can be enabled or disabled by various level combinations at OEAB or OEBA. Data input functions
always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
When select control is low, clocks can occur simultaneously if allowances are made for propagation delays from A to B (B to
A) plus setup and hold times. When select control is high, clocks must be staggered to load both registers.
CD74FCT652
BiCMOS OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCBS734A JULY 2000 REVISED JULY 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OEAB
X
L
L
OEAB
L
L
CLKAB
X
CLKBA
X
SAB
X
SBA
L
CLKAB
X
CLKBA
X
SAB
L
SBA
X
H
CLKAB CLKBA
X
SAB
X
SBA
X
CLKAB
CLKBA
SAB
SBA
X
H
X
X
X
X
X
H
L
H or L
H
H
OEBA
OEBA
H
H
OEAB OEBA
OEAB
OEBA
H or L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM A, B, OR A AND B
TRANSFER STORED DATA TO A AND/OR B
3
21
1
23
2
22
1
23
2
22
3
21
3
21
23
2
22
3
21
1
2
22
1
23
Figure 1. Bus-Management Functions
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