1
Data sheet acquired from Harris Semiconductor
SCHS122I
Features
Wide Analog Input Voltage Range . . . . . . . . . .
5V Max
Low "On" Resistance
- 70
Typical (V
CC
- V
EE
= 4.5V)
- 40
Typical (V
CC
- V
EE
= 9V)
Low Crosstalk between Switches
Fast Switching and Propagation Speeds
"Break-Before-Make" Switching
Wide Operating Temperature Range . . -55
o
C to 125
o
C
CD54HC/CD74HC Types
- Operation Control Voltage . . . . . . . . . . . . . . 2V to 6V
- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V
- High Noise Immunity . . . N
IL
= 30%, N
IH
= 30% of V
CC
,
V
CC
= 5V
CD54HCT/CD74HCT Types
- Operation Control Voltage . . . . . . . . . . . 4.5V to 5.5V
- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V
- Direct LSTTL Input
Logic Compatibility . . . V
IL
= 0.8V Max, V
IH
= 2V Min
- CMOS Input Compatibility . . . . . I
I
1
A at V
OL
, V
OH
Description
These devices are digitally controlled analog switches which
utilize silicon gate CMOS technology to achieve operating
speeds similar to LSTTL with the low power consumption of
standard CMOS integrated circuits.
These analog multiplexers/demultiplexers control analog
voltages that may vary across the voltage supply range (i.e.
V
CC
to V
EE
). They are bidirectional switches thus allowing
any analog input to be used as an output and vice-versa.
The switches have low "on" resistance and low "off" leak-
ages. In addition, all three devices have an enable control
which, when high, disables all switches to their "off" state.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC4051F3A
-55 to 125
16 Ld CERDIP
CD54HC4052F3A
-55 to 125
16 Ld CERDIP
CD54HC4053F3A
-55 to 125
16 Ld CERDIP
CD54HCT4051F3A
-55 to 125
16 Ld CERDIP
CD74HC4051E
-55 to 125
16 Ld PDIP
CD74HC4051M
-55 to 125
16 Ld SOIC
CD74HC4051MT
-55 to 125
16 Ld SOIC
CD74HC4051M96
-55 to 125
16 Ld SOIC
CD74HC4051NSR
-55 to 125
16 Ld SOP
CD74HC4051PWR
-55 to 125
16 Ld TSSOP
CD74HC4051PWT
-55 to 125
16 Ld TSSOP
CD74HC4052E
-55 to 125
16 Ld PDIP
CD74HC4052M
-55 to 125
16 Ld SOIC
CD74HC4052MT
-55 to 125
16 Ld SOIC
CD74HC4052M96
-55 to 125
16 Ld SOIC
CD74HC4052NSR
-55 to 125
16 Ld SOP
CD74HC4052PW
-55 to 125
16 Ld TSSOP
CD74HC4052PWR
-55 to 125
16 Ld TSSOP
CD74HC4052PWT
-55 to 125
16 Ld TSSOP
CD74HC4053E
-55 to 125
16 Ld PDIP
CD74HC4053M
-55 to 125
16 Ld SOIC
CD74HC4053MT
-55 to 125
16 Ld SOIC
CD74HC4053M96
-55 to 125
16 Ld SOIC
CD74HC4053NSR
-55 to 125
16 Ld SOP
CD74HC4053PW
-55 to 125
16 Ld TSSOP
CD74HC4053PWR
-55 to 125
16 Ld TSSOP
CD74HC4053PWT
-55 to 125
16 Ld TSSOP
CD74HCT4051E
-55 to 125
16 Ld PDIP
CD74HCT4051M
-55 to 125
16 Ld SOIC
CD74HCT4051MT
-55 to 125
16 Ld SOIC
CD74HCT4051M96
-55 to 125
16 Ld SOIC
CD74HCT4052E
-55 to 125
16 Ld PDIP
CD74HCT4052M
-55 to 125
16 Ld SOIC
CD74HCT4052MT
-55 to 125
16 Ld SOIC
CD74HCT4052M96
-55 to 125
16 Ld SOIC
CD74HCT4053E
-55 to 125
16 Ld PDIP
CD74HCT4053M
-55 to 125
16 Ld SOIC
CD74HCT4053MT
-55 to 125
16 Ld SOIC
CD74HCT4053M96
-55 to 125
16 Ld SOIC
CD74HCT4053PWR
-55 to 125
16 Ld TSSOP
CD74HCT4053PWT
-55 to 125
16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2004, Texas Instruments Incorporated
CD54/74HC4051, CD54/74HCT4051,
CD54/74HC4052, CD74HCT4052,
CD54/74HC4053, CD74HCT4053
High-Speed CMOS Logic
Analog Multiplexers/Demultiplexers
[ /Title
(CD54
HC405
1,
CD74
HC405
1,
CD74
HCT40
51,
CD74
HC405
2,
November 1997 - Revised July 2004
3
Functional Diagram of HC/HCT4051
TG
TG
TG
TG
TG
TG
TG
3
A
COMMON
OUT/IN
BINARY
TO
1 OF 8
DECODER
WITH
ENABLE
11
10
9
6
E
S
2
S
1
S
0
LOGIC
LEVEL
CONVERSION
8
7
GND
V
EE
16
V
CC
13
14
15
12
1
5
2
4
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CHANNEL IN/OUT
TG
TRUTH TABLE
HC/HCT4051
INPUT STATES
"ON"
CHANNELS
ENABLE
S
2
S
1
S
0
L
L
L
L
A0
L
L
L
H
A1
L
L
H
L
A2
L
L
H
H
A3
L
H
L
L
A4
L
H
L
H
A5
L
H
H
L
A6
L
H
H
H
A7
H
X
X
X
None
X = Don't care
'HC4051, 'HCT4051, 'HC4052, CD74HCT4052, 'HC4053, CD74HCT4053
'HC4051, 'HCT4051, 'HC4052, CD74HCT4052, 'HC4053, CD74HCT4053
4
Functional Diagram of 'HC4052, CD74HCT4052
TG
TG
TG
TG
TG
TG
TG
TG
13
COMMON A
OUT/IN
BINARY
TO
1 OF 4
DECODER
WITH
ENABLE
10
9
6
E
S
1
S
0
LOGIC
LEVEL
CONVERSION
16
V
CC
4
2
5
1
B
0
B
1
B
2
B
3
B CHANNELS IN/OUT
3
COMMON B
OUT/IN
8
7
GND
V
EE
12
14
15
11
A
3
A
2
A
1
A
0
A CHANNELS IN/OUT
TRUTH TABLE
'HC4052, CD74HCT4052
INPUT STATES
"ON"
CHANNELS
ENABLE
S
1
S
0
L
L
L
A0, B0
L
L
H
A1, B1
L
H
L
A2. B2
L
H
H
A3, B3
H
X
X
None
X = Don't care
'HC4051, 'HCT4051, 'HC4052, CD74HCT4052, 'HC4053, CD74HCT4053
'HC4051, 'HCT4051, 'HC4052, CD74HCT4052, 'HC4053, CD74HCT4053
5
Functional Diagram of 'HC4053, CD74HCT4053
TG
TG
TG
TG
TG
TG
14
11
10
9
6
E
S
2
S
1
S
0
7
GND
V
EE
16
V
CC
15
C COMMON
OUT/IN
4
B COMMON
OUT/IN
A COMMON
OUT/IN
LOGIC LEVEL
CONVERSION
BINARY TO
1 OF 2
DECODERS
WITH ENABLE
12
13
2
1
5
3
C
1
C
0
B
1
B
0
A
1
A
0
IN/OUT
8
TRUTH TABLE
'HC4053, CD74HCT4053
INPUT STATES
"ON"
CHANNELS
ENABLE
S
0
S
1
S
2
L
L
L
L
C0, B0, A0
L
H
L
L
C0, B0, A1
L
L
H
L
C0, B1, A0
L
H
H
L
C0, B1, A1
L
L
L
H
C1, B0, A0
L
H
L
H
C1, B0, A1
L
L
H
H
C1, B1, A0
L
H
H
H
C1, B1, A1
H
X
X
X
None
X = Don't care
'HC4051, 'HCT4051, 'HC4052, CD74HCT4052, 'HC4053, CD74HCT4053
'HC4051, 'HCT4051, 'HC4052, CD74HCT4052, 'HC4053, CD74HCT4053
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