1
Semiconductor
Features
Edge-Triggered Data Flip-Flops
- Transparent Select Latches
Buffered Inputs
3-State Complementary Outputs
Bus Line Driving Capability
Typical Propagation Delay: V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
- Clock to Output = 22ns
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
4.5V to 5.5V Operation
Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Description
The CD74HCT356 consists of data selectors/multiplexers that
select one of eight sources. The data select bits (S0, S1, and
S2) are stored in transparent latches that are enabled by a low
latch enable input (LE).
The data is stored in edge-triggered flip-flops that are
triggered by a low-to-high clock transition.
In both types the 3-state outputs are controlled by three
output-enable inputs (OE1, OE2, and OE3).
Pinout
CD74HCT356
(PDIP or SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD74HCT356E
-55 to 125
20 Ld PDIP
CD74HCT356M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
D7
D6
D5
D4
D3
D2
D0
D1
CP
GND
V
CC
Y
OE3
OE2
Y
OE1
S0
S1
S2
LE
SCLS459A - June 2001 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD74HCT356
High-Speed CMOS Logic
8-Input Multiplexer/Register, Three-State
3
H
H
H
L
L
H
D7
D7
H
H
H
H or L
L
L
H
D7
n
D7
n
H = High Voltage Level (Steady State); L = Low Voltage Level (Steady State);
= Transition from Low to High Level;
X = Don't Care; Z = High-Impedance State (Off State); D0
n
...D7
n
= the level of steady-state inputs D0 through D7, respectively,
before the most recent low-to-high transition of data control.
NOTE:
1. This column shows the input address setup with LE low.
TRUTH TABLE (Continued)
INPUTS
OUTPUTS
SELECT (NOTE 1)
CLOCK
OUTPUT ENABLES
S2
S1
S0
CP
OE1
OE2
OE3
Y
Y
Block Diagram
15
D
A
T
A
R
E
G
I
S
T
E
R
S
1
8
O
F
S
E
L
E
C
T
O
R
ADDRESS
DECODE
A
R
D
D
R
E
S
S
E
G
I
S
T
E
R
16
17
9
8
7
6
5
4
3
2
1
11
14
13
12
OE1
OE2
OE3
CP
D0
D1
D2
D3
D4
D5
D6
D7
LE
S0
S1
S2
19
18
Y
Y
BUFFERS
ENABLE LOGIC
CD74HCT356
5
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . . . . . .
35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
. . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
58
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or
V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or
V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
to
GND
0
5.5
-
-
0.1
-
1
-
1
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 3)
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
3-State Leakage
Current
I
OZ
V
IL
or
V
IH
V
O
=
V
CC
or
GND
5.5
-
-
0.5
-
5
-
10
A
NOTE:
3. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
CD74HCT356
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