CDCR81
DIRECT RAMBUS
TM
CLOCK GENERATOR
SCAS606B NOVEMBER 1998 REVISED NOVEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
300-MHz Differential Clock Source for
Direct RAMBUS Memory Systems for an
600-MHz Data Transfer Rate
D
Synchronizes the Clock Domains of the
Rambus Channel With an External System
or Processor Clock
D
Three Power Operating Modes to Minimize
Power for Mobile and Other
Power-Sensitive Applications
D
Operates From a Single 3.3-V Supply and
120-mW at 300 MHz (Typ)
D
Packaged in a Shrink Small-Outline
Package (DBQ)
D
Wide Phase-Lock Input Frequency Range
33 MHz to 100 MHz
D
No External Components Required for PLL
D
Supports Independent Channel Clocking
D
Spread Spectrum Clocking Tracking
Capability to Reduce EMI
D
Designed For Use With TI's 133-MHz Clock
Synthesizers CDC925, CDC924, CDC922
and CDC921
description
The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system
or processor clock. It is designed to support Direct Rambus memory on desktop, workstation, server and mobile
PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory
applications.
The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to
enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct
Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the
DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK
to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK
frequencies by ratios M and N such that PCLK/M = SYNCLK/N, where SYNCLK = BUSCLK/4. The DRCG
detects the phase difference between PCLK/M and SYNCLK/N and adjusts the phase of BUSCLK such that
the skew between PCLK/M and SYNCLK/N is minimized. This allows data to be transferred across the
SYNCLK/PCLK boundary without incurring additional latency.
User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of
one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz
with clock references ranging from 33 MHz to 100 MHz. The CDCR81 meets Rambus Clock Generator,
Revision 1.0 specification up to 300 MHz. The mode select terminals can be used to select a bypass mode
where the frequency multiplied reference clock is directly output to the Rambus channel for systems where
synchronization between the Rambus clock and a system clock is not required. Test modes are provided to
bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state
for board testing.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Direct Rambus and Rambus are trademarks of Rambus Inc.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
DD
IR
REFCLK
V
DD
P
GNDP
GNDI
PCLKM
SYNCLKN
GNDC
V
DD
C
V
DD
IPD
STOPB
PWRDNB
S0
S1
V
DD
O
GNDO
CLK
NC
CLKB
GNDO
V
DD
O
MULT0
MULT1
S2
DBQ PACKAGE
(TOP VIEW)
NC No internal connection
CDCR81
DIRECT RAMBUS
TM
CLOCK GENERATOR
SCAS606B NOVEMBER 1998 REVISED NOVEMBER 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The CDCR81 is characterized for operation over free-air temperatures of 0
C to 85
C.
functional block diagram
Bypass MUX
Test MUX
B
A
PLL
Phase
Aligner
PACLK
PLLCLK
ByPCLK
CLK
CLKB
REFCLK
D
SYNCLKN
PCLKM
MULT0
MULT1
2
PWRDWNB
S0
S1
S2
STOPB
FUNCTION TABLE
MODE
S0
S1
S2
CLK
CLKB
Normal
0
0
0
Phase aligned clock
Phase aligned clock B
Bypass
1
0
0
PLLCLK
PLLCLKB
Test
1
1
0
REFCLK
REFCLKB
Output test (OE)
0
1
X
Hi-Z
Hi-Z
Reserved
0
0
1
--
--
Reserved
1
0
1
--
--
Reserved
1
1
1
Hi-Z
Hi-Z
X = don't care, Hi-Z = high impedance
CDCR81
DIRECT RAMBUS
TM
CLOCK GENERATOR
SCAS606B NOVEMBER 1998 REVISED NOVEMBER 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
CLK
20
O
Output clock
CLKB
18
O
Output clock (complement)
GNDC
8
GND for phase aligner
GNDI
5
GND for control inputs
GNDO
17, 21
GND for clock outputs
GNDP
4
GND for PLL
MULT0
15
I
PLL multiplier select
MULT1
14
I
PLL multiplier select
NC
19
Not used
PCLKM
6
I
Phase detector input
PWRDNB
12
I
Active low power down
REFCLK
2
I
Reference clock
S0
24
I
Mode control
S1
23
I
Mode control
S2
13
I
Mode control
STOPB
11
I
Active low output disable
SYNCLKN
7
I
Phase detector input
VDDC
9
VDD for phase aligner
VDDIPD
10
Reference voltage for phase detector inputs and STOPB
VDDIR
1
Reference voltage for REFCLK
VDDO
16, 22
VDD for clock outputs
VDDP
3
VDD for PLL
CDCR81
DIRECT RAMBUS
TM
CLOCK GENERATOR
SCAS606B NOVEMBER 1998 REVISED NOVEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PLL divider selection
Table 1 lists the supported REFCLK and BUSCLK frequencies. Other REFCLK frequencies are permitted,
provided that (267 MHz < BUSCLK < 400 MHz) and (33 MHz < REFCLK < 100 MHz).
Table 1. REFCLK and BUSCLK Frequencies
MULT0
MULT1
REFCLK
(MHz)
MULTIPLY
RATIO
BUSCLK
(MHz)
0
0
67
4
267
0
1
50
6
300
0
1
67
6
400
1
1
33
8
267
1
1
50
8
400
1
0
100
8/3
267
clock output driver states
Table 2. Clock Output Driver States
STATE
PWRDNB
STOPB
CLK
CLKB
Powerdown
0
X
GND
GND
CLK stop
1
0
VX, STOP
VX, STOP
Normal
1
1
PACLK/PLLCLK/
REFCLK
PACLKB/PLLCLKB/
REFCLKB
Depending on the state of S0, S1, and S2.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
DD
(see Note 1)
0.5 V to 4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
, at any output terminal
0.5 V to V
DD
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range,V
I
, at any input terminal
0.5 V to V
DD
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD rating
TBD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation
see Dissipation Rating Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0
C to 85
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
PACKAGE
TA
25
C
POWER RATING
DERATING FACTOR
ABOVE TA = 25
C
TA = 70
C
POWER RATING
TA = 85
C
POWER RATING
DBQ
1400 mW
11 mW/
C
905 mW
740 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
CDCR81
DIRECT RAMBUS
TM
CLOCK GENERATOR
SCAS606B NOVEMBER 1998 REVISED NOVEMBER 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VDD
3.135
3.3
3.465
V
High-level input voltage, VIH (CMOS)
0.7
VDD
V
Low-level input voltage, VIL (CMOS)
0.3
VDD
V
Initial phase error at phase detector inputs
(required range for phase aligner)
0.5
tc(PD)
0.5
tc(PD)
REFCLK low-level input voltage, VIL
0.3
VDDIR
V
REFCLK high-level input voltage, VIH
0.7
VDDIR
V
Input signal low voltage, VIL (STOPB)
0.3
VDDIPD
V
Input signal high voltage, VIH (STOPB)
0.7
VDDIPD
V
Input reference voltage for (REFCLK) (VDDIR)
1.235
3.465
V
Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD)
1.235
3.465
V
High-level output current, IOH
16
mA
Low-level output current, IOL
16
mA
Operating free-air temperature, TA
0
85
C
timing requirements
MIN
MAX
UNIT
Input cycle time, tc(in)
10
40
ns
Input cycle-to-cycle jitter
250
ps
Input duty cycle over 10,000 cycles
40%
60%
Input frequency modulation, fmod
30
33
kHz
Modulation index, non-linear maximum 0.5%
0.6%
Phase detector input cycle time (PCLKM and SYNCLKN)
30
100
ns
Input slew rate, SR
1
4
V/ns
Input duty cycle (PCLKM and SYNCLKN)
25%
75%
PDF 
ZIP