8-Bit Latched Registered Transceiver
CY54/74FCT543T
SCCS030 - May 1994 - Revised March 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright
2000, Texas Instruments Incorporated
Features
Function, pinout, and drive compatible with FCT and
F logic
FCT-C speed at 5.3 ns max. (Com'l)
FCT-A speed at 6.5 ns max. (Com'l)
Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
Edge-rate control circuitry for significantly improved
noise characteristics
Power-off disable feature
Matched rise and fall times
Fully compatible with TTL input and output logic levels
ESD > 2000V
Sink current
64 mA (Com'l), 48 mA (Mil)
Source current
32 mA (Com'l), 12 mA (Mil)
Separation controls for data flow in each direction
Back to back latches for storage
Extended commercial range of
-
40C to +85C
Functional Description
The FCT543T octal latched transceiver contains two sets of
eight D-type latches with separate latch enable (LEAB, LEBA)
and output enable (OEAB, OEBA) controls for each set to
permit independent control of inputting and outputting in either
direction of data flow. For data flow from A to B, for example,
the A-to-B enable (CEAB) input must be LOW in order to enter
data from A or to take data from B, as indicated in the truth
table. With CEAB LOW, a LOW signal on the A-to-B latch
enable (LEAB) input makes the A-to-B latches transparent; a
subsequent LOW-to-HIGH transition of the LEAB signal puts
the A latches in the storage mode and their output no longer
change with the A inputs. With CEAB and OEAB both LOW,
the three-stage B output buffers are active and reflect the data
present at the output of the A latches. Control of data from B
to A is similar, but uses CEAB, LEAB, and OEAB inputs.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
Pin Configurations
LE
D Q
LE
D
Q
Detail A
Detail A x 7
A
0
A
2
A
1
A
3
A
4
A
6
A
5
A
7
B
0
B
2
B
1
B
3
B
4
B
6
B
5
B
7
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
Functional Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
0
LEBA
LEAB
CEBA
CEAB
OEBA
OEAB
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
V
CC
15
SOIC/QSOP
Top View
LEBA
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB
B
1
B
2
B
3
B
4
B
5
B
6
B
7
OEAB
CEBA
OEBA
A
0
GND
B
0
LEAB
CY54/74FCT543T
2
Maximum Ratings
[4, 5]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 65
C to +135
C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Input Voltage ........................................... 0.5V to +7.0V
DC Output Voltage......................................... 0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ...... 120 mA
Power Dissipation .......................................................... 0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Notes:
1.
H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care.
2.
A-to-B data flow shown: B-to-A flow control is the same, except using CEBA, LEBA, and OEBA.
3.
Before LEAB LOW-to-HIGH Transition.
4.
Unless otherwise noted, these limits are over the operating free-air temperature range.
5.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
6.
T
A
is the "instant on" case temperature.
Pin Description
Name
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
CEAB
A-to-B Enable Input (Active LOW)
CEBA
B-to-A Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input (Active LOW)
LEBA
B-to-A Latch Enable Input (Active LOW)
A
A-to-B Data Inputs or B-to-A Three-State Outputs
B
B-to-A Data Inputs or A-to-B Three-State Outputs
Function Table
[1, 2]
Inputs
Latch
Outputs
CEAB
LEAB
OEAB
A-to-B
[3]
B
H
X
X
Storing
High Z
X
H
X
Storing
X
X
X
H
X
High Z
L
L
L
Transpar-
ent
Current A Inputs
L
H
L
Storing
Previous A Inputs
Operating Range
Range
Range
Ambient
Temperature
V
CC
Commercial
DT
0
C to +70
C
5V
5%
Commercial
T, AT, CT
40
C to +85
C
5V
5%
Military
[6]
All
55
C to +125
C
5V
10%
CY54/74FCT543T
3
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
[7]
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
=Min., I
OH
=32 mA
Com'l
2.0
V
V
CC
=Min., I
OH
=15 mA
Com'l
2.4
3.3
V
V
CC
=Min., I
OH
=12 mA
Mil
2.4
3.3
V
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
=64 mA
Com'l
0.3
0.55
V
V
CC
=Min., I
OL
=48mA
Mil
0.3
0.55
V
V
IH
Input HIGH Voltage
2.0
V
V
IL
Input LOW Voltage
0.8
V
V
H
Hysteresis
[8]
All inputs
0.2
V
V
IK
Input Clamp Diode Voltage
V
CC
=Min., I
IN
=18 mA
0.7
1.2
V
I
IH
Input HIGH Current
V
CC
=Max., V
IN
=V
CC
5
A
I
IH
Input HIGH Current
[8]
V
CC
=Max., V
IN
=2.7V
1
A
I
IL
Input LOW Current
[8]
V
CC
=Max., V
IN
=0.5V
1
A
I
OZH
Off State HIGH-Level Output
Current
V
CC
=Max., V
OUT
= 2.7V
10
A
I
OZL
Off State LOW-Level
Output Current
V
CC
= Max., V
OUT
= 0.5V
10
A
I
OS
Output Short Circuit Current
[9]
V
CC
=Max., V
OUT
=0.0V
60
120
225
mA
I
OFF
Power-Off Disable
V
CC
=0V, V
OUT
=4.5V
1
A
Capacitance
[8]
Parameter
Description
Typ.
[7]
Max.
Unit
C
IN
Input Capacitance
5
10
pF
C
OUT
Output Capacitance
9
12
pF
Notes:
7.
Typical values are at V
CC
=5.0V, T
A
=+25C ambient.
8.
This parameter is specified but not tested.
9.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
CY54/74FCT543T
4
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.
[7]
Max.
Unit
I
CC
Quiescent Power Supply Current
V
CC
=Max., V
IN
0.2V, V
IN
V
CC
0.2V
0.1
0.2
mA
I
CC
Quiescent Power Supply Current
(TTL inputs)
V
CC
=Max., V
IN
=3.4V,
[10]
f
1
=0, Outputs Open
0.5
2.0
mA
I
CCD
Dynamic Power Supply Current
[11]
V
CC
=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
CEAB and OEAB=LOW, CEBA=HIGH,
V
IN
0.2V or V
IN
V
CC
0.2V
0.06
0.12
mA/MHz
I
C
Total Power Supply Current
[12]
V
CC
=Max., f
0
=10 MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=5 MHz,
CEAB and OEAB=LOW,CEBA=HIGH,
f
0
=LEAB = 10 MHz,
V
IN
0.2V or V
IN
V
CC
0.2V
0.7
1.4
mA
V
CC
=Max., f
0
=10 MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=5 MHz,
CEAB and OEAB=LOW, CEBA=HIGH,
f
0
=LEAB = 10 MHz, V
IN
=3.4V or V
IN
=GND
1.2
3.4
mA
V
CC
=Max., f
0
=10 MHz,
50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
1
=5 MHz,
CEAB and OEAB=LOW, CEBA=HIGH,
f
0
=LEAB = 10 MHz,
V
IN
0.2V or V
IN
V
CC
0.2V
2.8
5.6
[13]
mA
V
CC
=Max., f
0
=10 MHz,
50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
1
=5 MHz,
CEAB and OEAB=LOW, CEBA=HIGH,
f
0
=LEAB = 10 MHz, V
IN
=3.4V or V
IN
=GND
5.1
14.6
[13]
mA
Notes:
10. Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
12. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
= Quiescent Current with CMOS input levels
I
CC
= Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the I
CC
formula. These limits are specified but not tested.
CY54/74FCT543T
5
Switching Characteristics
Over the Operating Range
[14]
Parameter
Description
FCT543T
FCT543AT
Unit
Fig. No.
[15]
Military
Commercial
Commercial
Min.
[14]
Max.
Min.
[14]
Max.
Min.
[14]
Max.
t
PLH
t
PHL
Propagation Delay
Transparent Mode A to B or B to A
2.0
10.0
2.5
8.5
2.5
6.5
ns
1, 3
t
PLH
t
PHL
Propagation Delay
LEBA to A, LEAB to B
2.5
14.0
2.5
12.5
2.5
8.0
ns
1, 5
t
PZH
t
PZL
Output Enable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
2.0
14.0
2.0
12.0
2.0
9.0
ns
1, 7, 8
t
PZH
t
PZL
Output Disable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
2.0
13.0
2.0
9.0
2.0
7.5
ns
1, 7, 8
t
S
Set-Up Time HIGH or LOW,
A or B to LEBA or LEAB
3.0
2.0
2.0
ns
9
t
H
Hold Time HIGH or LOW,
A or B to LEBA or LEAB
2.0
2.0
2.0
ns
9
t
W
Pulse Width LOW
[8]
LEBA or LEAB
5.0
5.0
5.0
ns
5
Parameter
Description
FCT543CT
Unit
Fig. No.
[15]
Commercial
Min.
[14]
Max.
t
PLH
t
PHL
Propagation Delay
Transparent Mode A to B or B to A
2.5
5.3
ns
1, 3
t
PLH
t
PHL
Propagation Delay
LEBA to A, LEAB to B
2.5
7.0
ns
1, 5
t
PZH
t
PZL
Output Enable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
2.0
8.0
ns
1, 7, 8
t
PZH
t
PZL
Output Disable Time
OEBA or OEAB to A or B
CEBA or CEAB to A or B
2.0
6.5
ns
1, 7, 8
t
S
Set-Up Time, HIGH or LOW,
A or B to LEBA or LEAB
2.0
ns
9
t
H
Hold Time, HIGH or LOW,
A or B to LEBA or LEAB
2.0
ns
9
t
W
Pulse Width LOW LEBA or LEAB
[8]
5.0
ns
5
Notes:
14. Minimum limits are specified but not tested on Propagation Delays.
15. See "Parameter Measurement Information" in the General Information Section.
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