DAC5674

SLWS148 - SEPTEMBER 2003

14 BIT, 400 MSPS, 2x/4x INTERPOLATING CommsDAC

DIGITAL TO ANALOG CONVERTER

FEATURES

200-MSPS Maximum Input Data Rate

400-MSPS Maximum Update Rate DAC

76-dBc SFDR Over Full First Nyquist Zone
With Single Tone Input Signal (F

out

= 21 MHz)

74-dBc ACPR W-CDMA at 15.36 MHz IF

69-dBc ACPR W-CDMA at 30.72 MHz IF

Selectable 2x or 4x Interpolation Filter

- Linear Phase
- 0.05-dB Passband Ripple
- 80-dB Stopband Attenuation
- Stopband Transition 0.4-0.6 F

data

- nterpolation Filters Configurable in Either

Low-Pass or High-Pass Mode, Allows For
Selection Higher Order Image

On-chip 2x/4x PLL Clock Multiplier, PLL
Bypass Mode

Differential Scalable Current Outputs: 2 mA to
20 mA

On-Chip 1.2-V Reference

1.8-V Digital and 3.3-V Analog Supply
Operation

1.8/3.3-V CMOS Compatible Interface

Power Dissipation: 435 mW at 400 MSPS

Package: 48-Pin TQFP

APPLICATIONS

Cellular Base Transceiver Station Transmit
Channel

- CDMA: W-CDMA, CDMA2000, IS-95
- TDMA: GSM, IS-136, EDGE/UWC-136

Test and Measurement: Arbitrary Waveform
Generation

Direct Digital Synthesis (DDS)

Cable Modem Termination System

DESCRIPTION

The DAC5674 is a 14-bit resolution high-speed digital-to-analog converter (DAC) with integrated
4x-interpolation filter, on-board clock multiplier, and on-chip voltage reference. The device has been designed
for high-speed digital data transmission in wired and wireless communication systems, high-frequency
direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.

The 4x-interpolation filter is implemented as a cascade of two 2x-interpolation filters, each of which can be
configured for either low-pass or high-pass response. This enables the user to select one of the higher order
images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting
high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter
architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and
costs.

In 4x-interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at
intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission
in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter
requirements by filtering out the images in the adjacent Nyquist zones.

The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential
clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is
supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock
divider of the PLL ensures that the digital filters operate at the correct clock frequencies.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

2003, Texas Instruments Incorporated

DAC5674

SLWS148 - SEPTEMBER 2003

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.

The DAC5674 operates from an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. The digital
I/O's are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 500 mW at maximum operating conditions.
The DAC5674 provides a nominal full-scale differential current-output of 20 mA, supporting both single-ended
and differential applications. The output current can be directly fed to the load with no additional external output
buffer required. The device has been specifically designed for a differential transformer coupled output with a
50-

doubly terminated load. For a 20-mA full-scale output current both a 4:1 impedance ratio (resulting in an

output power of 4 dBm) and 1:1 impedance ratio transformer (-2-dBm output power) are supported. The latter
configuration is preferred for optimum performance at high output frequencies and update rates.

An accurate on-chip 1.2-V temperature compensated bandgap reference and control amplifier allows the user
to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control
capabilities. Alternatively, an external reference voltage may be applied for maximum flexibility. The device
features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby optimizing the
power consumption for the system's need.

The DAC5674 is available in a 48-pin HTQFP Powerpad plastic quad flatpack package. The device is
characterized for operation over the industrial temperature range of -40

C to 85

AVAILABLE OPTIONS

PACKAGED DEVICES

48-HTQFP PowerPAD

Plastic Quad Flatpack

-40

C to 85

DAC5674IPHP

-40 C to 85 C

DAC5674IPHPR

NOTE: PowerPAD is a trademark of Texas Instruments.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

UNIT

Supply voltage range

AVDD(2), CLKVDD(2), IOVDD(2), PLLVDD(2)

-0.5 V to 4 V

Supply voltage range

DVDD(3)

-0.5 V to 2.3 V

Voltage between AGND, DGND, CLKGND, PLLGND, and IOGND

-0.5 V to 0.5 V

D[13..0](3), HP1, HP2, DIV0(3), DIV1(3), PLLLOCK(3), RESET(3), X4(3)

-0.5 V to IOVDD + 0.5 V

Supply voltage range

IOUT1, IOUT2(2)

-1 V to AVDD + 0.5 V

Supply voltage range

EXTIO(2), EXTLO(2), BIASJ(2), SLEEP(2), CLK(2), CLKC(2), LPF(2)

-0.5 V to AVDD + 0.5 V

Peak input current (any input)

20 mA

Peak total input current (all inputs)

-30 mA

Operating free-air temperature range, TA: DAC5674I

-40

C to 85

Storage temperature range

-65

C to 150

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds

260

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Measured with respect to AGND.
(3) Measured with respect to DGND.

DAC5674

SLWS148 - SEPTEMBER 2003

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DC ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, Rset = 1.91 k

, internal reference, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

Bits

DC ACCURACY(1)

INL

Integral nonlinearity

1 LSB = IOUTFS/214, TMIN to TMAX

-3.5

3.5

LSB

INL

Integral nonlinearity

1 LSB = IOUTFS/214, TMIN to TMAX

-2.14e-4

2.14e-4

IOUTFS

DNL

Differential nonlinearity

-2

LSB

DNL

Differential nonlinearity

-1.22e-4

1.22e-4

IOUTFS

Monotonicity

Montonic to 12 bits

ANALOG OUTPUT

Offset error

0.02

FSR

Gain error

Without internal reference

2.3

%FSR

Gain error

With internal reference

1.3

%FSR

Minimum full-scale output
current(2)

Maximum full-scale output
current(2)

Output compliance range(3)

IOUTFS = 20 mA

-1

1.25

Output resistance

300

Output capacitance

REFERENCE OUTPUT

Reference voltage

1.14

1.2

1.26

Reference output current(4)

100

REFERENCE INPUT

VEXTIO

Input voltage range

0.1

1.25

Input resistance

Small signal bandwidth

1.4

MHz

Input capacitance

100

TEMPERATURE COEFFICIENTS

Offset drift

ppm of

FSR/

Gain drift

Without internal reference

ppm of

FSR/

Gain drift

With internal reference

100

ppm of

FSR/

Reference voltage drift

ppm/

POWER SUPPLY

AVDD

Analog supply voltage

3.3

3.6

DVDD

Digital supply voltage

1.65

1.8

1.95

CLKVDD

Clock supply voltage

3.3

3.6

IOVDD

I/O supply voltage

1.65

3.6

PLLVDD

PLL supply voltage

3.3

3.6

IAVDD

Analog supply current

Including output current through the load
resistor, AVDD = 3.3 V, DVDD = 1.8 V, 4x
interpolation,PLL on, 9-MHz IF, 400 MSPS

Specifications subject to change without notice.
(1) Measured differentially across IOUT1 and IOUT2 into 50

(2) Nominal full-scale current, IOUTFS, equals 32X the IBIAS current.
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting

in reduced reliability of the DAC5674 device. The upper limit of the output compliance is determined by the load resistors and full-scale output
current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.

(4) Use an external buffer amplifier with high impedance input to drive any external load.

DAC5674

SLWS148 - SEPTEMBER 2003

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DC ELECTRICAL CHARACTERISTICS (CONTINUED)

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, Rset = 1.91 k

, internal reference, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY (CONTINUED)

IDVDD

Digital supply current

AVDD = 3.3 V, DVDD = 1.8 V, 4x interpolation,PLL
on, 9-MHz IF, 400 MSPS

107

140

ISLEEP3.3 Sleep mode

Sleep mode, supply current 3.3 V

ISLEEP1.8 Sleep mode

Sleep mode, supply current 1.8 V

0.5

IPLLVDD

PLL supply current(1)

Fdata = 100 MSPS, Fupdate = 400 MSPS,
DIV[1:0] = '00', AVDD = 3.3 V, DVDD = 1.8 V, 4x
interpolation,PLL on, 9-MHz IF, 400 MSPS

IIOVDD

Buffer supply current

AVDD = 3.3 V, DVDD = 1.8 V, 4x interpolation,PLL
on, 9-MHz IF, 400 MSPS

ICLKVDD

Clock supply current(1)

AVDD = 3.3 V, DVDD = 1.8 V, 4x interpolation,PLL
on, 9-MHz IF, 400 MSPS

Power dissipation

AVDD = 3.3 V, DVDD = 1.8 V, 4x interpolation,
PLL on, 9-MHz IF, 400 MSPS

435

550

APSRR

Power supply rejection ratio

-0.2

0.2

%FSR/V

DPSRR

-0.2

0.2

%FSR/V

Operating range

-40

Specifications subject to change without notice.
(1) PLL enabled

AC ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V,
IOUTFS = 20 mA, differential transformer coupled output, 50-

doubly terminated load (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG OUTPUT

fCLK

Maximum output update rate

400

MSPS

ts(DAC)

Output settling time to 0.1%

Mid-scale transition

tr(IOUT)

Output rise time 10% to 90%(1)

1.4

tf(IOUT)

Output fall time 90% to 10%(1)

1.5

Output noise

IOUTFS = 20 mA

pA/

Output noise

IOUTFS = 2 mA

pA/

AC LINEARITY 1:1 IMPEDANCE RATIO TRANSFORMER

Spurious free dynamic range (First

fDATA = 52 MSPS, fOUT = 14 MHz, TA = 25

SFDR

Spurious free dynamic range (First
Nyquist zone < fDATA/2) X4 LL-mode

fDATA = 100 MSPS, fOUT = 21 MHz, TMIN to TMAX

dBc

SFDR

Nyquist zone < fDATA/2) X4 LL-mode

fDATA = 100 MSPS, fOUT = 41 MHz, TMIN to TMAX

dBc

SNR

Signal-to-noise ratio (First Nyquist

fDATA = 78 MSPS, fOUT = 20 MHz, TMIN to TMAX

SNR

Signal-to-noise ratio (First Nyquist
zone < fDATA/2) X4 LL-mode

fDATA = 100 MSPS, fOUT = 20 MHz, TMIN to TMAX

ACPR

Adjacent channel power ratio
W-CDMA signal with 3.84 MHz BW

fDATA = 61.44 MSPS, IF = 15.360 MHz, X4 LL-mode

ACPR

W-CDMA signal with 3.84 MHz BW
5-MHz channel spacing

fDATA = 122.88 MSPS, IF = 30.72 MHz, X2 L-mode

IMD3

Third-order two-tone intermodulation

fDATA = 61.44 MSPS, fOUT = 45.4 and 46.4 MHz,
X4 HL-mode

dBc

IMD3

Third-order two-tone intermodulation
(each tone at -6 dBFS)

fDATA = 61.44 MSPS, fOUT = 15.1 and 16.1 MHz,
X4 LL-mode

dBc

IMD

Four-tone Intermodulation to Nyquist

fDATA = 78 MSPS fOUT = 15.6 MHz, 15.8 MHz,
16.2 MHz, 16.4 MHz, X4 LL-mode

dBc

IMD

Four-tone Intermodulation to Nyquist
(each tone at 12 dBFS)

fDATA = 52 MSPS fOUT = 68.8 MHz, 69.6 MHz,
71.2 MHz, 72 MHz, X4 HH-mode

dBc

(1) Measured single ended into 50-

load.

DAC5674

SLWS148 - SEPTEMBER 2003

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ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, differential transformer coupled output, 50-

doubly terminated load (unless otherwise noted)

DIGITAL SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CMOS INTERFACE

VIH

High-level input voltage for SLEEP and EXTLO

0.7xAVDD

VIL

Low-level input voltage for SLEEP and EXTLO

0.3xAVDD

VIH

High-level input voltage other digital inputs

0.7xIOVDD

VIL

Low-level input voltage other digital inputs

0.3xIOVDD

IIH

High-level input current

IIL

Low-level input current

-1

Input capacitance

TIMING INTERNAL CLOCK MODE

tSU

Input setup time

0.6

Input hold time

0.6

tLPH

Input latch pulse high time

tlat_2x

Data in to DAC out latency - 2X interpolation

clk

tlat_4x

Data in to DAC out latency - 4X interpolation

clk

TIMING - EXTERNAL CLOCK MODE

tsu

Input setup time

Input hold time

-1.75

tlph

Input latch pulse high time

td_clk

Clock delay time

3.6

tlat_2x

Data in to DAC out latency - 2X interpolation

clk

tlat_4x

Data in to DAC out latency - 4X interpolation

clk

PLL

Input data rate supported

200

MSPS

Phase noise

At 600-kHz offset

-124

dBc/Hz

Phase noise

At 6-MHz offset

-134

dBc/Hz

DIGITAL FILTER SPECIFICATIONS

fDATA

Input data rate

200

MSPS

FIR1 and FIR2 DIGITAL FILTER CHARACTERISTICS

0.005 db

0.407

Passband width

0.01 dB

0.41

fOUT/

Passband width

0.1 dB

0.427

fOUT/

fDATA

3 dB

0.481

fDATA

DAC5674

SLWS148 - SEPTEMBER 2003

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Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AGND

37, 41, 44

Analog ground return

AVDD

45, 46

Analog supply voltage

BIASJ

Full-scale output current bias

CLK

External clock input

CLKC

Complementary external clock input

CLKGND

Ground return for internal clock buffer

CLKVDD

Internal clock buffer supply voltage

D[13..0]

3-16

Data bits 0 through 13
D13 is most significant data bit (MSB)
D0 is least significant data bit (MSB)

DIV[1..0]

27,28

PLL prescaler divide ratio settings

DGND

1, 2, 19, 24

Digital ground return

DVDD

21, 47, 48

Digital supply voltage

EXTIO

I/O

Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
Used as internal reference output when EXTLO = AGND, requires a 0.1-

F decoupling capacitor to AGND

when used as reference output

EXTLO

For internal reference connect to AGND. Connect to AVDD to disable the internal reference

HP1

Filter 1 high-pass setting. Active high

HP2

Filter 2 high-pass setting. Active high

IOGND

Input digital ground return

IOVDD

Input digital supply voltage

IOUT1

DAC current output. Full scale when all input bits are set 1

IOUT2

DAC complementary current output. Full scale when all input bits are 0

LPF

PLL loop filter connection

PLLGND

Ground return for internal PLL

PLLLOCK

PLL lock status bit. PLL is locked to input clock when high. Provides output clock equal to the data rate
when the PLL is disabled.

PLLVDD

Internal PLL supply voltage. Connect to PLLGND to disable PLL clock multiplier.

RESET

Reset internal registers. Active high

SLEEP

Asynchronous hardware power down input. Active high. Internally pull down.

4x interpolation mode. Active high. Filter 1 is bypassed when connected to DGND

DAC5674

SLWS148 - SEPTEMBER 2003

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TYPICAL CHARACTERISTICS

-1.0

-0.8

-0.6

-0.4

-0.2

-0.0

0.2

0.4

0.6

0.8

1.0

2000

4000

6000

8000

10000

12000

14000

16000

INTEGRAL NONLINEARITY

INPUT CODE

Input Code

INL - Integral Nonlinearity - LSB

VCC = 3.3 V
IOUTfS = 20 mA

Figure 2

-1.0

-0.8

-0.6

-0.4

-0.2

-0.0

0.2

0.4

0.6

0.8

1.0

2000

4000

6000

8000

10000

12000

14000

16000

DIFFERENTIAL NONLINEARITY

INPUT CODE

Input Code

DNL - Differential Nonlinearity - LSB

VCC = 3.3 V
IOUTfS = 20 mA

Figure 3

DAC5674

SLWS148 - SEPTEMBER 2003

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Figure 4

fO - Output Frequency - MHz

VCC = 3.3 V
fS = 50 MSPS
IOUTfS = 20 mA
4x LL-Mode

SFDR - Spurious-Free Dynamic Range - dBc

SPURIOUS-FREE DYNAMIC RANGE

OUTPUT FREQUENCY

0 dBfS

-3 dBfS

-6 dBfS

Figure 5

fO - Output Frequency - MHz

VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4x LL-Mode

SFDR - Spurious-Free Dynamic Range - dBc

SPURIOUS-FREE DYNAMIC RANGE

OUTPUT FREQUENCY

0 dBfS

-6 dBfS

-3 dBfS

Figure 6

f - Frequency - MHz

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

100

125

150

175

200

VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4x LL-Mode
Fout = 10 MHz

Power - dBm

POWER

FREQUENCY

Figure 7

fO - Output Frequency - MHz

VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4x LL-Mode
In Band = 0 - 50 MHz

SFDR - In-Band Spurious-Free Dynamic Range - dBc

IN-BAND

SPURIOUS-FREE DYNAMIC RANGE

OUTPUT FREQUENCY

0 dBfS

-12 dBfS

-6 dBfS

DAC5674

SLWS148 - SEPTEMBER 2003

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Figure 8

fO - Output Frequency - MHz

VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4x LL-Mode
Out-of-Band = 50 - 100 MHz

SFDR - Out-of-Band Spurious-Free Dynamic Range - dBc

OUT-OF-BAND

SPURIOUS-FREE DYNAMIC RANGE

OUTPUT FREQUENCY

0 dBfS

-12 dBfS

-6 dBfS

Figure 9

f - Frequency - MHz

-120

-100

-80

-60

-40

-20

VCC = 3.3 V
fS = 61.44 MSPS
fcarrier = 15.36 MHz
IOUTfS = 20 mA
ACPR = 73.25 dB
4x LL-Mode

P - Power - dBm

POWER

FREQUENCY

Figure 10

f - Frequency - MHz

-120

-100

-80

-60

-40

-20

VCC = 3.3 V
fS = 122.88 MSPS
fcarrier = 30.72 MHz
IOUTfS = 20 mA
ACPR = 70.23 dB
2x L-Mode

P - Power - dBm

POWER

FREQUENCY

Figure 11

f - Frequency - MHz

-120

-100

-80

-60

-40

-20

P - Power - dBm

POWER

FREQUENCY

VCC = 3.3 V
fS =76.80 MSPS
fcarrier = 19.20 MHz

IOUTfS = 20 mA
ACPR = 70.22 dB
4x LL-Mode

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SLWS148 - SEPTEMBER 2003

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Figure 12

f - Frequency - MHz

-120

-100

-80

-60

-40

-20

VCC = 3.3 V
fS = 61.44 MSPS
fcarrier = 15.36 MHz
IOUTfS = 20 mA
ACPR = 69.73 dB
4x LH-Mode

P - Power - dBm

POWER

FREQUENCY

Figure 13

fO - Output Frequency - MHz

VCC = 3.3 V
fS = 78 MSPS
fout1 = fout
fout2 = fout + 1 MHz
IOUTfS = 20 mA
4x LL-Mode

wo-T

one IMD3 - dBc

TWO-TONE IMD3

OUTPUT FREQUENCY

fO - Output Frequency - MHz

VCC = 3.3 V
fS = 78 MSPS
fout1 = fout
fout2 = fout + 4 MHz
IOUTfS = 20 mA
4x LL-Mode

wo-T

one IMD3 - dBc

TWO-TONE IMD3

OUTPUT FREQUENCY

Figure 14

DAC5674

SLWS148 - SEPTEMBER 2003

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DETAILED DESCRIPTION

Figure 1 shows a simplified block diagram of the DAC5674. The CMOS device consists of a segmented array
of PMOS current sources, capable of delivering a full-scale output current up to 20 mA. Differential current
switches direct the current of each current source to either one of the complementary output nodes IOUT1 or
IOUT2. The complementary output currents thus enable differential operation, canceling out common mode
noise sources (digital feed-through, on-chip, and PCB noise), dc offsets, even order distortion components, and
increase signal output power by a factor of two.

The full-scale output current is set using an external resistor R

BIAS

in combination with an on-chip bandgap

voltage reference source (1.2 V) and control amplifier. The current I

BIAS

through resistor R

BIAS

is mirrored

internally to provide a full-scale output current equal to 32 times I

BIAS

. The full-scale current can be adjusted

from 20 mA down to 2 mA.

Interpolation Filter

The interpolation filters FIR1 and FIR2 can be configured for either low-pass or high-pass response. In this way,
higher order images can be selected. This is shown in Table 1. Table 2 shows the DAC IF output range for the
different filter response combinations, for both the first and second Nyquist zone (after interpolation). Table 3
lists the DAC IF output ranges for two popular GSM data rates. Table 3 shows the W-CDMA IF carrier center
frequency for an input data rate of 61.44 MSPS and a fundamental input IF of 15.36 MHz. Figure 15 shows the
spectral response; the corresponding nonzero tap weights are:

[5, -20, 50, -108, 206, -361, 597, -947, 1467, -2267, 3633, -6617, 20746, 32768]

f / fin

-150

-100

-50

0.0

0.2

0.4

0.6

0.8

1.0

Amplitude - dB

AMPLITUDE

FREQUENCY

f / fin

0.0

0.2

0.4

0.6

0.8

1.0

0.005

Amplitude - dB

AMPLITUDE

FREQUENCY

-0.005

0.000

Figure 15. FIR1 and FIR2 Magnitude Spectrum

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SLWS148 - SEPTEMBER 2003

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Table 1. Interpolation Filters Configuration

FILTER 1

CONFIGURATION

FILTER 2

CONFIGURATION

IF OUTPUT RANGE 1

(FIRST NYQUIST ZONE)

IF OUTPUT RANGE 2

(SECOND NYQUIST ZONE)

CONFIGURATION

FREQUENCY

SINX/X ATT. [dB]

FREQUENCY

SINX/X ATT. [dB]

Low pass

...

0.4Fdata

...

0.14

3.6

...

4Fdata

19.2

...

Low pass

High pass

1.6

...

2Fdata

2.42

...

3.92

...

2.4Fdata

3.92

...

5.94

High pass

Low pass

0.6

...

0.8Fdata

0.32

...

0.58

3.2

...

3.4Fdata

12.6

...

15.4

High pass

1.2

...

1.4Fdata

1.33

...

1.83

2.6

...

2.8Fdata

7.20

...

8.69

Table 2. Interpolation Filters Configuration: Example Frequencies GSM

FILTER 1

FILTER 2

IF OUTPUT RANGE 1

(FIRST NYQUIST ZONE)

IF OUTPUT RANGE 2

(SECOND NYQUIST ZONE)

FILTER 1

CONFIGURATION

FILTER 2

CONFIGURATION

IF FREQUENCY [MHz]

CONFIGURATION

Fdata = 52 MSPS

Fdata = 78 MSPS

Fdata = 52 MSPS

Fdata = 78 MSPS

Low pass

...

20.8

...

31.2

187.2

...

208

280.8

...

312

Low pass

High pass

83.2

...

108

124.8

...

156

104

...

124.8

156

...

187.2

High pass

Low pass

31.2

...

41.6

46.8

...

62.4

166.4

...

176.8

249.6

...

265.2

High pass

62.4

...

72.8

93.6

...

109.2

135.2

...

145.6

202.8

...

218.4

Table 3. Interpolation Filters Configuration: Example Frequencies W-CDMA, IF = F

data

/4, F

DATA

= 61.44

MSPS: F

update

= 245.76 MSPS

FILTER 1

CONFIGURATION

FILTER 2

CONFIGURATION

IF FREQUENCY [MHZ]

(FIRST NYQUIST ZONE)

IF FREQUENCY [MHZ]

(SECOND NYQUIST ZONE)

CONFIGURATION

IF CENTER [MHz]

SINX/X ATT. [dB]

IF CENTER [MHz]

SINX/X ATT. [dB]

Low pass

15.36

0.05

230.4

23.6

Low pass

High pass

107.52

2.93

138.24

5.11

High pass

Low pass

46.08

0.51

199.68

13.2

High pass

76.8

1.44

168.96

8.29

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Low-Pass/Low-Pass 4x Interpolation Filter Operation

Figure 16 shows the low-pass/low-pass interpolation operation where the 4x FIR filter is implemented as a
cascade of two 2x interpolation filters. The user can place their IF signal at a maximum of 0.4 times the FIR
filter input (i.e. DAC5674 input) data rate. For a 100-MSPS data rate, this would translate into a pass-band
extending to 40 MHz.

80 dB

Input Spectrum

Output DUC

Normalized IF:IFmax

0.4

Fdata

2Fdata

3Fdata

4Fdata

First

2x Interpolation

Filter

Transition Band

(Fdata

2IF) Fdata

Fdata

2Fdata

3Fdata

4Fdata

Normalized Transition Band

0.4) 1

0.2

Spectrum After

2x Interpolation

Fdata

2Fdata

3Fdata

4Fdata

Second

2x Interpolation

Filter

Fdata

2Fdata

3Fdata

Fdata

Spectrum After

4x Interpolation

Fdata

2Fdata

3Fdata

4Fdata

Fupdate

Transition Band

(Fdata

IF) Fdata

Normalized Transition Band

0.4) 1

0.6

Figure 16. Low-Pass/Low-Pass 4x Interpolation Filter Operation

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Low-Pass/High-Pass 4x Interpolation Filter Operation

By configuring the low-pass filters as high-pass filters the user can select one of the images present at multiples
of the clock. Figure 17 shows the low-pass/high-pass filter response. After digital filtering, the DAC transmits
at
2F

data

- IF and 2F

data

+ IF. This configuration is equivalent to sub-sampling receiver systems where a

high-speed analog-to-digital converter samples high IF frequencies with relatively low sample rates, resulting
in low (output) data rates.

The placement of the IF in the first Nyquist zone combined with the DAC5674 input data determines the final
output signal frequency. For F

data

= 100 MSPS and a fundamental IF of 0.4 x F

data

= 40 MHz, this would translate

into images located at 160 MHz and 240 MHz. Note that this is the equivalent of mixing a 40-MHz analog IF
signal with a 200-MHz sine wave. By doing this, the first mixer in the total transmission chain is eliminated.

80 dB

Input Spectrum

Output DUC

Fdata

2Fdata

3Fdata

4Fdata

First

2x Interpolation

Filter

Fdata

2Fdata

3Fdata

4Fdata

Spectrum After

2x Interpolation

Fdata

2Fdata

3Fdata

4Fdata

Second

2x Interpolation

Filter

Fdata

2Fdata

3Fdata

Fdata

Spectrum After

4x Interpolation

2Fdata

4Fdata

Fupdate

Fdata

)

3Fdata

Transition Band

(Fdata

2IF) Fdata

Normalized Transition Band

0.4) 1

0.2

Transition Band

(Fdata

IF) Fdata

Normalized Transition Band

0.4) 1

0.6

Fdata

3Fdata

Figure 17. Low-Pass 2x, High-Pass 2x Interpolation Filter Operation

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High-Pass/Low-Pass 4x Interpolation Filter Operation

Figure 18 shows the high-pass/low-pass filter configuration. Images at F

data

- IF and 3F

data

+ IF can be

selected. Note that the latter image severely attenuates by the sinx/x response. The transition bands of filter
1 and filter 2 of 0.2 allow for the placement of the fundamental IF between 0.2

...

0.4F

data

. This results in an output

IF of 0.6

...

0.8F

data

80 dB

Input Spectrum

Output DUC

Fdata

2Fdata

3Fdata

4Fdata

First

2x Interpolation

Filter

Fdata

2Fdata

3Fdata

4Fdata

Transition Band

(Fdata

2IF) Fdata

Normalized Transition Band

0.4) 1

0.2

Spectrum After

2x Interpolation

Fdata

2Fdata

3Fdata

4Fdata

Second

2x Interpolation

Filter

Fdata

2Fdata

3Fdata

Fdata

Transition Band

2IF 2Fdata

Normalized Transition Band

0.2 2

0.2

Spectrum After

4x Interpolation

2Fdata

4Fdata

Fupdate

Fdata

)

3Fdata

Fdata

3Fdata

Figure 18. High-Pass 2x, Low-Pass 2x Interpolation Filter Operation

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High-Pass/High-Pass 4x Interpolation Filter Operation

Figure 19 shows the high-pass/high-pass filter configuration. The transition bands of filter 1 and filter 2 allow
for the placement of the fundamental IF between 0.2

...

0.4F

data

. In this configuration the user can select the

images at F

data

+ IF and 3F

data

IF. For F

data

= 100 MSPS and a fundamental IF of 0.4 x F

data

= 40 MHz, this

would translate into images located at 140 MHz and 260 MHz. Note that this is the equivalent of mixing a 60-MHz
analog IF signal with a 200-MHz sine wave.

80 dB

Input Spectrum

Output DUC

Fdata

2Fdata

3Fdata

4Fdata

First

2x Interpolation

Filter

Fdata

2Fdata

3Fdata

4Fdata

Transition Band

(Fdata

2IF) Fdata

Normalized Transition Band

0.4) 1

0.2

Spectrum After

2x Interpolation

Fdata

2Fdata

3Fdata

4Fdata

Second

2x Interpolation

Filter

Fdata

2Fdata

3Fdata

Fdata

Transition Band

2IF 2Fdata

Normalized Transition Band

0.2 2

0.2

Spectrum After

4x Interpolation

2Fdata

4Fdata

Fupdate

Fdata

)

3Fdata

Fdata

3Fdata

Figure 19. High-Pass/High-Pass 4x Interpolation Filter Operation

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IF=32

160

240

320

112

208

100

IF=40

200

300

400

260

140

IF=26

130

195

260

169

"Sinx/x"

Attenuation

Fupdate

65 MSPS

1.83 dB

7.2 dB

"Sinx/x"

Attenuation

Fupdate

80 MSPS

1.83 dB

7.2 dB

"Sinx/x"

Attenuation

Fupdate

100 MSPS

1.83 dB

7.2 dB

Figure 20. High-Pass 4x Interpolation Filter Operation: Example Frequencies

Clock Generation Function

An internal PLL or external clock can be used to derive the internal clocks (1x, 2x, and 4x) for the logic, FIR
interpolation filters, and DAC. Basic functionality is depicted in Figure 21. Power for the internal PLL blocks
(PLLVDD and PLLGND) is separate from the other clock generation blocks power (CLKVDD and CLKGND),
thus minimizing phase noise within the PLL. The PLLVDD pin establishes internal/external clock mode: when
PLLVDD is grounded, external clock mode is active and when PLLVDD is 3.3 V, internal clock mode is active.

In external clock mode, the user provides a differential external clock on pins CLK/CLKC. This clock becomes
the 4x clock and is twice divided down to generate the 2x and 1x clocks. The 2x or 1x clock is multiplexed out
on the PLLLOCK pin to allow for external clock synchronization.

In internal clock mode, the user provides a differential external reference clock on CLK/CLKC. A type four
phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback clock and
drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated by dividing
the VCO output by 1x, 2x, 4x, or 8x, as selected by the prescaler (DIV[1:0]). The output of the prescaler is the
4x clock, and is divided down twice to generate the 2x and 1x clocks. Pin X4 selects the 1x or 2x clock to clock
in the input data; the selected clock is also fed back to the PFD for synchronization. The PLLLOCK pin is an
output indicating when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user
at pin LPF. See the Low-Pass Filter section for filter setting calculations. Table 4 provides a summary of the
clock configurations with corresponding data rate ranges.

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PLLVDD

PLLGND

CLKGND

CLKVDD

CLK

CLKC

PFD

VCO

/1
/2
/4
/8

D[13:0]

DIV[1:0]

PLLVDD

PLLLOCK

LPF

Clk

Buffer

Clk_4x

DAC5674

Charge

Pump

Clk_2x

Clk_1x

Data

Figure 21. Clock Generation Functional Diagram

Table 4. Clock Mode Configuration

CLOCK MODE

PLLVDD

DIV[1:0]

DATA RANGE (MHz)

PLLLOCK PIN FUNCTION

External 2X

0 V

DC to 200

External clock/2

External 4X

0 V

DC to 100

External clock/4

Internal 2X

3.3 V

100 to 200

Internal PLL lock indicator

Internal 2X

3.3 V

50 to 100

Internal PLL lock indicator

Internal 2X

3.3 V

25 to 50

Internal PLL lock indicator

Internal 2X

3.3 V

12 to 25

Internal PLL lock indicator

Internal 4X

3.3 V

50 to 100

Internal PLL lock indicator

Internal 4X

3.3 V

25 to 50

Internal PLL lock indicator

Internal 4X

3.3 V

12 to 25

Internal PLL lock indicator

Internal 4X

3.3 V

5 to 12

Internal PLL lock indicator

Low-Pass Filter

The PLL consists of a type four phase-frequency detector (PFD), charge pump, external low-pass loop filter,
voltage to current converter, and current controlled oscillator (ICO) as shown in Figure 22. The DAC5674
evaluation board comes with component values R = 200, C1 = 0.01

F, and C2 = 100 pF. These values have

been designed to give the phase margins and loop bandwidths listed in Table 5 for the five divide down factors
of prescaling and interpolation. Note that the values derived were based on a charge pump current output of
1 mA and a VCO gain of 300 MHz/V (nominal at Fvco = 400 MHz). With this filter, the settling time from a phase
or frequency disturbance is about 2.5

s. If different PLL dynamics are required, DAC5674 users can design

a second order filter for their application using PLL Loop Filter Components section.

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PFD

ref

ICO

Fref

Fvco

LPF

DAC5674

External Loop Filter

Figure 22. PLL Functional Block Diagram

Table 5. DAC5674 Evaluation Board PLL Loop Filter Parameters

N(1)

PHASE MARGIN (DEGREES)

BANDWIDTH (MHZ)

1.6

1.4

0.7

0.4

(1) N is the VCO divide-down factor from prescale and interpolation.

Digital Inputs

Figure 23 shows a schematic of the equivalent CMOS digital inputs of the DAC5674. The CMOS-compatible
inputs have logic thresholds of IOVDD/2

20%. The 14-bit digital data input follows the offset positive binary

coding scheme.

D[13:0]

SLEEP

EXTLO

DIV[1:0]

RESET

HP1, HP2

Internal
Digital In

IOVDD (AVDD for SLEEP and EXTLO)

IOGND

Figure 23. CMOS/TTL Digital Equivalent Input

Clock Input and Timing

Figure 24 shows the clock and data input timing diagram for internal and external clock modes, respectively.
Note that a negative value indicates a reversal of the edge positions as shown in the timing diagram. Figure 24
also shows the delay (t

) of the 1x/2x data clock (PLLLOCK) from CLK in external clock mode (typical t

4.1

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ns). The latency from data to DAC is defined by Figure 25. The DAC5674 features a differential clock input.
In internal clock mode, the internal data clock is a divided down version of the PLL clock (/2 or /4), depending
on the level of interpolation (2x or 4x). In external mode, the internal data clock is a divided down version of the
input CLK (/2 or /4), depending on the level of interpolation (2x or 4x). Internal edge-triggered flip-flops latch
the input word on the rising edge of the positive data clock.

CLKC

PLLLOCK

D[13:0]

Valid Data

CLK

CLKC

D[13:0]

Valid Data

tsu

tlph

tsu

td_clk

Figure 24. Internal (Left) and External (Right) Clock Mode Timing

2x Interpolation

4x Interpolation

DAC

2000

3FFF

2000

Typical tsu = 0.5 ns, th = 0.1 ns

Typical tsu = 2.9 ns, th = -2.3 ns, td = 3.6 ns

D[13:0]

tlat_nx

Figure 25. Data to DAC Latency

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Figure 26 shows an equivalent circuit for the clock input.

CLK

Internal

Digital In

CLKC

CLKGND

R1
10 k

AVDD

10 k

R2
10 k

AVDD

CLKVDD

Figure 26. Clock Input Equivalent Circuit

Figure 27, Figure 28, Figure 29, and Figure 30 show various input configurations for driving the differential
clock input (CLK/CLKC).

200

CLK

1:4

CLKC

Termination Resistor

Swing Limitation

Optional, May Be Bypassed

for Sine Wave Input

CAC

0.1

Figure 27. Preferred Clock Input Configuration

Ropt

CLK

1:1

CLKC

Optional, Reduces

Clock Feed-Through

CAC

0.01

TTL/CMOS

Source

Ropt

CLK

CLKC

Node CLKC

Internally Biased

to IVDD 2

TTL/CMOS

Source

0.01

Figure 28. Driving the DAC5674 With a Single-Ended TTL/CMOS Clock Source

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CAC

0.01

CAC

0.01

VTT

Differential

ECL

(LV)PECL

Source

CLK

CLKC

Figure 29. Driving the DAC5674 With Differential ECL/PECL Clock Source

CAC

0.01

CAC

0.01

VTT

Single-Ended

ECL

(LV)PECL

Source

ECL/PECL

Gate

CLK

CLKC

Figure 30. Driving the DAC5674 With a Single-Ended ECL/PECL Clock Source

Supply Inputs

The DAC5674 comprises separate analog and digital supplies at AVDD, DVDD, and IOVDD. These supplies
can range from 3 V to 3.6 V for AVDD, 1.65 to 1.95 V for DVDD, and 1.65 to 3.6 for IOVDD.

DAC Transfer Function

The DAC5674 delivers complementary output currents IOUT1 and IOUT2. The DAC supports straight binary
coding, with D13 being the MSB and D0 the LSB. Output current IOUT1 equals the approximate full-scale output
current when all input bits are set high, i.e., the binary input word has the decimal representation 16383.
Full-scale output current flows through terminal IOUT2 when all input bits are set low (mode 0, straight binary
input). The relation between IOUT1 and IOUT2 can thus be expressed as:

IOUT1 = IOUT

IOUT2

Where IOUT

is the full-scale output current. The output currents can be expressed as:

IOUT1

IOUT

CODE

16384

IOUT2

IOUT

16383

CODE

16384

Where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2
drive resistor loads (R

) or a transformer with equivalent input load resistance (R

). This would translate into

single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:

VOUT1

IOUT1

CODE

16384

IOUT

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VOUT2

IOUT2

(16383CODE)

16384

IOUT

The differential output voltage VOUT

DIFF

can thus be expressed as:

VOUT

DIFF

VOUT1VOUT2

(2CODE1683)

16384

IOUT

The latter equation shows that applying the differential output results in doubling of the signal power delivered
to the load. Since the output currents IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Note that care should be taken not to exceed the compliance voltages at node IOUT1
and IOUT2, which would lead to increased signal distortion.

Reference Operation

The DAC5674 comprises a bandgap reference and control amplifier for biasing the full-scale output current.
The full-scale output current is set by applying an external resistor R

BIAS

. The bias current I

BIAS

through resistor

BIAS

is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current

equals 32 times this bias current. The full-scale output current IOUT

can thus be expressed as:

IOUT

BIAS

EXTIO

BIAS

where V

EXTIO

is the voltage at terminal EXTIO. The band-gap reference voltage delivers an accurate voltage

of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
C

EXT

of 0.1

F should be connected externally to terminal EXTIO for compensation. The band-gap reference

can additionally be used for external reference operation. In that case, an external buffer with high impedance
input should be applied in order to limit the band-gap load current to a maximum of 100 nA. The internal
reference can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor
C

EXT

may hence be omitted. Terminal EXTIO serves as either input or output node.

The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor R

BIAS

or changing

the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the
full-scale output current range of 20 mA.

Analog Current Outputs

Figure 31 shows a simplified schematic of the current source array output with corresponding switches.
Differential switches direct the current of each individual PMOS current source to either the positive output node
IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack
of the current sources and differential switches, and is typically >300 k

in parallel with an output capacitance

of 5 pF.

The external output resistors are referred to an external ground. The minimum output compliance at nodes
IOUT1 and IOUT2 is limited to -1 V, determined by the CMOS process. Beyond this value, transistor breakdown
may occur resulting in reduced reliability of the DAC5674 device. The maximum output compliance voltage at
nodes IOUT1 and IOUT2 equals 1.25 V. Exceeding the maximum output compliance voltage adversely affects
distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5
V.

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AVDD

Current Source Array

IOUT1

IOUT2

S(1)

S(1)C

RLOAD

S(2)

S(2)C

S(N)

S(N)C

Figure 31. Equivalent Analog Current Output

The DAC5674 can be easily configured to drive a doubly terminated 50-

cable using a properly selected RF

transformer. Figure 19 and Figure 20 show the 50-

doubly terminated transformer configuration with 1:1 and

4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be
grounded to enable a DC current flow. Applying a 20-mA full-scale output current would lead to a 0.5 V

for

a 1:1 transformer and a 1 V

output for a 4:1 transformer.

Figure 21 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent
load resistance of 25

. Node IOUT2 should be connected to AGND or terminated with a resistor of 25

AGND. The nominal resistor load of 25

gives a differential output swing of 1 V

when applying a 20-mA

full-scale output current.

IOUT1

1:1

IOUT2

RLOAD

100

AGND

Figure 32. Driving a Doubly Terminated 50-

Cable Using a 1:1 Impedance Ratio Transformer

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IOUT1

4:1

IOUT2

100

RLOAD

AGND

Figure 33. Driving a Doubly Terminated 50-

Cable Using a 4:1 Impedance Ratio Transformer

IOUT1

IOUT2

RLOAD

AGND

Figure 34. Driving a Doubly Terminated 50-

Cable Using Single-Ended Output

Sleep Mode

The DAC5674 features a power-down mode that turns off the output current and reduces the supply current
to less than 5 mA over the supply range of 3 V to 3.6 V and temperature range. The power-down mode is
activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal
pulldown circuit at node SLEEP ensures that the DAC5674 is enabled if the input is left disconnected. Power-up
and power-down activation times depend on the value of external capacitor at node SLEEP. For a nominal
capacitor value of 0.1-

F power-down takes less than 5

s, and power-up takes approximately 3 ms.

DAC5674 Evaluation Board

There is a combo EVM board for the DAC5674 digital-to-analog converter for evaluation. This board allows the
user the flexibility to operate the DAC5674 in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. The digital
inputs are designed to interface with a TMS320 DSP SDK or to be driven directly from various pattern
generators with the on-board option to add a resistor network for proper load termination.

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PLL LOOP FILTER COMPONENTS

For the external second order filter shown in Figure 35, the components R, C1, and C2 are calculated for a
desired phase margin and loop bandwidth. The resistance R3 = 200

and the capacitance is C3 = 8 pF are

internal to the DAC5674.

External

Internal

Figure 35. External Second Order Filter

100

150

200

250

300

350

400

450

500

100

200

300

400

500

600

VCO GAIN

FREQUENCY

Frequency - MHz

VCO Gain - MHz

Figure 36. Typical DAC5674 G

VCO

at 25

The VCO gain (G

VCO

) as a function of VCO frequency for the DAC5674 is shown in Figure 36. For a desired

VCO frequency, the loop filter values can be calculated using the equation below.

Nominal PLL design parameters include:

charge pump current: iqp = 1 mA

vco gain: Kvco = 2

xGvco rad/A

prescale/interpolation divide: N = {2,4,8,16,32}

phase detector gain: Kd = iqpx(2

-1

A/rad

Let,

desired loop band width =

desired phase margin =

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then,

+ t

1 1

+ t

where

Kvco

2
d

tan

)

sec

tan

)

sec

tan

)

sec

Example:

= 70 degrees,

= 1 MHz

then,

R (

)

C1 (

C2 (PF)

0.02

670

0.01

335

173

0.005

167

346

0.002

692

0.001

The calculated phase margin and loop band width can be verified by plotting the gain and phase of the open
loop transfer function given by:

H(s)

vco

(

)

sRC1)

RC1C2

)

(C1

)

C2)

Figure 37 shows the open loop gain and phase for the DAC5674 evaluation board loop filter.

f - Frequency - MHz

Gain - dB

GAIN

FREQUENCY

0.01

0.1

100

-180

-160

-140

-120

-100

f - Frequency - MHz

Phase -

PHASE

FREQUENCY

0.01

0.1

100

-20

-40

-60

N = 2, 4, 8, 16, 32

Figure 37. Open Loop Phase and Gain Plots for the DAC5674 Evaluation Board

The phase error (

err

) phase and frequency step responses are given by the equations below and are plotted

in Figure 24 for the DAC5674 evaluation board loop filter.

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err

+ Df

) w

Phase step response

err

+ Dw

Frequency step response

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

t - Time -

Normalized Phase Error

NORMALIZED PHASE ERROR

TIME

Response to a Frequency Step at Time 0

N = 2, 4, 8, 16, 32

Increasing N

t - Time -

-0.5

0.0

0.5

1.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Normalized Phase Error

NORMALIZED PHASE ERROR

TIME

Response to a Phase Step at Time 0

N = 2, 4, 8, 16, 32

Increasing N

Figure 38. Phase and Frequency Step Responses for the DAC5674 Evaluation Board

IMPORTANT NOTICE

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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products

Applications

Amplifiers

amplifier.ti.com

Audio

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

www.ti.com/broadband

Interface

interface.ti.com

Digital Control

www.ti.com/digitalcontrol

Logic

logic.ti.com

Military

www.ti.com/military

Power Mgmt

power.ti.com

Optical Networking

www.ti.com/opticalnetwork

Microcontrollers

microcontroller.ti.com

Security

www.ti.com/security

Telephony

www.ti.com/telephony

Video & Imaging

www.ti.com/video

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

2004, Texas Instruments Incorporated

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