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Электронный компонент: DAC6571

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FEATURES
DESCRIPTION
APPLICATIONS
V
DD
SCL
A0
GND
Output
Buffer
Power Down
Control Logic
Resistor
Network
Ref (+) REF(-)
10-Bit
DAC
I
2
C
Control
Logic
DAC
Register
Power-On
Reset
V
OUT
SDA
DAC6571
SLAS406 DECEMBER 2003
+2.7 V to +5.5 V, I
2
C INTERFACE, VOLTAGE OUTPUT,
10-BIT DIGITAL-TO-ANALOG CONVERTER
Micropower Operation: 125 A @ 3 V
The DAC6571 is a low-power, single channel, 10-Bit
Fast Update Rate: 188 kSPS
buffered voltage output DAC. Its on-chip precision
output amplifier allows rail-to-rail output swing to be
Power-On Reset to Zero
achieved. The DAC6571 utilizes an I
2
C compatible
+2.7 V to +5.5 V Power Supply
two wire serial interface that operates at clock rates
Specified Monotonic by Design
up to 3.4 Mbps with address support of up to two
I
2
CTM Interface up to 3.4 Mbps
DAC6571s on the same data bus.
On-Chip Output Buffer Amplifier, Rail-to-Rail
The output voltage range of the DAC is 0 V to V
DD
.
Operation
The DAC6571 incorporates a power-on-reset circuit
Double-Buffered Input Register
that ensures that the DAC output powers up at zero
Address Support for up to Two DAC6571s
volts and remains there until a valid write to the
device
takes
place.
The
DAC6571
contains
a
Small 6 Lead SOT 23 Package
power-down feature, accessed via the internal control
Operation From -40
C to 105
C
register, that reduces the current consumption of the
device to 50 nA at 5 V.
The low power consumption of this part in normal
Process Control
operation makes it ideally suited for portable battery
Data Acquistion Systems
operated equipment. The power consumption is less
Closed-Loop Servo Control
than 0.7 mW at V
DD
= 5 V reducing to 1 W in
PC Peripherals
power-down mode.
Portable Instrumentation
DAC7571/6571/5571 are 12/10/8 bit single channel
I
2
C DACs from the same family. DAC7574/6574/5574
and DAC7573/6573/5573 are 12/10/8 bit quad chan-
nel
I
2
C
DACs.
Also
see
DAC8571/8574
for
single/quad channel 16-bit I
2
C DACs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I
2
C is a trademark of Philips Corporation.
PRODUCTION DATA information is current as of publication date.
Copyright 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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PIN CONFIGURATIONS
A0
SCL
SDA
6
5
4
1
2
3
V
OUT
GND
V
DD
D671
1
2
3
6
5
4
YMLL
(TOP VIEW)
(BOTTOM VIEW)
Lot Trace Code
ABSOLUTE MAXIMUM RATINGS
(1)
DAC6571
SLAS406 DECEMBER 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
PACKAGE
ORDERING
PRODUCT
PACKAGE
TEMPERATURE
TRANSPORT MEDIA
DESIGNATOR
MARKING
NUMBER
RANGE
DAC6571IDBVT
250 Piece Small Tape and Reel
DAC6571
SOT23-6
DBV
-40
C to +105
C
D671
DAC6571IDBVR
3000 Piece Tape and Reel
PIN DESCRIPTION (SOT23-6)
PIN
NAME
DESCRIPTION
1
V
OUT
Analog output voltage from DAC
Ground reference point for all
2
GND
circuitry on the part
3
V
DD
Analog Voltage Supply Input
4
SDA
Serial Data Input
5
SCL
Serial Clock Input
6
A0
Device Address Select
LOT
Year (3 = 2003); M onth (19 = JANSEP; A=OCT,
TRACE
B=NOV, C=DEC); LL Random code generated
CODE:
when assembly is requested
UNITS
V
DD
to GND
-0.3V to +6V
Digital Input voltage to GND
-0.3 V to +V
DD
+ 0.3 V
V
OUT
to GND
-0.3 V to +V
DD
+ 0.3 V
Operating temperature range
-40
C to + 105
C
Storage temperature range
-65
C to + 150
C
Junction temperature range (T
J
max)
+ 150
C
Power dissipation
(T
J
max - T
A
)R
JA
Thermal impedance, R
JA
240
C/W
Lead temperature, soldering
Vapor phase (60s)
215
C
Infrared (15s)
220
C
(1)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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ELECTRICAL CHARACTERISTICS
DAC6571
SLAS406 DECEMBER 2003
V
DD
= +2.7 V to +5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications -40
C to +105
C unless otherwise noted.
DAC6571
PARAMETER
CONDITIONS
UNITS
MIN
TYP
MAX
STATIC PERFORMANCE
(1)
Resolution
10
Bits
Relative accuracy
2
LSB
Differential nonlinearity
Assured monotonic by design
0.5
LSB
Zero code error
All zeroes loaded to DAC register
5
20
mV
Full-scale error
All ones loaded to DAC register
-0.15
-1.25
% of FSR
Gain error
1.25
% of FSR
Zero code error drift
7
V/
C
Gain temperature coefficient
3
ppm of FSR/
C
OUTPUT CHARACTERISTICS
(2)
Output voltage range
0
V
DD
V
1/4 Scale to 3/4 scale change (400
H
to C00
H
) ;
Output voltage settling time
7
9
s
R
L
=
Slew rate
1
V/s
R
L
=
470
pF
Capacitive load stability
R
L
= 2k
1000
pF
Code change glitch impulse
1 LSB Change around major carry
20
nV-s
Digital feedthrough
0.5
nV-s
DC output impedance
1
V
DD
= +5V
50
mA
Short-circuit current
V
DD
= +3V
20
mA
Coming out of power-down mode, V
DD
= +5V
2.5
s
Power-up time
Coming out of power-down mode, V
DD
= +3V
5
s
LOGIC INPUTS
(2)
Input current
1
A
V
IN
L, Input low voltage
V
DD
= +3V
0.3
V
DD
V
0.7
V
D
V
IN
H, Input high voltage
V
DD
= +5V
V
D
Pin capacitance
3
pF
POWER REQUIREMENTS
V
DD
2.7
5.5
V
I
DD
(normal operation)
DAC active and excluding load current
V
DD
= +3.6V to +5.5V
V
IH
= V
DD
and V
IL
= GND
155
200
A
V
DD
= +2.7V to +3.6V
V
IH
= V
DD
and V
IL
= GND
125
160
A
I
DD
(all power-down modes)
V
DD
= +3.6 V to +5.5V
V
IH
= V
DD
and V
IL
= GND
0.2
1
A
V
DD
= +2.7V to +3.6V
V
IH
= V
DD
and V
IL
= GND
0.05
1
A
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2mA, V
DD
= +5V
93
%
(1)
Linearity calculated using a reduced code range of 12 to 1012; output unloaded.
(2)
Specified by design and characterization, not production tested.
3
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TIMING CHARACTERISTICS
DAC6571
SLAS406 DECEMBER 2003
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Standard mode
100
kHz
Fast mode
400
kHz
f
SCL
SCL Clock Frequency
High-speed mode, C
B
- 100pF max
3.4
MHz
High-Speed mode, C
B
- 400pF max
1.7
MHz
Standard mode
4.7
s
Bus Free Time Between a STOP
t
BUF
and START Condition
Fast mode
1.3
s
Standard mode
4.0
s
Hold Time (Repeated) START
t
HD
; t
STA
Fast mode
600
ns
Condition
High-speed mode
160
ns
Standard mode
4.7
s
Fast mode
1.3
s
t
LOW
LOW Period of the SCL Clock
High-speed mode, C
B
- 100pF max
160
ns
High-speed mode, C
B
- 400pF max
320
ns
Standard mode
4.0
s
Fast mode
600
ns
t
HIGH
HIGH Period of the SCL Clock
High-speed mode, C
B
- 100pF max
60
ns
High-speed mode, C
B
- 400pF max
120
ns
Standard mode
4.7
s
Setup Time for a Repeated
t
SU
; t
STA
Fast mode
600
ns
START Condition
High-speed mode
160
ns
Standard mode
250
ns
t
SU
; t
DAT
Data Setup Time
Fast mode
100
ns
High-speed mode
10
ns
Standard mode
0
3.45
s
Fast mode
0
0.9
s
t
HD
; t
DAT
Data Hold Time
High-speed mode, C
B
- 100pF max
0
70
ns
High-speed mode, C
B
- 400pF max
0
150
ns
Standard mode
20
0.1C
B
1000
ns
Fast mode
20
0.1C
B
300
ns
t
RCL
Rise Time of SCL Signal
High-speed mode, C
B
- 100pF max
10
40
ns
High-speed mode, C
B
- 400pF max
20
80
ns
Standard mode
20
0.1C
B
1000
ns
Rise Time of SCL Signal After a
Fast mode
20
0.1C
B
300
ns
t
RCL1
Repeated START Condition and
High-speed mode, C
B
- 100pF max
10
80
ns
After an Acknowledge BIT
High-speed mode, C
B
- 400pF max
20
160
ns
Standard mode
20
0.1C
B
300
ns
Fast mode
20
0.1C
B
300
ns
t
FCL
Fall Time of SCL Signal
High-speed mode, C
B
- 100pF max
10
40
ns
High-speed mode, C
B
- 400pF max
20
80
ns
Standard mode
20
0.1C
B
1000
ns
Fast mode
20
0.1C
B
300
ns
t
RDA
Rise Time of SDA Signal
High-speed mode, C
B
- 100pF max
10
80
ns
High-speed mode, C
B
- 400pF max
20
160
ns
Standard mode
20
0.1C
B
300
ns
Fast mode
20
0.1C
B
300
ns
t
FDA
Fall Time of SDA Signal
High-speed mode, C
B
- 100pF max
10
80
ns
High-speed mode, C
B
- 400pF max
20
160
ns
4
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DAC6571
SLAS406 DECEMBER 2003
TIMING CHARACTERISTICS (continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Standard mode
4.0
s
t
SU
; t
STO
Setup Time for STOP Condition
Fast mode
600
ns
High-speed mode
160
ns
C
B
Capacitive Load for SDA and SCL
400
pF
Fast mode
50
ns
t
SP
Pulse Width of Spike Suppressed
High-speed mode
10
ns
Standard mode
Noise Margin at the HIGH Level
V
NH
for Each Connected Device
Fast mode
0.2V
DD
V
(Including Hysteresis)
High-speed mode
Standard mode
Noise Margin at the LOW Level for
V
NL
Each Connected Device
Fast mode
0.1V
DD
V
(Including Hysteresis)
High-speed mode
5
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TYPICAL CHARACTERISTICS: V
DD
= +5 V
-2
-1
0
1
2
-0.5
-0.25
0
0.25
0.5
0
128
256
384
512
640
768
896
1024
Digital Input Code
LE - LSB
DLE - LSB
V
DD
= 5 V at 25
C
Digital Input Code
LE - LSB
DLE - LSB
-2
-1
0
1
2
-0.5
-0.25
0
0.25
0.5
0
128
256
384
512
640
768
896
1024
V
DD
= 5 V at -40
C
-16
-8
0
8
16
0
128
256
384
512
640
768
896
1024
V
DD
= 5 V, T
A
= 25
C
Digital Input Code
Output Error (mV)
-2
-1
0
1
2
-0.5
-0.25
0
0.25
0.5
0
128
256
384
512
640
768
896
1024
Digital Input Code
V
DD
= 5 V at 105
C
LE - LSB
DLE - LSB
-30
-20
-10
0
10
20
30
-50 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90 100 110
Full-Scale Error - mV
T - Temperature -
_
C
V
DD
= 5 V
-30
-20
-10
0
10
20
30
-50 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90
110
Zero-Scale Error - mV
T - Temperature -
_
C
V
DD
= 5 V
100
DAC6571
SLAS406 DECEMBER 2003
At T
A
= +25
C, +V
DD
= +5 V, unless otherwise noted.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
CODE (-40
C)
CODE (+25
C )
Figure 1.
Figure 2.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
CODE (+105
C)
TYPICAL TOTAL UNADJUSTED ERROR
Figure 3.
Figure 4.
ZERO-SCALE ERROR
FULL-SCALE ERROR
vs
vs
TEMPERATURE
TEMPERATURE
Figure 5.
Figure 6.
6
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I
DD
- Supply Current -
m
A
0
500
1000
1500
2000
2500
80
90
100
1
10
120
130
140
150
160
170
180
190
200
f - Frequency - Hz
V
DD
= 5 V
0
V
O
U
T
(
V
)
I
SOURCE/SINK
(mA)
5
10
15
5
4
3
2
1
0
DAC Loaded with 3FF
H
DAC Loaded with 00
H
0
50
100
150
200
250
300
-50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110
- Supply Current -
I DD
A
T - Temperature -
_
C
V
DD
= 5 V
0
100
200
300
400
500
0H
BH
80H 100H 180H 200H 280H 300H 380H 3F3H 3FFH
I DD
A
- Supply Current -
Code
V
DD
= 5 V
0
50
100
150
200
250
300
2.7
3.2
3.7
4.2
4.7
5.2
5.7
- Supply Current -
I DD
A
V
DD
- Supply Voltage - V
2.7
I
D
D

(
n
A
)
V
DD
(V)
3.2
3.7
4.2
4.7
5.2
5.7
100
90
80
70
60
50
40
30
20
10
0
+25
C
40
C
+105
C
DAC6571
SLAS406 DECEMBER 2003
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)
At T
A
= +25
C, +V
DD
= +5 V, unless otherwise noted.
I
DD
HISTOGRAM
SOURCE AND SINK CURRENT CAPABILITY
Figure 7.
Figure 8.
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
CODE
TEMPERATURE
Figure 9.
Figure 10.
SUPPLY CURRENT
POWER-DOWN CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
Figure 11.
Figure 12.
7
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CLK (5V/div)
V
OUT
(1V/div)
Time (1
s/div)
Full-Scale Code Change
00
H
to 3FF
H
Output Loaded with
2 K
and 200pF to GND
0
I
D
D

(
A
)
V
LOGIC
(V)
1
2
3
4
5
2500
2000
1500
1000
500
0
Time
CLK (5V/div)
V
OUT
(1V/div)
1023 to 0
Output Loaded with
2 k
W
and 200 pF to GND
Full-Scale Code Change
1
m
s/div
Time (1
s/div)
CLK (5V/div)
V
OUT
(1V/div)
Half-Scale Code Change
Output Loaded with
2k
and 200pF to GND
256 to 768
(1
s /d iv)
C LK (5 V /div)
V
O U T
(1V /div )
H alf-S ca le C o de C ha nge
O utpu t Lo ad ed w ith
2k
an d 20 0pF to G N D
768 to 256
Time
Time (20
s/div)
Loaded with 2k
to V
DD
.
V
DD
(1V/div)
V
OUT
(1V/div)
DAC6571
SLAS406 DECEMBER 2003
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)
At T
A
= +25
C, +V
DD
= +5 V, unless otherwise noted.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
FULL-SCALE SETTLING TIME
Figure 13.
Figure 14.
FULL-SCALE SETTLING TIME
HALF-SCALE SETTLING TIME
Figure 15.
Figure 16.
HALF-SCALE SETTLING TIME
POWER-ON RESET TO 0V
Figure 17.
Figure 18.
8
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Time (0.5
s/div)
Loa ded w ith
2 k
and 2 00p F to G N D .
C ode C hang e:
V
O
U
T
(
2
0
m
V
/
d
i
v
)
512 to 511
Time (5
s/div)
CLK (5V/div)
V
OUT
(1V/div)
DAC6571
SLAS406 DECEMBER 2003
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)
At T
A
= +25
C, +V
DD
= +5 V, unless otherwise noted.
EXITING POWER-DOWN
(512 Loaded)
CODE CHANGE GLITCH
Figure 19.
Figure 20.
9
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TYPICAL CHARACTERISTICS: V
DD
= +2.7V
-2
-1
0
1
2
-0.5
-0.25
0
0.25
0.5
0
128
256
384
512
640
768
896
1024
Digital Input Code
V
DD
= 2.7 V at 25
C
LE - LSB
DLE - LSB
-2
-1
0
1
2
-0.5
-0.25
0
0.25
0.5
0
128
256
384
512
640
768
896
1024
Digital Input Code
V
DD
= 2.7 V at -40
C
LE - LSB
DLE - LSB
-2
-1
0
1
2
-0.5
-0.25
0
0.25
0.5
0
128
256
384
512
640
768
896
1024
Digital Input Code
V
DD
= 2.7 V at 105
C
LE - LSB
DLE - LSB
Digital Input Code
Output Error (mV)
-16
-8
0
8
16
0
128
256
384
512
640
768
896
1024
V
DD
= 2.7 V, T
A
= 25
C
DAC6571
SLAS406 DECEMBER 2003
At T
A
= +25
C, +V
DD
= +2.7V, unless otherwise noted.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
CODE (-40
C)
CODE (+25
C)
Figure 21.
Figure 22.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
OUTPUT ERROR
vs
vs
CODE (+105
C)
CODE (+25
C)
Figure 23.
Figure 24.
10
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-30
-20
-10
0
10
20
30
-50 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90 100 110
Zero-Scale Erro - mV
T - Temperature -
_
C
V
DD
= 2.7 V
-30
-20
-10
0
10
20
30
-50 -40-30 -20 -10 0
10 20 30 40 50 60 70 80 90 100 110
Full-Scale Error - mV
T - Temperature -
_
C
V
DD
= 2.7 V
I
DD
- Supply Current -
m
A
f - Frequency - Hz
0
500
1000
1500
2000
2500
80
90
100
1
10
120
130
140
150
160
170
180
190
200
V
DD
= 2.7 V
0
V
O
U
T
(
V
)
I
S O U R C E /S IN K
(m A )
5
1 0
1 5
3
2
1
0
D A C Lo ad ed w ith
D A C Lo ade d w ith 000
H
V
D D
= + 3V
3FF
H
0
100
200
300
400
500
0H
BH
80H 100H 180H 200H 280H 300H 380H 3F3H 3FFH
I DD
A
- Supply Current -
Code
V
DD
= 2.7 V
- Supply Current -
I DD
A
T - Temperature -
_
C
0
50
100
150
200
250
300
-50 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90 100 110
V
DD
= 2.7 V
DAC6571
SLAS406 DECEMBER 2003
TYPICAL CHARACTERISTICS: V
DD
= +2.7V (continued)
At T
A
= +25
C, +V
DD
= +2.7V, unless otherwise noted.
ZERO-SCALE ERROR
FULL-SCALE ERROR
vs
vs
TEMPERATURE
TEMPERATURE
Figure 25.
Figure 26.
I
DD
HISTOGRAM
SOURCE AND SINK CURRENT CAPABILITY
Figure 27.
Figure 28.
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
CODE
9 TEMPERATURE
Figure 29.
Figure 30.
11
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Tim e (1
s/d iv )
C LK (2.7V /div )
V
O U T
(1V /div )
F ull-S c ale C o de C h an ge
000
H
to 3 FF
H
O utpu t L oad ed w ith
2 k
an d 200 pF to G N D
0
I
D
D

(
A
)
V
LOGIC
(V)
1
2
3
4
5
2500
2000
1500
1000
500
0
Time (1
s/div)
CLK (2.7V/div)
V
OUT
(1V/div)
Full-Scale Code Change
3FF
H
to 000
H
Output Loaded with
2 k
and 200pF to GND
Time (1
s/div)
CLK (2.7V/div)
V
OUT
(1V/div)
Half-Scale Code Change
Output Loaded with
2 k
and 200 pF to GND
256 to 768
Time (1
s/div)
C LK (2.7V /div )
V
O U T
(1V /d iv )
H alf-S ca le C ode C ha nge
O u tp ut Lo aded w ith
2 k
and 200 pF to GND
768 to 256
POWER-ON RESET to 0V
Time (20
s/div)
DAC6571
SLAS406 DECEMBER 2003
TYPICAL CHARACTERISTICS: V
DD
= +2.7V (continued)
At T
A
= +25
C, +V
DD
= +2.7V, unless otherwise noted.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
FULL SCALE SETTLING TIME
Figure 31.
Figure 32.
FULL SCALE SETTLING TIME
HALF SCALE SETTLING TIME
Figure 33.
Figure 34.
HALF SCALE SETTLING TIME
POWER ON RESET 0 V
Figure 35.
Figure 36.
12
www.ti.com
Time (0.5
s/div)
Loa de d w ith 2k
W
and 2 00pF to G N D .
C ode C hange :
V
O
U
T
(
2
0
m
V
/
d
i
v
)
512 to 511
H
Time (5
s/div)
CLK (2.7V/div)
V
OUT
(1V/div)
DAC6571
SLAS406 DECEMBER 2003
TYPICAL CHARACTERISTICS: V
DD
= +2.7V (continued)
At T
A
= +25
C, +V
DD
= +2.7V, unless otherwise noted.
EXITING-POWER DOWN (512 Loaded)
CODE CHANGE GLITCH
Figure 37.
Figure 38.
13
www.ti.com
THEORY OF OPERATION
D/A SECTION
_
+
Resistor String
Ref+
Ref-
DAC Register
V
OUT
50 k
W
50 k
W
V
DD
GND
70 k
W
V
OUT
+ VDD
D
1024
RESISTOR STRING
V
DD
To Output
Amplifier
R
R
R
R
GND
Output Amplifier
I
2
C Interface
DAC6571
SLAS406 DECEMBER 2003
The architecture of the DAC6571 consists of a string DAC followed by an output buffer amplifier.Figure 39 shows
a generalized block diagram of the DAC architecture.
Figure 39. R-String DAC Architecture
The input coding to the DAC6571 is unsigned binary, which gives the ideal output voltage as:
Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 1023.
The resistor string section is shown in Figure 40. It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the ouptupt amplifier by closing one of the switches connecting the string to
the amplifier. Because the acrhitecture consists of a string of resistors, it is specified monotonic.
Figure 40. Typical Resistor String
The output buffer amplifier is a gain-of-2 amplifier, capable of generating rail-to-rail voltages on its output, which
gives an output range of 0 V to V
DD
. It is capable of driving a load of 2 k
in parallel with 1000 pF to GND. The
source and sink capabilities of the output amplifier can be seen in the typical characteristics curves. The slew
rate is 1 V/s with a half-scale settling time of 7 s with the output unloaded.
I
2
C is a 2-wire serial interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.
14
www.ti.com
F/S-Mode Protocol
HS-Mode Protocol
Start
Condition
SDA
Stop
Condition
SDA
SCL
S
P
SCL
DAC6571
SLAS406 DECEMBER 2003
THEORY OF OPERATION (continued)
The DAC6571 works as a slave and supports the following data transfer modes, as defined in the I
2
C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data
transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in
this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as
HS-mode. The DAC6571 supports 7-bit addressing; 10-bit addressing and general call address are not
supported.
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 41. All I
2
C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 43) by pulling the SDA line low
during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link
with the addressed slave. All I
2
C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the
HS master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps
operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated
start conditions should be used to secure the bus in HS-mode.
Figure 41. START and STOP Conditions
15
www.ti.com
Change of Data Allowed
Data Line
Stable;
Data Valid
SDA
SCL
Not Acknowledge
Acknowledge
1
2
8
9
Clock Pulse for
Acknowledgement
S
START
Condition
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1
2
7
8
9
ACK
1
2
3 - 8
9
ACK
Address
R/W
DAC6571
SLAS406 DECEMBER 2003
THEORY OF OPERATION (continued)
Figure 42. Bit Transfer on the I
2
C Bus
Figure 43. Acknowledge on the I
2
C Bus
Figure 44. Bus Protocol
16
www.ti.com
DAC6571 I
2
C Update Sequence
Address Byte
Broadcast Address Byte
Control - Most Significant Byte
Least Significant Byte
DAC6571
SLAS406 DECEMBER 2003
THEORY OF OPERATION (continued)
The DAC6571 requires a start condition, a valid I
2
C address, a control-MSB byte, and an LSB byte for a single
update. After the receipt of each byte, DAC6571 acknowledges by pulling the SDA line low during the high period
of a single clock pulse. A valid I
2
C address selects the DAC6571. The CTRL/MSB byte sets the operational
mode of the DAC6571, and the 4 most significant bits. The DAC6571 then receives the LSB byte containing 6
least significant data bits. DAC6571 performs an update on the falling edge of the acknowledge signal that
follows the LSB byte.
For the first update, DAC6571 requires a start condition, a valid I
2
C address, a CTRL/MSB byte, an LSB byte.
For all consecutive updates, DAC6571 needs a CTRL/MSB byte, and an LSB byte.
Using the I
2
C high-speed mode (f
scl
= 3.4 MHz), the clock running at 3.4 MHz, each 10-bit DAC update other than
the first update can be done within 18 clock cycles (CTRL/MSB byte, acknowledge signal, LSB byte,
acknowledge signal), at 188.88 KSPS. Using the fast mode (f
scl
= 400 kHz), clock running at 400 kHz, maximum
DAC update rate is limited to 22.22 KSPS. Once a stop condition is received, DAC6571 releases the I
2
C bus and
awaits a new start condition.
MSB
LSB
1
0
0
1
1
0
A0
0
The address byte is the first byte received following the START condition from the master device. The first six
bits (MSBs) of the address are factory preset to 100110. The next bit of the address is the device select bit A0.
The A0 address input can be connected to V
DD
or digital GND, or can be actively driven by TTL/CMOS logic
levels. The device address is set by the state of this pin during the power-up sequence of the DAC6571. Up to 2
devices (DAC6571) can be connected to the same I
2
C-Bus without requiring additional glue logic.
MSB
LSB
1
0
0
1
0
0
0
0
Broadcast addressing is also supported by DAC6571. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC6571 devices. Using the broadcast address, DAC6571 responds
regardless of the state of the address pin A0.
Most Significant Byte CTRL/MSB[7:0] consists of two zeros, two power-down bits, and four most significant bits
of 10-bit unsigned binary D/A conversion data.
Least Significant Byte LSB[7:0] consists of the 6 least significant bits of the 10-bit unsigned binary D/A
conversion data, followed by 2 don't care bits. DAC6571 updates at the falling edge of the acknowledge signal
that follows the LSB[0] bit.
17
www.ti.com
SLAVE ADDRESS
0
A
Ctrl/MS-Byte
A
LS-Byte
A/A
P
"0" (write)
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
From Master to DAC6571
From DAC6571 to Master
A = Acknowledge (SDA LOW)
A = Not Acknowledge (SDA HIGH)
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
DAC6571 I
2
C-SLAVE ADDRESS:
1
0
0
1
1
0
A0
0
MSB
LSB
Factory Preset
A0 = I
2
C Address Pin
Standard-and Fast-Mode:
S
HS-Master Code
0
A
Ctrl/MS-Byte
A
LS-Byte
A/A
P
"0" (write)
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
High-Speed-Mode (HS-Mode):
S
A Sr Slave Address
HS-Mode Continues
F/S-Mode
HS-Mode
F/S-Mode
Sr Slave Address
0
0
0
0
1
X
X
0
MSB
LSB
HS-Mode Master Code:
0
0
PD1
PD2
D9
D8
D7
D6
MSB
LSB
Ctrl/MS-Byte:
D5
D4
D3
D2
D1
D0
X
X
MSB
LSB
LS-Byte:
D9 - D0 = Data Bits
DAC6571
SLAS406 DECEMBER 2003
Figure 45. Master Transmitter Addressing DAC6571 as a Slave Receiver With a 7-Bit Address
18
www.ti.com
POWER-ON RESET
POWER-DOWN MODES
Resistor
String DAC
Powerdown
Circuitry
V
OUT
Amplifier
Resistor
Network
CURRENT CONSUMPTION
DRIVING RESISTIVE AND CAPACITIVE LOADS
DAC6571
SLAS406 DECEMBER 2003
The DAC6571 contains a power-on reset circuit that controls the output voltage during power-up. On power-up,
the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a valid
write sequence is made to the DAC. This is useful in applications where it is important to know the state of the
DAC output while it is in the process of powering up.
The DAC6571 contains four separate modes of operation. These modes are programmable via two bits (PD1
and PD0). Table 1 shows how the state of these bits correspond to the mode of operation.
Table 1. Modes of Operation for the DAC6571
PD1
PD0
OPERATING MODE
0
0
Normal Operation
0
1
1k
to AGND, PWD
1
0
100k
to AGND, PWD
1
1
High Impedance, PWD
When both bits are set to 0, the device works normally with normal power consumption of 150 A at 5V.
However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only
does the supply current fall but the output stage is also internally switched from the output of the amplifier to a
resistor network of known values. This has the advantage that the output impedance of the device is known while
in power-down mode. There are three different options: The output is connected internally to AGND through a 1
k
resistor, a 100 k
resistor, or it is left open-circuited (high impedance). The output stage is illustrated in
Figure 46.
Figure 46. Output Stage During Power-Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time required to exit power down is typically 2.5 s for AV
DD
=
5 V and 5 s for AV
DD
= 3V. See the Typical Characteristics for more information.
The DAC6571 typically consumes 150 A at V
DD
= 5 V and 120 A at V
DD
= 3 V. Additional current consumption
can occur due to the digital inputs if V
IH
<< V
DD
. For most efficient power operation, CMOS logic levels are
recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200 nA.
The DAC6571 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC6571 can operate rail-to-rail when driving a capacitive load. When the outputs of
the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output
stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity
performance of the DAC. This may occur within approximately the top 20 mV of the DAC's digital input-to-voltage
output transfer characteristic.
19
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OUTPUT VOLTAGE STABILITY
APPLICATIONS
USING REF02 AS A POWER SUPPLY FOR THE DAC6571
REF02
15 V
5 V
1.14 mA
A0
SCL
SDA
I
2
C
Interface
V
OUT
= 0 V to 5 V
DAC6571
LAYOUT
DAC6571
SLAS406 DECEMBER 2003
The DAC6571 exhibits excellent temperature stability of 5 ppm/
C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage to stay within a
25 V window for a
1
C
ambient temperature change. Combined with good dc noise performance and true 10-bit differential linearity, the
DAC6571 becomes a perfect choice for closed-loop control applications.
Due to the extremely low supply current required by the DAC6571, a possible configuration is to use a REF02 +5
V precision voltage reference to supply the required voltage to the DAC6571's supply input as well as the
reference input, as shown in Figure 47. This is especially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V. The REF02 will output a steady supply voltage for the
DAC6571. If the REF02 is used, the current it needs to supply to the DAC6571 is 140 A typical. When a DAC
output is loaded, the REF02 also needs to supply the current to the load. The total typical current required (with a
5 mW load on a given DAC output) is: 140 A + (5 mW/5 V) = 1.14 mA.
The load regulation of the REF02 is typically (0.005%
V
DD
)/mA, which results in an error of 0.285 mV for the
1.14 mA current drawn from it. This corresponds to a 0.05 LSB error for a 0 V to 5 V output range.
Figure 47. REF02 as Power Supply to DAC6571
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The power applied to V
DD
should be well regulated and low noise. Switching power supplies and DC/DC
converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, V
DD
should be connected to a +5V power supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. In addition, the 1 F to 10
F and 0.1 F bypass capacitors are strongly recommended. In some situations, additional bypassing may be
required, such as a 100F electrolytic capacitor or even a Pi filter made up of inductors and capacitors--all
designed to essentially low-pass filter the +5V supply, removing the high-frequency noise.
20
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