Low Cost 12-Bit CMOS

Four-Quadrant Multiplying

DIGITAL-TO-ANALOG CONVERTER

FEATURES

FULL FOUR-QUADRANT
MULTIPLICATION

12-BIT END-POINT LINEARITY

DIFFERENTIAL LINEARITY

1/2LSB MAX

OVER TEMPERATURE

MONOTONICITY GUARANTEED OVER
TEMPERATURE

TTL-/CMOS-COMPATIBLE

SINGLE +5V TO +15V SUPPLY

LATCH-UP RESISTANT

7521/7541/7541A REPLACEMENT

PACKAGES: Plastic DIP, Plastic SOIC

LOW COST

DESCRIPTION

The Burr-Brown DAC7541A is a low cost 12-bit,
four-quadrant multiplying digital-to-analog converter.
Laser-trimmed thin-film resistors on a monolithic
CMOS circuit provide true 12-bit integral and differ-
ential linearity over the full specified temperature
range.

DAC7541A is a direct, improved pin-for-pin replace-
ment for 7521, 7541, and 7541A industry standard
parts. In addition to a standard 18-pin plastic package,
the DAC7541A is also available in a surface-mount
plastic 18-pin SOIC.

10k

20k

10k

20k

10k

20k

10k

20k

OUT 2

Bit 11

Bit 3

Bit 2

Bit 1

(MSB)

REF

Bit 12
(LSB)

20k

OUT 1

SPDT NMOS

Switches

Digital Inputs (DTL-/TTL-/CMOS-compatible)
Logic: A switch is closed to I

OUT 1

for its digital input in a "HIGH" state.

Switches shown for digital inputs "HIGH".

DAC7541A

International Airport Industrial Park · Mailing Address: PO Box 11400 · Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd. · Tucson, AZ 85706

Tel: (520) 746-1111 · Twx: 910-952-1111 · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132

1987 Burr-Brown Corporation

PDS-639C

Printed in U.S.A. September, 1993

SBAS147

DAC7541A

PARAMETER

GRADE

= +25

= T

MAX

, T

MIN

(1)

UNITS

TEST CONDITIONS/COMMENTS

PROPAGATION DELAY
(from Digital Input change to 90% of

Out

Load = 100

, C

EXT

= 13pF.

final Analog Output)

All

100

ns typ

Digital Inputs = 0V to V

or V

to 0V.

DIGITAL-TO-ANALOG GLITCH

REF

= 0V, all digital inputs 0V to V

or V

IMPULSE

All

1000

nV-s typ

0V. Measured using OPA606 as output amplifier.

MULTIPLYING FEEDTHROUGH
ERROR
(V

REF

to Out

)

All

1.0

mVp-p max

REF

10V, 10kHz sine wave.

OUTPUT CURRENT SETTLING TIME

All

0.6

s typ

To 0.01% of Full Scale Range.
Out

Load = 100

, C

EXT

= 13pF.

All

1.0

s max

Digital Inputs: 0V to V

or V

to 0V.

OUTPUT CAPACITANCE
C

OUT 1

(Pin 1)

All

100

pF max

Digital Inputs = V

OUT 2

(Pin 2)

All

pF max

Digital Inputs = V

OUT 1

(Pin 1)

All

pF max

Digital Inputs = V

OUT 2

(Pin 2)

All

100

pF max

Digital Inputs = V

PARAMETER

GRADE

= +25

= T

MAX

, T

MIN

(1)

UNITS

TEST CONDITIONS/COMMENTS

ACCURACY
Resolution

All

Bits

Relative Accuracy

LSB max

1LSB =

0.024% of FSR.

1/2

LSB max

1/2LSB =

0.012% of FSR.

Differential Non-linearity

LSB max

All grades guaranteed monotonic to 12 bits,

1/2

LSB max

MIN

to T

MAX

Gain Error

LSB max

Measured using internal R

and includes effect

LSB max

of leakage current and gain T.C.
Gain error can be trimmed to zero.

Gain Temperature Coefficient

(

Gain/

Temperature)

ALL

ppm/

C max

Typical value is 2ppm/

Output Leakage Current: Out

(Pin 1)

J, K

nA max

All digital inputs = 0V.

Out

(Pin 2)

J, K

nA max

All digital inputs = V

REFERENCE INPUT
Voltage (Pin 17 to GND)

All

10/+10

V min/max

Input Resistance (Pin 17 to GND)

All

7-18

min/max

Typical input resistance = 11k

Typical input resistance temperature coefficient is
50ppm/

DIGITAL INPUTS
V

(Input HIGH Voltage)

All

2.4

V min

(Input LOW Voltage)

All

0.8

V max

(Input Current)

All

A max

Logic inputs are MOS gates.
I

typ (25

C) = 1nA

(Input Capacitance)

(2)

All

pF max

= 0V

POWER SUPPLY REJECTION

Gain/

All

0.01

0.02

% per % max

= +11.4V to +16V

POWER SUPPLY
V

Range

All

+5 to +16

V min to

Accuracy is not guaranteed over this range.

V max

All

mA max

All digital inputs V

or V

All

100

500

A max

All digital inputs 0V or V

SPECIFICATIONS

ELECTRICAL

At +25

C, +V

= +12V or +15V, V

REF

= +10V, V

PIN 1

= V

PIN 2

= 0V, unless otherwise specified.

NOTES: (1) Temperature ranges are: = 0

C to + 70

C for JP, KP, JU and KU versions. (2) Guaranteed by design but not production tested.

DAC7541A

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for design guidance only and are not production tested.
V

= +15V, V

REF

= +10V except where stated, V

PIN 1

= V

PIN 2

= 0V, output amp is OPA606 except where stated.

DAC7541A

NOTE: (1) Temperature ranges are: = 0

C to + 70

C for JP, KP, JU and KU versions.

DAC7541A

TEMPERATURE

RELATIVE

MODEL

PACKAGE

RANGE

ACCURACY (LSB)

GAIN ERROR (LSB)

DAC7541AJP

Plastic DIP

C to +70

DAC7541AKP

Plastic DIP

C to +70

1/2

DAC7541AJU

Plastic SOIC

C to +70

DAC7541AKU

Plastic SOIC

C to +70

1/2

BURN-IN SCREENING OPTION
See text for details.

ABSOLUTE MAXIMUM RATINGS

(1)

PIN CONNECTIONS

(Pin 16) to Ground ...................................................................... +17V

REF

(Pin 17) to Ground ..................................................................... +25V

RPB

(Pin 18) to Ground .....................................................................

25V

Digital Input Voltage (pins 4-15) to Ground ............................... 0.4V, V

PIN 1

, V

PIN 2

to Ground ............................................................. 0.4V, V

Power Dissipation (any Package):
To +75

C ..................................................................................... 450mW

Derates above +75

C .............................................................. 6mW/

Lead Temperature (soldering, 10s) ................................................ +300

Storage Temperature: Plastic Package ......................................... +125

NOTE: (1) Stresses above those listed above may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

Top View

DIP/SOIC

ELECTROSTATIC
DISCHARGE SENSITIVITY

The DAC7541A is an ESD (electrostatic discharge) sensi-
tive device. The digital control inputs have a special FET
structure, which turns on when the input exceeds the supply
by 18V, to minimize ESD damage. However, permanent
damage may occur on unconnected devices subject to high
energy electrostatic fields. When not in use, devices must be
stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before
devices are removed.

BURN-IN SCREENING

Burn-in screening is an option available for the models in the
Ordering Information table. Burn-in duration is 160 hours at
the indicated temperature (or equivalent combination of time
and temperature).

All units are tested after burn-in to ensure that grade speci-
fications are met. To order burn-in, add "-BI" to the base
model number.

PACKAGE INFORMATION

PACKAGE DRAWING

MODEL

PACKAGE

NUMBER

(1)

DAC7541JP

Plastic DIP

218

DAC7541KP

Plastic DIP

218

DAC7541JU

Plastic SOIC

219

DAC7541KU

Plastic SOIC

219

DAC7541JP-BI

Plastic DIP

218

DAC7541KP-BI

Plastic DIP

218

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix D of Burr-Brown IC Data Book.

DAC7541A

OUT 1

OUT 2

GND

Bit 1 (MSB)

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

REF

Bit 12

(LSB)

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

TEMPERATURE

RELATIVE

BURN-IN TEMP.

MODEL

PACKAGE

RANGE

ACCURACY (LSB)

(160 Hours)

(1)

DAC7541AJP-BI

Plastic DIP

C to +70

+85

DAC7541AKP-BI

Plastic DIP

C to +70

1/2

+85

ORDERING INFORMATION

DAC7541A

TYPICAL PERFORMANCE CURVES

= +25

C, V

= +15V, unless otherwise noted.

MECHANICAL INFORMATION

MILS (0.001")

MILLIMETERS

Die Size

104 x 105

2.64 x 2.67

0.13

Die Thickness

0.51

0.08

Min. Pad Size

4 x 4

0.10 x 0.10

Metalization

Aluminum

PAD

FUNCTION

OUT1

OUT2

GND

Bit 1 (MSB)

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

PAD

FUNCTION

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12 (LSB)

REF

FEEDBACK

Substrate Bias: Isolated.
NC: No Connection.

DIE TOPOLOGY DAC7541A

GAIN ERROR vs SUPPLY VOLTAGE

Gain Error (LSB)

5/2

3/2

1/2

Supply Voltage (V)

0.001

Frequency (Hz)

FEEDTHROUGH ERROR vs FREQUENCY

Feedthrough (% FSR)

10k

100

100k

0.10

0.010

LINEARITY vs SUPPLY VOLTAGE

Linearity Error (LSB)

3/2

5/4

3/4

1/2

1/4

Supply Voltage (V)

SUPPLY CURRENT vs SUPPLY VOLTAGE

Supply Current (µA)

3/2

5/4

3/4

1/2

1/4

Supply Voltage (V)

= +2.4V

= V

DAC7541A

DISCUSSION
OF SPECIFICATIONS

RELATIVE ACCURACY

This term (also known as linearity) describes the transfer
function of analog output to digital input code. The linearity
error describes the deviation from a straight line between
zero and full scale.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the deviation from an ideal 1LSB
change in the output, from one adjacent output state to the
next. A differential nonlinearity specification of

1.0LSB

guarantees monotonicity.

GAIN ERROR

Gain error is the difference in measure of full-scale output
versus the ideal DAC output. The ideal output for the
DAC7541A is (4095/4096)

REF

). Gain error may be

adjusted to zero using external trims.

OUTPUT LEAKAGE CURRENT

The measure of current which appears at Out

with the DAC

loaded with all zeros, or at Out

with the DAC loaded with

all ones.

MULTIPLYING FEEDTHROUGH ERROR

This is the AC error output due to capacitive feedthrough
from V

REF

to Out

with the DAC loaded with all zeros. This

test is performed at 10kHz.

OUTPUT CURRENT SETTLING TIME

This is the time required for the output to settle to a tolerance
of

0.5LSB of final value from a change in code of all zeros

to all ones, or all ones to all zeros.

PROPAGATION DELAY

This is the measure of the delay of the internal circuitry and
is measured as the time from a digital code change to the
point at which the output reaches 90% of final value.

DIGITAL-TO-ANALOG GLITCH IMPULSE

This is the measure of the area of the glitch energy measured
in nV-seconds. Key contributions to glitch energy are digital
word-bit timing differences, internal circuitry timing differ-
ences, and charge injected from digital logic.

MONOTONICITY

Monotonicity assures that the analog output will increase or
stay the same for increasing digital input codes. The
DAC7541A is guaranteed monotonic to 12 bits.

POWER SUPPLY REJECTION

Power supply rejection is the measure of the sensitivity of
the output (full scale) to a change in the power supply
voltage.

FIGURE 1. Simplified DAC Circuit.

EQUIVALENT CIRCUIT ANALYSIS

Figures 2 and 3 show the equivalent circuits for all digital
inputs low and high, respectively. The reference current is
switched to I

OUT 2

when all inputs are low and I

OUT 1

when

inputs are high. The I

current source is the combination of

surface and junction leakages to the substrate; the
1/4096 current source represents the constant one-bit current
drain through the ladder terminal.

DYNAMIC PERFORMANCE
Output Impedance

The output resistance, as in the case of the output capaci-
tance, is also modulated by the digital input code. The
resistance looking back into the I

OUT 1

terminal may be

anywhere between 10k

(the feedback resistor alone when

all digital inputs are low) and 7.5k

(the feedback resistor

in parallel with approximately 30k

of the R-2R ladder

network resistance when any single bit logic is high). The
static accuracy and dynamic performance will be affected by
this modulation. The gain and phase stability of the output

CIRCUIT DESCRIPTION

The DAC7541A is a 12-bit multiplying D/A converter
consisting of a highly stable thin-film R-2R ladder network
and 12 pairs of current steering switches on a monolithic
chip. Most applications require the addition of a voltage or
current reference and an output operational amplifier.

A simplified circuit of the DAC7541A is shown in Figure 1.
The R-2R inverted ladder binarily divides the input currents
that are switched between I

OUT 1

and I

OUT 2

bus lines. This

switching allows a constant current to be maintained in each
ladder leg independent of the input code.

The input resistance at V

REF

(Figure 1) is always equal to

LDR

is the R/2R ladder characteristic resistance and

is equal to value "R"). Since R

at the V

REF

pin is constant,

the reference terminal can be driven by a reference voltage
or a reference current, AC or DC, of positive or negative
polarity.

Bit 12
(LSB)

10k

20k

10k

20k

OUT 2

Bit 3

Bit 2

Bit 1

(MSB)

REF

20k

OUT 1

Digital Inputs (DTL-/TTL-/CMOS-compatible)

Switches shown for digital inputs "HIGH".

DAC7541A

FIGURE 2. DAC7541A Equivalent Circuit (All inputs

LOW).

FIGURE 3. DAC7541A Equivalent Circuit (All inputs

HIGH).

1/4096

90pF

60pF

R = 10k

OUT 1

OUT 2

REF

10k

1/4096

90pF

55pF

R = 10k

OUT 2

OUT 1

10k

REF

amplifier, board layout, and power supply decoupling will
all affect the dynamic performance of the DAC7541A. The
use of a compensation capacitor may be required when high-
speed operational amplifiers are used. It may be connected
across the amplifier's feedback resistor to provide the nec-
essary phase compensation to critically dampen the output.
See Figures 4 and 6.

APPLICATIONS

OP AMP CONSIDERATIONS

The input bias current of the op amp flows through the
feedback resistor, creating an error voltage at the output of
the op amp. This will show up as an offset through all codes
of the transfer characteristics. A low bias current op amp
such as the OPA606 is recommended.

Low offset voltage and V

drift are also important. The

output impedance of the DAC is modulated with the digital
code. This impedance change (approximately 10k

to 30k

)

is a change in closed-loop gain to the op amp. The result is
that V

will be multiplied by a factor of one to two

depending on the code. This shows up as a linearity error.
Offset can be adjusted out using Figure 4. Gain may be
adjusted using Figure 5.

UNIPOLAR BINARY OPERATION
(Two-Quadrant Multiplication)

Figure 4 shows the analog circuit connections required for
unipolar binary (two-quadrant multiplication) operation. With
a DC reference voltage or current (positive or negative
polarity) applied at pin 17, the circuit is a unipolar D/A
converter. With an AC reference voltage or current, the
circuit provides two-quadrant multiplication (digitally con-
trolled attenuation). The input/output relationship is shown
in Table I.

BINARY INPUT

ANALOG OUTPUT

MSB

LSB

1111 1111 1111

REF

(4095/4096)

1000 0000 0000

REF

(2048/4096)

0000 0000 0001

REF

(1/4096)

0000 0000 0000

TABLE I. Unipolar Codes.

phase compensation (10 to 25pF) in Figure 4 may be

required for stability when using high speed amplifiers. C

is used to cancel the pole formed by the DAC internal
feedback resistance and output capacitance at Out

in Figure 5 provides full scale trim capability--load the

DAC register to 1111 1111 1111, adjust R

for V

OUT

REF

(4095/4096). Alternatively, full scale can be adjusted

by omitting R

and R

and trimming the reference voltage

magnitude.

BIPOLAR FOUR-QUADRANT OPERATION

Figure 6 shows the connections for bipolar four-quadrant
operation. Offset can be adjusted with the A

to A

summing

resistor, with the input code set to 1000 0000 0000. Gain
may be adjusted by varying the feedback resistor of A

. The

input/output relationship is shown in Table II.

BINARY INPUT

ANALOG OUTPUT

MSB

LSB

1111 1111 1111

REF

(2047/2048)

1000 0000 0000

0111 1111 1111

REF

(1/2048)

0000 0000 0000

REF

(2048/2048)

TABLE II. Bipolar Codes.

DAC7541A

FIGURE 4. Basic Connection With Op Amp V

Adjust: Unipolar (two-quadrant) Multiplying Configuration.

FIGURE 5. Basic Connection With Gain Adjust (allows adjustment up or down).

FIGURE 6. Bipolar Four-Quadrant Multiplier.

DAC7541A

Out

REF

OUT

OPA604

+15V

Out

10k

OUT

= V

REF

+ + + · · · +

(

4096

)

10V

REF

+10V

4095

4096

OUT

REF

Where: B

= 1 if the B

digital input is HIGH.

= 0 if the B

digital input is LOW.

MSB

Single-Point Ground

DAC7541A

REF

OPA604

+15V

10k

MSB

200

200k

OPA604

1/2 OPA2604

REF

DAC7541A

Bits 1-12

33pF

4...15

OUT

10k

20k

OPA604

1/2 OPA2604

OUT

= +V

REF

+ + + · · · + 1

(

2048

)

PACKAGING INFORMATION

ORDERABLE DEVICE

STATUS(1)

PACKAGE TYPE

PACKAGE DRAWING

PINS

PACKAGE QTY

DAC7541AJP

ACTIVE

PDIP

DAC7541AJU

ACTIVE

SOP

DTC

DAC7541AKP

ACTIVE

PDIP

DAC7541AKU

ACTIVE

SOP

DTC

DAC7541AKU/1K

ACTIVE

SOP

DTC

1000

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

www.ti.com

3-Oct-2003

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