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PRODUCT PREVIEW
FEATURES
DESCRIPTION
APPLICATIONS
_
+
Interface
Logic
Shift
Register
DAC
Register
String
DAC
Power-Down
Logic
Power-On
Reset
V
DD
IOV
DD
V
REF
H
V
FB
V
OUT
V
REF
L
GND
CLR
SDO
SDIN
SYNC
SCLK
DAC7551
SLAS441 MARCH 2005
12-BIT, ULTRALOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
2.7-V to 5.5-V Single Supply
The DAC7551 is a single-channel, voltage-output
DAC with exceptional linearity and monotonicity. Its
12-Bit Linearity and Monotonicity
proprietary architecture minimizes glitch energy. The
Rail-to-Rail Voltage Output
low-power DAC7551 operates from a single 2.7-V to
Settling Time: 5 s (Max)
5.5-V supply. The DAC7551 output amplifiers can
Ultralow Glitch Energy: 0.1 nVs
drive a 2-k
, 200-pF load rail-to-rail with 5-s settling
time; the output range is set using an external voltage
Low Power: 200 A (Max)
reference.
Power Down: 2 A (Max)
The 3-wire serial interface operates at clock rates up
Power-On Reset to Zero Scale
to 50 MHz and is compatible with SPI, QSPI,
SPI-Compatible Serial Interface: Up to 50 MHz
MicrowireTM, and DSP interface standards. The parts
Daisy-Chain Capability
incorporate a power-on-reset circuit to ensure that the
DAC outputs power up to zero volts and remain there
Asynchronous Hardware Clear
until a valid write cycle to the device takes place. The
Specified Temperature Range: 40C to 105C
parts contain a power-down feature that reduces the
Small, 2-mm x 3-mm, 12-Lead SON Package
current consumption of the device to under 2 A.
The small size and low-power operation makes the
DAC7551 ideally suited for battery-operated portable
Portable Battery-Powered Instruments
applications. The power consumption is typically
Digital Gain and Offset Adjustment
0.5 mW at 5 V, 0.23 mW at 3 V, and reduces to 1 W
in power-down mode.
Programmable Voltage and Current Sources
Programmable Attenuators
The DAC7551 is available in a 12-lead SON package
and is specified over 40C to 105C.
Industrial Process Control
FUNCTIONAL BLOCK DIAGRAM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Microwire is a trademark of National Semiconductor Corp..
PRODUCT PREVIEW information concerns products in the forma-
Copyright 2005, Texas Instruments Incorporated
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
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PRODUCT PREVIEW
ABSOLUTE MAXIMUM RATINGS
DAC7551
SLAS441 MARCH 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIED
PACKAGE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
TEMPERATURE
DESIGNATOR
MARKING
NUMBER
MEDIA
RANGE
DAC7551IDRNT
250-piece Tape and Reel
DAC7551
12 SON
DRN
40C TO 105C
D51
DAC7551IDRNR
2500-piece Tape and Reel
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at
www.ti.com
.
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
DD
to GND
0.3 V to 6 V
Digital input voltage to GND
0.3 V to V
DD
+ 0.3 V
V
OUT
to GND
0.3 V to V
DD
+ 0.3 V
Operating temperature range
40C to 105C
Storage temperature range
65C to 150C
Junction temperature (T
J
Max)
150C
(1)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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PRODUCT PREVIEW
ELECTRICAL CHARACTERISTICS
DAC7551
SLAS441 MARCH 2005
V
DD
= 2.7 V to 5.5 V, V
REF
H = V
DD
, V
REF
L = GND, R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications 40C to 105C,
unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
(1)
Resolution
12
Bits
Relative accuracy
0.35
1
LSB
Differential nonlinearity
Specified monotonic by design
0.08
0.5
LSB
Offset error
12
mV
Zero-scale error
All zeroes loaded to DAC register
12
mV
Gain error
0.15
%FSR
Full-scale error
0.5
%FSR
Zero-scale error drift
7
V/C
Gain temperature coefficient
3
ppm of FSR/C
PSRR
V
DD
= 5 V
0.75
mV/V
OUTPUT CHARACTERISTICS
(2)
Output voltage range
2 x V
REF
L
V
REF
H
V
Output voltage settling time
R
L
= 2 k
; 0 pF < C
L
< 200 pF
5
s
Slew rate
1
V/s
Capacitive load stability
R
L
=
470
pF
R
L
= 2 k
1000
Digital-to-analog glitch impulse
1 LSB change around major carry
0.1
nV-s
Digital feedthrough
0.1
nV-s
Output noise density (10-kHz offset
70
nV/rtHz
frequency)
Total harmonic distortion
F
OUT
= 1 kHz, F
S
= 1 MSPS, BW = 20 kHz
85
dB
DC output impedance
1
Short-circuit current
V
DD
= 5 V
50
mA
V
DD
= 3 V
20
Power-up time
Coming out of power-down mode, V
DD
= 5 V
15
s
Coming out of power-down mode, V
DD
= 3 V
15
REFERENCE INPUT
V
REF
H, Input range
0
V
DD
V
V
REF
L, Input range
V
REF
L < V
REF
H
0
GND
V
DD
V
Reference input impedance
100
k
Reference current
V
REF
= V
DD
= 5 V
130
250
A
V
REF
= V
DD
= 3 V
65
123
LOGIC INPUTS
(2)
Input current
1
A
V
IN_L
, Input low voltage
V
DD
= 5 V
0.3 V
DD
V
V
IN_H
, Input high voltage
V
DD
= 3 V
0.7 V
DD
V
Pin capacitance
3
pF
(1)
Linearity tested using a reduced code range of 30 to 4065; output unloaded.
(2)
Specified by design and characterization, not production tested.
3
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PRODUCT PREVIEW
ELECTRICAL CHARACTERISTICS (Continued)
DAC7551
SLAS441 MARCH 2005
V
DD
= 2.7 V to 5.5 V, V
REF
H = V
DD
, V
REF
L = GND, R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications 40C to 105C,
unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER REQUIREMENTS
V
DD
2.7
5.5
V
I
DD
(normal operation)
DAC active and excluding load current
V
DD
= 3.6 V to 5.5 V
150
200
A
V
IH
= V
DD
and V
IL
= GND
V
DD
= 2.7 V to 3.6 V
100
150
I
DD
(all power-down modes)
V
DD
= 3.6 V to 5.5 V
V
IH
= V
DD
and V
IL
= GND
0.2
2
A
V
DD
= 2.7 V to 3.6 V
0.05
2
Reference input impedance
100
k
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2 mA, V
DD
= 5 V
93%
4
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PRODUCT PREVIEW
TIMING CHARACTERISTICS
(1) (2)
SCLK
SYNC
SDIN
D15
D14
D13
D12
D11
D1
D0
D15
t
8
t
4
t
3
t
2
t
1
t
7
t
6
t
5
D0
t
9
Input Word n
Input Word n+1
Undefined
D15
D14
D0
Input Word n
t
10
SDO
CLR
DAC7551
SLAS441 MARCH 2005
V
DD
= 2.7 V to 5.5 V, R
L
= 2 k
to GND; all specifications 40C to 105C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
= 2.7 V to 3.6 V
20
t
1
(3)
SCLK cycle time
ns
V
DD
= 3.6 V to 5.5 V
20
V
DD
= 2.7 V to 3.6 V
10
t
2
SCLK HIGH time
ns
V
DD
= 3.6 V to 5.5 V
10
V
DD
= 2.7 V to 3.6 V
10
t
3
SCLK LOW time
ns
V
DD
= 3.6 V to 5.5 V
10
V
DD
= 2.7 V to 3.6 V
4
SYNC falling edge to SCLK falling edge setup
t
4
ns
time
V
DD
= 3.6 V to 5.5 V
4
V
DD
= 2.7 V to 3.6 V
5
t
5
Data setup time
ns
V
DD
= 3.6 V to 5.5 V
5
V
DD
= 2.7 V to 3.6 V
4.5
t
6
Data hold time
ns
V
DD
= 3.6 V to 5.5 V
4.5
V
DD
= 2.7 V to 3.6 V
0
t
7
SCLK falling edge to SYNC rising edge
ns
V
DD
= 3.6 V to 5.5 V
0
V
DD
= 2.7 V to 3.6 V
20
t
8
Minimum SYNC HIGH time
ns
V
DD
= 3.6 V to 5.5 V
20
V
DD
= 2.7 V to 3.6 V
TBD
t
9
SCLK falling edge to SDO valid
ns
V
DD
= 3.6 V to 5.5 V
TBD
V
DD
= 2.7 V to 3.6 V
TBD
t
10
CLR pulse width low
ns
V
DD
= 3.6 V to 5.5 V
TBD
(1)
All input signals are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2)
See Serial Write Operation timing diagram
Figure 1
.
(3)
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
Figure 1. Serial Write Operation
5
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PRODUCT PREVIEW
PIN DESCRIPTION
12
11
10
9
8
7
1
2
3
4
5
6
VDD
VREFH
VREFL
VFB
VOUT
GND
CLR
SYNC
SCLK
SDIN
SDO
IOVDD
DRN PACKAGE
(TOP VIEW)
DAC7551
SLAS441 MARCH 2005
Terminal Functions
TERMINAL
DESCRIPTION
NO.
NAME
1
VDD
Analog voltage supply input
2
VREFH
Positive reference voltage input
3
VREFL
Negative reference voltage input
4
VFB
DAC amplifier sense input.
5
VOUT
Analog output voltage from DAC
6
GND
Ground
7
CLR
Asynchronous input to clear the DAC registers. When CLR is low, the DAC register is set to 000H and the output
voltage to 0 V.
8
SYNC
Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out
to the DAC7551.
9
SCLK
Serial clock input
10
SDIN
Serial data input
11
SDO
Serial data output
12
IOVDD
I/O voltage supply input
6
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PRODUCT PREVIEW
TYPICAL CHARACTERISTICS
Linearity Error - LSB
Digital Input Code
Differential Linearity Error - LSB
-1
-0.5
0
0.5
1
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
V
REF
H = 4.096 V
V
DD
= 5 V
V
REF
L = GND
Linearity Error - LSB
Digital Input Code
Differential Linearity Error - LSB
-1
-0.5
0
0.5
1
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
V
DD
= 2.7 V
V
REF
L = GND
V
REF
H = 2.5 V
0
0.25
0.5
0.75
1
-40
-10
20
50
80
V
DD
= 5 V,
V
REF
H= 4.096 V,
V
REF
L= GND
T
A
- Free-Air Temperature -
C
Zero-Scale Error - mV
0
0.25
0.5
0.75
1
-40
-10
20
50
80
V
DD
= 2.7 V,
V
REF
H = 2.5 V,
V
REF
L = GND
T
A
- Free-Air Temperature -
C
Zero-Scale Error - mV
DAC7551
SLAS441 MARCH 2005
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 2.
Figure 3.
ZERO-SCALE ERROR
ZERO-SCALE ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 4.
Figure 5.
7
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PRODUCT PREVIEW
-1
-0.75
-0.5
-0.25
0
-40
-10
20
50
80
T
A
- Free-Air Temperature -
C
Full-Scale Error - mV
V
DD
= 5 V,
V
REF
H= 4.096 V,
V
REF
L= GND
-1
-0.75
-0.5
-0.25
0
-40
-10
20
50
80
T
A
- Free-Air Temperature -
C
Full-Scale Error - mV
V
DD
= 2.7 V,
V
REF
H= 2.5 V,
V
REF
L= GND
0
0.05
0.1
0.15
0.2
0
5
10
15
Typical
V
DD
= 2.7 V,
V
REF
H = 2.5 V,
V
REF
L = GND
V
DD
= 5.5 V,
V
REF
H = 4.096 V,
V
REF
L = GND
- Output V
oltage - V
V
O
I
SINK
- Sink Current - mA
DAC Loaded with 000h
5.20
5.30
5.40
5.50
0
5
10
15
V
DD
= V
REF
H = 5.5 V,
V
REF
L = GND
- Output V
oltage - V
V
O
I
SOURCE
- Source Current - mA
DAC Loaded with FFFh
DAC7551
SLAS441 MARCH 2005
TYPICAL CHARACTERISTICS (continued)
FULL-SCALE ERROR
FULL-SCALE ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 6.
Figure 7.
SINK CURRENT AT NEGATIVE RAIL
SOURCE CURRENT AT POSITIVE RAIL
Figure 8.
Figure 9.
8
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PRODUCT PREVIEW
0
50
100
150
200
250
0
512
1024 1536 2048 2560 3072 3584 4096
Digital Input Code
DDI
Supply Current -
-
A
V
DD
= 5.5 V,
V
REF
H= 4.096 V,
V
REF
L= GND
V
DD
= 2.7 V,
V
REF
H= 2.5 V,
V
REF
L= GND
Powered, No Load
2.4
2.5
2.6
2.7
0
5
10
15
V
DD
= V
REF
H = 2.7 V,
V
REF
L = GND
- Output V
oltage - V
V
O
I
SOURCE
- Source Current - mA
DAC Loaded with FFFh
100
150
200
-40
-10
20
50
80
110
DDI
Supply Current -
-
A
T
A
- Free-Air Temperature -
C
V
DD
= 5.5 V,
V
REF
H= 4.096 V,
V
REF
L= GND
V
DD
= 2.7 V,
V
REF
H= 2.5 V,
V
REF
L= GND
Powered, No Load
75
88
100
113
125
2.7
3.1
3.4
3.8
4.1
4.5
4.8
5.2
5.5
DDI
Supply Current -
-
A
V
DD
- Supply Voltage - V
DAC Powered, No Load,
V
REF
H= 2.5 V,
V
REF
L= GND
DAC7551
SLAS441 MARCH 2005
TYPICAL CHARACTERISTICS (continued)
SOURCE CURRENT AT POSITIVE RAIL
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
Figure 10.
Figure 11.
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
Figure 12.
Figure 13.
9
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PRODUCT PREVIEW
0
400
800
1200
1600
0
1
2
3
4
5
V
LOGIC
- Logic Input Voltage - V
DDI
Supply Current -
-
A
T
A
= 25
5
C,
SCLK Input (All Other Inputs = GND)
V
DD
= 5.5 V,
V
REF
H= 4.096 V,
V
REF
L=GND
V
DD
= 2.7 V,
V
REF
H= 2.5 V
V
REF
L= GND
0
500
1000
1500
2000
128
136
144
152
160 168
176
184
192
f - Frequency - Hz
I
DD
- Current Consumption -
m
A
V
DD
= 5.5 V,
V
REF
H= 4.096 V,
V
REF
L=GND
0
500
1000
1500
2000
117
124
131
138
145
152
159
166
173
f - Frequency - Hz
I
DD
- Current Consumption -
m
A
V
DD
= 2.7 V,
V
REF
H= 2.5 V,
V
REF
L= GND
Digital Input Code
T
otal Error - mV
V
DD
= 5 V,
V
REF
H= 4.096 V,
V
REF
L= GND,
T
A
= 25
5
C
-4
-2
0
2
4
0
512
1024 1536 2048 2560 3072 3584 4095
DAC7551
SLAS441 MARCH 2005
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V
vs
LOGIC INPUT VOLTAGE
Figure 14.
Figure 15.
HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V
TOTAL ERROR - 5 V
Figure 16.
Figure 17.
10
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PRODUCT PREVIEW
-4
-2
0
2
4
0
512
1024 1536 2048 2560 3072 3584 4095
Digital Input Code
T
otal Error - mV
V
DD
= 2.7 V,
V
REF
H= 2.5 V,
V
REF
L= GND,
T
A
= 25
5
C
0
1
2
3
4
5
- Output V
oltage - V
V
O
t - Time - 4
m
s/div
V
DD
= 5 V,
V
REF
H = 4.096 V, V
REF
L = GND
Power-Up Code 4000
0
1
2
3
4
5
V
DD
= 5 V,
Output Loaded With 200 pF to GND
Code 41 to 4055
- Output V
oltage - V
V
O
t - Time - 5
m
s/div
V
REF
H = 4.096 V, V
REF
L = GND,
0
1
2
3
V
DD
= 2.7 V,
Output Loaded With 200 pF to GND
Code 41 to 4055
- Output V
oltage - V
V
O
t - Time - 5
m
s/div
V
REF
H = 2.5 V, V
REF
L = GND
DAC7551
SLAS441 MARCH 2005
TYPICAL CHARACTERISTICS (continued)
TOTAL ERROR - 2.7 V
EXITING POWER-DOWN MODE
Figure 18.
Figure 19.
LARGE-SIGNAL SETTLING TIME - 5 V
LARGE-SIGNAL SETTLING TIME - 2.7 V
Figure 20.
Figure 21.
11
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PRODUCT PREVIEW
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
Trigger Pulse
V
O
(5 mV/Div)
-
Time - (400 nS/Div)
-100
-90
-80
-70
-60
-50
-40
0
1
2
3
4
5
6
7
8
9
10
V
DD
= 5 V, V
REF
H = 4.096 V, V
REF
L = GND
-1-dB FSR Digital Input, Fs = 1 Msps
Measurement Bandwidth = 20 kHz
2nd Harmonic
3rd Harmonic
THD - T
otal Harmonic Distortion - dB
Output Frequency (Tone) - kHz
THD
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
DAC7551
SLAS441 MARCH 2005
TYPICAL CHARACTERISTICS (continued)
MIDSCALE GLITCH
WORST-CASE GLITCH
Figure 22.
Figure 23.
DIGITAL FEEDTHROUGH ERROR
TOTAL HARMONIC DISTORTION
vs
OUTPUT FREQUENCY
Figure 24.
Figure 25.
12
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PRODUCT PREVIEW
3-Wire Serial Interface
DAC7551
SLAS441 MARCH 2005
TYPICAL CHARACTERISTICS (continued)
The DAC7551 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface.
Table 1. Serial Interface Programming
CONTROL
DATA BITS
FUNCTION
DB15
DB14
DB13
DB12
DB11DB0
(PD1)
(PD0)
X
X
0
0
data
Normal mode
X
X
0
1
X
Powerdown 1 k
X
X
1
0
X
Powerdown 100 k
X
X
1
1
X
Powerdown Hi-Z
13
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PRODUCT PREVIEW
THEORY OF OPERATION
DAC External Reference Input
D/A SECTION
Power-On Reset
_
+
Resistor String
Ref +
Ref -
DAC Register
V
OUT
V
REF
H
V
REF
L
V
FB
Power Down
Asynchronous Clear
V
REF
H
To Output
Amplifier
R
R
R
R
V
REF
L
RESISTOR STRING
SERIAL INTERFACE
OUTPUT BUFFER AMPLIFIERS
16-Bit Word and Input Shift Register
DAC7551
SLAS441 MARCH 2005
There is a single reference input pin for the DAC. The
The architecture of the DAC7551 consists of a string
reference input is unbuffered. The user can have a
DAC followed by an output buffer amplifier.
Figure 26
reference voltage as low as 0.25 V and as high as
shows a generalized block diagram of the DAC
V
DD
because there is no restriction due to headroom
architecture.
and footroom of any reference amplifier.
It is recommended to use a buffered reference in the
external circuit (e.g., REF3140). The input impedance
is typically 100 k
.
On power up, the internal register is cleared and the
DAC channel is updated with zero-scale voltage. The
Figure 26. Typical DAC Architecture
DAC output remains in this state until valid data is
written. This is particularly useful in applications
The input coding to the DAC7551 is unsigned binary,
where it is important to know the state of the DAC
which gives the ideal output voltage as:
output while the device is powering up. In order not to
V
OUT
= 2 x V
REF
L + (V
REF
H V
REF
L) x D/4096
turn on ESD protection devices, V
DD
should be
applied before any other pin is brought high.
Where D = decimal equivalent of the binary code that
is loaded to the DAC register which can range from 0
to 4095.
The DAC7551 has a flexible power-down capability.
During a power-down condition, the user has flexi-
bility to select the output impedance of the DAC.
During power-down operation, the DAC can have
either 1-k
, 100-k
, or Hi-Z output impedance to
ground.
Figure 27. Typical Resistor String
The DAC7551 output is asynchronously set to
zero-scale voltage immediately after the CLR pin is
brought low. The CLR signal resets all internal
registers and therefore behaves like the Power-On
Reset. The DAC7551 updates at the first rising edge
The resistor string section is shown in
Figure 27
. It is
of the SYNC signal that occurs after the CLR pin is
simply a string of resistors, each of value R. The
brought back to high.
digital code loaded to the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier. The voltage is tapped
off by closing one of the switches connecting the
The DAC7551 is controlled over a versatile 3-wire
string to the amplifier. Because it is a string of
serial interface, which operates at clock rates up to
resistors, it is specified monotonic.
50 MHz and is compatible with SPI, QSPI, Microwire,
and DSP interface standards.
In order to initialize the serial interface for the next
The output buffer amplifier is capable of generating
update, the DAC7551 requires a falling SCLK edge
rail-to-rail voltages on its output, which gives an
after the rising SYNC.
output range of 0 V to V
DD
. It is capable of driving a
load of 2 k
in parallel with up to 1000 pF to GND.
The source and sink capabilities of the output ampli-
The input shift register is 16 bits wide. DAC data is
fier can be seen in the typical curves. The slew rate is
loaded into the device as a 16-bit word under the
1 V/s with a half-scale settling time of 3 s with the
control of a serial clock input, SCLK, as shown in the
output unloaded.
Figure 1
timing diagram. The 16-bit word, illustrated
in
Table 1
, consists of four control bits followed by 12
bits of DAC data. The data format is straight binary
14
www.ti.com
PRODUCT PREVIEW
GLITCH ENERGY
APPLICATION INFORMATION
Waveform Generation
Daisy-Chain Operation
Generating 5-V, 10-V, and 12-V Outputs For
INTEGRAL AND DIFFERENTIAL LINEARITY
DAC7551
SLAS441 MARCH 2005
with all zeroes corresponding to 0-V output and all
ones corresponding to full-scale output (V
REF
1
The DAC7551 uses a proprietary architecture that
LSB). Data is loaded MSB first (Bit 15) where the first
minimizes glitch energy. The code-to-code glitches
two bits (DB15 and DB14) are don't care bits. Bit 13
are so low, they are usually buried within the
and bit 12 (DB13 and DB12) determine either normal
wide-band noise and cannot be easily detected. The
mode operation or power-down mode (see
Table 1
).
DAC7551 glitch is typically well under 0.1 nV-s. Such
The SYNC input is a level-triggered input that acts as
low glitch energy provides more than 10X improve-
a frame synchronization signal and chip enable. Data
ment over industry alternatives.
can only be transferred into the device while SYNC is
low. To start the serial data transfer, SYNC should be
taken low, observing the minimum SYNC to SCLK
falling edge setup time, t
4
. After SYNC goes low,
serial data is shifted into the device's input shift
Due to its exceptional linearity and low glitch, the
register on the falling edges of SCLK for 16 clock
DAC7551 is well suited for waveform generation
pulses.
(from DC to 10 kHz). The DAC7551 large-signal
The SPI interface is enabled after SYNC becomes
settling time is 5 s, supporting an update rate of 200
low and the data is continuously shifted into the shift
KSPS. However, the update rates can exceed 1
register at each falling edge of SCLK. When SYNC is
MSPS if the waveform to be generated consists of
brought high the last 16 bits stored in the shift
small voltage steps between consecutive DAC up-
register get latched into the DAC register, and the
dates. To obtain a high dynamic range, REF3140
DAC updates.
(4.096 V) or REF02 (5.0 V) are recommended for
reference voltage generation.
Serial
Data
Output
(SDO)
pin
is
provided
to
Precision Industrial Control
daisy-chain multiple DAC7551 devices in a system.
Industrial control applications can require multiple
As long as SYNC is high the SDO pin is in a
feedback loops consisting of sensors, ADCs, MCUs,
high-impedance state. When SYNC is brought low
DACs, and actuators. Loop accuracy and loop speed
the output of the internal shift register is tied to the
are the two important parameters of such control
SDO pin. As long as SYNC is low, at each falling
loops.
edge of SCLK, SDO duplicates SDIN signal with a
16-cycle delay. To support multiple devices in a daisy
Loop Accuracy:
chain, SCLK and SYNC signals are shared across all
In a control loop, the ADC has to be accurate. Offset,
devices, and SDO of one DAC7551 should be tied to
gain, and the integral linearity errors of the DAC are
the SDIN of the next DAC7551. For n devices in such
not factors in determining the accuracy of the loop.
a daisy chain, 16n SCLK cycles are required to shift
As long as a voltage exists in the transfer curve of a
the entire input data stream. After 16n SCLK falling
monotonic DAC, the loop can find it and settle to it.
edges are received following a falling SYNC, the data
On the other hand, DAC resolution and differential
stream becomes complete, and SYNC can be
linearity do determine the loop accuracy, because
brought high to update n devices simultaneously.
each DAC step determines the minimum incremental
SDO operation is specified at a maximum SCLK
change the loop can generate. A DNL error less than
speed of 10 MHz.
1 LSB (non-monotonicity) can create loop instability.
A DNL error greater than +1 LSB implies unnecess-
arily large voltage steps and missed voltage targets.
The DAC7551 uses precision thin-film resistors pro-
With high DNL errors, the loop loses its stability,
viding exceptional linearity and monotonicity. Integral
resolution, and accuracy. Offering 12-bit ensured
linearity error is typically within (+/-) 0.35 LSBs, and
monotonicity and 0.08 LSB typical DNL error, 755X
differential linearity error is typically within (+/-) 0.08
DACs are great choices for precision control loops.
LSBs.
Loop Speed:
Many factors determine control loop speed. Typically,
the ADC's conversion time, and the MCU's compu-
tation time are the two major factors that dominate
the time constant of the loop. DAC settling time is
rarely a dominant factor because ADC conversion
times usually exceed DAC conversion times. DAC
offset, gain, and linearity errors can slow the loop
15
www.ti.com
PRODUCT PREVIEW
V
out
+
V
REF
R2
R1
)
1
Din
4096
*
V
tail
R2
R1
(1)
DAC7551
V
REF
H
DAC7551
_
+
V
dac
R2
R1
REF3140
V
REF
V
tail
V
OUT
OPA4130
DAC7551
SLAS441 MARCH 2005
down only during the start-up. Once the loop reaches
its steady-state operation, these errors do not affect
loop speed any further. Depending on the ringing
Fixed R1 and R2 resistors can be used to coarsely
characteristics of the loop's transfer function, DAC
set the gain required in the first term of the equation.
glitches can also slow the loop down. With its 1
Once R2 and R1 set the gain to include some
MSPS (small-signal) maximum data update rate,
minimal over-range, a single DAC7551 could be used
DAC7551 can support high-speed control loops.
to set the required offset voltages. Residual errors
Ultralow glitch energy of the DAC7551 significantly
are not an issue for loop accuracy because offset and
improves loop stability and loop settling time.
gain errors could be tolerated. One DAC7551 can
Generating Industrial Voltage Ranges:
provide the V
tail
voltages, while four additional
DAC7551 devices can provide V
dac
voltages to gener-
For control loop applications, DAC gain and offset
ate four high-voltage outputs. A single SPI interface is
errors are not important parameters. This could be
sufficient to control all five DAC7551 devices in a
exploited to lower trim and calibration costs in a
daisy-chain configuration.
high-voltage control circuit design. Using a quad
operational amplifier (OPA4130), and a voltage refer-
For 5-V operation: R1 = 10 k
, R2 = 15 k
, V
tail
=
ence (REF3140), the DAC7551 can generate the
3.33 V, V
REF
= 4.096 V
wide voltage swings required by the control loop.
For 10-V operation: R1 = 10 k
, R2 = 39 k
, V
tail
=
2.56 V, V
REF
= 4.096 V
For 12-V operation: R1 = 10 k
, R2 = 49 k
, V
tail
=
2.45 V, V
REF
= 4.096 V
Figure 28. Low-cost, Wide-swing Voltage Gener-
ator for Control Loop Applications
The output voltage of the configuration is given by:
16
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
DAC7551IDRNR
PREVIEW
SON
DRN
12
250
TBD
Call TI
Call TI
DAC7551IDRNT
PREVIEW
SON
DRN
12
250
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Addendum-Page 1
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