3 mm x 3 mm
Actual Size
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PRODUCT PREVIEW
FEATURES
DESCRIPTION
APPLICATIONS
_
+
Interface
Logic
Input
Register
DAC
Register
String
DAC A
Power-Down
Logic
Power-On
Reset
V
DD
IOV
DD
V
REFA
V
FBA
V
OUT
A
V
REFB
GND
CLR
DCEN
SDIN
SYNC
SCLK
_
+
Input
Register
DAC
Register
String
DAC B
V
FBB
V
OUT
B
PD
SDO
FUNCTIONAL BLOCK DIAGRAM
DAC7553
DAC7553
SLAS477 AUGUST 2005
12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
2.7-V to 5.5-V Single Supply
The
DAC7553
is
a
12-bit,
dual-channel,
volt-
age-output
DAC
with
exceptional
linearity
and
12-Bit Linearity and Monotonicity
monotonicity. Its proprietary architecture minimizes
Rail-to-Rail Voltage Output
undesired transients such as code-to-code glitch and
Settling Time: 5 s (Max)
channel-to-channel
crosstalk.
The
low-power
Ultralow Glitch Energy: 0.1 nVs
DAC7553 operates from a single 2.7-V to 5.5-V
supply. The DAC7553 output amplifiers can drive a
Ultralow Crosstalk: 100 dB
2-k
, 200-pF load rail-to-rail with 5-s settling time;
Low Power: 440 A (Max)
the output range is set using an external voltage
Per-Channel Power Down: 2 A (Max)
reference.
Power-On Reset to Midscale
The 3-wire serial interface operates at clock rates up
2s Complement Input Data Format
to 50 MHz and is compatible with SPI, QSPI,
MicrowireTM, and DSP interface standards. The out-
SPI-Compatible Serial Interface: Up to 50 MHz
puts of all DACs may be updated simultaneously or
Daisy-Chain Capability
sequentially. The parts incorporate a power-on-reset
Asynchronous Hardware Clear
circuit to ensure that the DAC outputs power up at
midscale and remain there until a valid write cycle to
Simultaneous or Sequential Update
the
device
takes
place.
The
parts
contain
a
Specified Temperature Range: 40C to 105C
power-down feature that reduces the current con-
Small 3-mm 3-mm, 16-Lead QFN Package
sumption of the device to under 2 A.
The small size and low-power operation makes the
DAC7553 ideally suited for battery-operated portable
Portable Battery-Powered Instruments
applications. The power consumption is typically
Digital Gain and Offset Adjustment
1.5 mW at 5 V, 0.75 mW at 3 V, and reduces to 1 W
in power-down mode.
Programmable Voltage and Current Sources
Programmable Attenuators
The DAC7553 is available in a 16-lead QFN package
and is specified over 40C to 105C.
Industrial Process Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Microwire is a trademark of National Semiconductor Corp..
PRODUCT PREVIEW information concerns products in the forma-
Copyright 2005, Texas Instruments Incorporated
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
www.ti.com
PRODUCT PREVIEW
ABSOLUTE MAXIMUM RATINGS
DAC7553
SLAS477 AUGUST 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIED
PACKAGE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
TEMPERATURE
DESIGNATOR
MARKING
NUMBER
MEDIA
RANGE
DAC7553IRGTT
250-piece Tape and Reel
DAC7553
16 QFN
RGT
40C TO 105C
D753
DAC7553IRGTR
2500-piece Tape and Reel
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at
www.ti.com
.
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
DD
to GND
0.3 V to 6 V
Digital input voltage to GND
0.3 V to V
DD
+ 0.3 V
V
out
to GND
0.3 V to V
DD
+ 0.3 V
Operating temperature range
40C to 105C
Storage temperature range
65C to 150C
Junction temperature (T
J
Max)
150C
(1)
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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PRODUCT PREVIEW
ELECTRICAL CHARACTERISTICS
DAC7553
SLAS477 AUGUST 2005
V
DD
= 2.7 V to 5.5 V, V
REF
= V
DD
, R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications 40C to 105C, unless otherwise
specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
(1)
Resolution
12
Bits
Relative accuracy
0.35
1
LSB
Differential nonlinearity
Specified monotonic by design
0.08
0.5
LSB
Offset error
12
mV
Zero-scale error
All zeroes loaded to DAC register
12
mV
Gain error
0.15
%FSR
Full-scale error
0.5
%FSR
Zero-scale error drift
7
V/C
Gain temperature coefficient
3
ppm of FSR/C
PSRR
V
DD
= 5 V
0.75
mV/V
OUTPUT CHARACTERISTICS
(2)
Output voltage range
0
VREF
V
Output voltage settling time
R
L
= 2 k
; 0 pF < C
L
< 200 pF
5
s
Slew rate
1.8
V/s
Capacitive load stability
R
L
=
470
pF
R
L
= 2 k
1000
Digital-to-analog glitch impulse
1 LSB change around major carry
0.1
nV-s
Channel-to-channel crosstalk
1-kHz full-scale sine wave,
100
dB
outputs unloaded
Digital feedthrough
0.1
nV-s
Output noise density (10-kHz offset fre-
120
nV/rtHz
quency)
Total harmonic distortion
F
OUT
= 1 kHz, F
S
= 1 MSPS,
85
dB
BW = 20 kHz
DC output impedance
1
Short-circuit current
V
DD
= 5 V
50
mA
V
DD
= 3 V
20
Power-up time
Coming out of power-down mode,
15
V
DD
= 5 V
s
Coming out of power-down mode,
15
V
DD
= 3 V
REFERENCE INPUT
VREF Input range
0
V
DD
V
Reference input impedance
V
REF
A and V
REF
B shorted together
50
k
V
REF
A = V
REF
B = V
DD
= 5 V,
100
250
V
REF
A and V
REF
B shorted together
Reference current
A
V
REF
A = V
REF
B = V
DD
= 3 V,
60
123
V
REF
A and V
REF
B shorted together
LOGIC INPUTS
(2)
Input current
1
A
V
IN_L
, Input low voltage
IOV
DD
2.7 V
0.3 IOV
DD
V
V
IN_H
, Input high voltage
IOV
DD
2.7 V
0.7 IOV
DD
V
Pin capacitance
3
pF
(1)
Linearity tested using a reduced code range of 30 to 4065; output unloaded.
(2)
Specified by design and characterization, not production tested. For 1.8 V < IOV
DD
< 2.7 V, It is recommended that
V
IH
= IOV
DD
, V
IL
= GND.
3
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PRODUCT PREVIEW
DAC7553
SLAS477 AUGUST 2005
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 2.7 V to 5.5 V, V
REF
= V
DD
, R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications 40C to 105C, unless otherwise
specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
V
DD,
, IOV
DD
(3)
2.7
5.5
V
I
DD
(normal operation)
DAC active and excluding load current
V
DD
= 3.6 V to 5.5 V
300
440
V
IH
= IOV
DD
and V
IL
= GND
A
V
DD
= 2.7 V to 3.6 V
250
400
I
DD
(all power-down modes)
V
DD
= 3.6 V to 5.5 V
0.2
2
V
IH
= IOV
DD
and V
IL
= GND
A
V
DD
= 2.7 V to 3.6 V
0.05
2
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2 mA, V
DD
= 5 V
93%
(3)
IOV
DD
operates down to 1.8 V with slightly degraded timing, as long as V
IH
= IOV
DD
and V
IL
= GND.
4
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PRODUCT PREVIEW
TIMING CHARACTERISTICS
(1) (2)
SCLK
SYNC
SDIN
D15
D14
D13
D12
D11
D1
D0
D15
t
8
t
4
t
3
t
2
t
1
t
7
t
6
t
5
D0
t
9
Input Word n
Input Word n+1
Undefined
D15
D14
D0
Input Word n
t
10
SDO
CLR
DAC7553
SLAS477 AUGUST 2005
V
DD
= 2.7 V to 5.5 V, R
L
= 2 k
to GND; all specifications 40C to 105C, unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
= 2.7 V to 3.6 V
20
t
1
(3)
SCLK cycle time
ns
V
DD
= 3.6 V to 5.5 V
20
V
DD
= 2.7 V to 3.6 V
10
t
2
SCLK HIGH time
ns
V
DD
= 3.6 V to 5.5 V
10
V
DD
= 2.7 V to 3.6 V
10
t
3
SCLK LOW time
ns
V
DD
= 3.6 V to 5.5 V
10
V
DD
= 2.7 V to 3.6 V
4
SYNC falling edge to SCLK falling edge setup
t
4
ns
time
V
DD
= 3.6 V to 5.5 V
4
V
DD
= 2.7 V to 3.6 V
5
t
5
Data setup time
ns
V
DD
= 3.6 V to 5.5 V
5
V
DD
= 2.7 V to 3.6 V
4.5
t
6
Data hold time
ns
V
DD
= 3.6 V to 5.5 V
4.5
V
DD
= 2.7 V to 3.6 V
0
t
7
SCLK falling edge to SYNC rising edge
ns
V
DD
= 3.6 V to 5.5 V
0
V
DD
= 2.7 V to 3.6 V
20
t
8
Minimum SYNC HIGH time
ns
V
DD
= 3.6 V to 5.5 V
20
V
DD
= 2.7 V to 3.6 V
10
t
9
SCLK falling edge to SDO valid
ns
V
DD
= 3.6 V to 5.5 V
10
V
DD
= 2.7 V to 3.6 V
10
t
10
CLR pulse width low
ns
V
DD
= 3.6 V to 5.5 V
10
(1)
All input signals are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2)
See Serial Write Operation timing diagram
Figure 1
.
(3)
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
Figure 1. Serial Write Operation
5
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PRODUCT PREVIEW
PIN DESCRIPTION
1
2
3
4
12
11
10
9
SCLK
SYNC
IOV
DD
SDO
V
OUT
A
V
DD
GND
V
OUT
B
VFBA
VREF
A
PD
DCEN
CLR
SDIN
VFBB
VREFB
16 15 14 13
5
6
7
8
DAC7553
SLAS477 AUGUST 2005
RGT PACKAGE
(TOP VIEW)
Terminal Functions
TERMINAL
DESCRIPTION
NO.
NAME
1
VOUTA
Analog output voltage from DAC A
2
VDD
Analog voltage supply input
3
GND
Ground
4
VOUTB
Analog output voltage from DAC B
5
VFBB
DAC B amplifier sense input.
6
VREFB
Positive reference voltage input for DAC B
7
PD
Power down
8
DCEN
Daisy-chain enable
9
SDO
Serial data output
10
IOVDD
I/O voltage supply input
11
SYNC
Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out
to the DAC7553
12
SCLK
Serial clock input
13
SDIN
Serial data input
14
CLR
Asynchronous input to clear the DAC registers. When CLR is low, the DAC registers are set to 000H and the output to
midscale voltage.
15
VREFA
Positive reference voltage input for DAC A
16
VFBA
DAC A amplifier sense input.
6
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PRODUCT PREVIEW
TYPICAL CHARACTERISTICS
-1
-0.5
0
0.5
1
Linearity Error - LSB
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Input Code
Differential Linearity Error - LSB
Channel A
V
REF
= 4.096 V
V
DD
= 5 V
Channel B
V
REF
= 4.096 V
V
DD
= 5 V
Linearity Error - LSB
Digital Input Code
Differential Linearity Error - LSB
-1
-0.5
0
0.5
1
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Linearity Error - LSB
Digital Input Code
Differential Linearity Error - LSB
-1
-0.5
0
0.5
1
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Channel A
V
REF
= 2.5 V
V
DD
= 2.7 V
-1
-0.5
0
0.5
1
-0.5
-0.25
0
0.25
0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Channel B
V
REF
= 2.5 V
V
DD
= 2.7 V
Linearity Error - LSB
Digital Input Code
Differential Linearity Error - LSB
DAC7553
SLAS477 AUGUST 2005
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 2.
Figure 3.
LINEARITY ERROR AND
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs
vs
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 4.
Figure 5.
7
www.ti.com
PRODUCT PREVIEW
-40
-10
20
50
80
0
1
2
3
-1
T
A
- Free-Air Temperature -
C
Zero-Scale Error - mV
Channel A
Channel B
V
DD
= 5 V,
V
REF
= 4.096 V
-1
0
1
2
3
-40
-10
20
50
80
T
A
- Free-Air Temperature -
C
Zero-Scale Error - mV
Channel A
Channel B
V
DD
= 2.7 V,
V
REF
= 2.5 V
-2
-1
0
1
-40
-10
20
50
80
T
A
- Free-Air Temperature -
C
Full-Scale Error - mV
Channel A
Channel B
V
DD
= 2.7 V,
V
REF
= 2.5 V
-40
-10
20
50
80
-2
-1
0
1
T
A
- Free-Air Temperature -
C
Full-Scale Error - mV
Channel A
Channel B
V
DD
= 5 V,
V
REF
= 4.096 V
DAC7553
SLAS477 AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
ZERO-SCALE ERROR
ZERO-SCALE ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 6.
Figure 7.
FULL-SCALE ERROR
FULL-SCALE ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 8.
Figure 9.
8
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PRODUCT PREVIEW
0
0.05
0.1
0.15
0.2
0
5
10
15
Typical for All Channels
V
DD
= 2.7 V,
V
REF
= 2.5 V
V
DD
= 5.5 V,
V
REF
= 4.096 V
- Output V
oltage - V
V
O
I
SINK
- Sink Current - mA
DAC Loaded with 000h
5.20
5.30
5.40
5.50
0
5
10
15
Typical for All Channels
V
DD
= V
REF
= 5.5 V
- Output V
oltage - V
V
O
I
SOURCE
- Source Current - mA
DAC Loaded with FFFh
2.4
2.5
2.6
2.7
0
5
10
15
Typical for All Channels
V
DD
= V
REF
= 2.7 V
- Output V
oltage - V
V
O
I
SOURCE
- Source Current - mA
DAC Loaded with FFFh
0
50
100
150
200
250
300
350
400
0
512
1024 1536 2048 2560 3072 3584 4096
Digital Input Code
V
DD
= 5.5 V,
V
REF
= 4.096 V
V
DD
= 2.7 V,
V
REF
= 2.5 V
All Channels Powered, No Load
DDI
Supply Current -
-
A
DAC7553
SLAS477 AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
SINK CURRENT AT NEGATIVE RAIL
SOURCE CURRENT AT POSITIVE RAIL
Figure 10.
Figure 11.
SOURCE CURRENT AT POSITIVE RAIL
SUPPLY CURRENT
vs
DIGITAL INPUT CODE
Figure 12.
Figure 13.
9
www.ti.com
PRODUCT PREVIEW
200
250
300
350
400
-40
-10
20
50
80
110
V
DD
= 5.5 V,
V
REF
= 4.096 V
V
DD
= 2.7 V,
V
REF
= 2.5 V
All Channels Powered, No Load
DDI
Supply Current -
-
A
T
A
- Free-Air Temperature -
C
200
250
300
350
400
2.7
3.1
3.4
3.8
4.1
4.5
4.8
5.2
5.5
DDI
Supply Current -
-
A
V
DD
- Supply Volatge - V
All DACs Powered,
No Load,
V
REF
= 2.5 V
0
500
1000
1500
2000
253
264
275
286
297
308
319
330
341
f - Frequency - Hz
I
DD
- Current Consumption -
m
A
V
DD
= 5.5 V,
V
REF
= 4.096 V
V
LOGIC
- Logic Input Voltage - V
0
400
800
1200
1600
0
1
2
3
4
5
DDI
Supply Current -
-
A
T
A
= 25
5
C, SCL Input
(All Other Inputs = GND)
V
DD
= 5.5 V,
V
REF
= 4.096 V
V
DD
= 2.7 V,
V
REF
= 2.5 V
DAC7553
SLAS477 AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
Figure 14.
Figure 15.
SUPPLY CURRENT
HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V
vs
LOGIC INPUT VOLTAGE
Figure 16.
Figure 17.
10
www.ti.com
PRODUCT PREVIEW
0
500
1000
1500
239
249
259
269
279
289
299
309
319
f - Frequency - Hz
I
DD
- Current Consumption -
m
A
V
DD
= 2.7 V,
V
REF
= 2.5 V
-4
-2
0
2
4
0
512
1024 1536 2048 2560 3072 3584
Digital Input Code
T
otal Error - mV
4095
Channel A Output
Channel B Output
V
DD
= 5 V,
V
REF
= 4.096 V,
T
A
= 25
5
C
-4
-2
0
2
4
0
512
1024 1536
2048 2560 3072 3584
Digital Input Code
T
otal Error - mV
4095
Channel A Output
Channel B Output
V
DD
= 2.7 V,
V
REF
= 2.5 V,
T
A
= 25
5
C
0
1
2
3
4
5
- Output V
oltage - V
V
O
t - Time - 4
m
s/div
V
DD
= 5 V,
V
REF
= 4.096 V,
Power-Up Code 4000
DAC7553
SLAS477 AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V
TOTAL ERROR - 5 V
Figure 18.
Figure 19.
TOTAL ERROR - 2.7 V
EXITING POWER-DOWN MODE
Figure 20.
Figure 21.
11
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PRODUCT PREVIEW
0
1
2
3
4
5
V
DD
= 5 V,
Output Loaded With 200 pF to GND
Code 41 to 4055
- Output V
oltage - V
V
O
t - Time - 5
m
s/div
V
REF
= 4.096 V
0
1
2
3
V
DD
= 2.7 V,
Output Loaded With 200 pF to GND
Code 41 to 4055
- Output V
oltage - V
V
O
t - Time - 5
m
s/div
V
REF
= 2.5 V
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
Trigger Pulse
V
O
(5 mV/Div)
-
Time - (400 nS/Div)
DAC7553
SLAS477 AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
LARGE-SIGNAL SETTLING TIME - 5 V
LARGE-SIGNAL SETTLING TIME - 2.7 V
Figure 22.
Figure 23.
MIDSCALE GLITCH
WORST-CASE GLITCH
Figure 24.
Figure 25.
12
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PRODUCT PREVIEW
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
Time - (400 nS/Div)
Trigger Pulse
V
O
(5 mV/Div)
-
-100
-90
-80
-70
-60
-50
-40
0
1
2
3
4
5
6
7
8
9
10
V
DD
= 5 V, V
REF
= 4.096 V
-1 dB FSR Digital Input, Fs = 1 Msps
Measurement Bandwidth = 20 kHz
2nd Harmonic
3rd Harmonic
THD - T
otal Harmonic Distortion - dB
Output Frequency (Tone) - kHz
THD
DAC7553
SLAS477 AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
DIGITAL FEEDTHROUGH ERROR
CHANNEL-TO-CHANNEL CROSSTALK
FOR A FULL-SCALE SWING
Figure 26.
Figure 27.
TOTAL HARMONIC DISTORTION
vs
OUTPUT FREQUENCY
Figure 28.
13
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PRODUCT PREVIEW
3-Wire Serial Interface
POWER-DOWN MODE
DAC7553
SLAS477 AUGUST 2005
TYPICAL CHARACTERISTICS (continued)
The DAC7553 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface.
Table 1. Serial Interface Programming
CONTROL
DATA BITS
DAC(s)
FUNCTION
DB15
DB14
DB13
DB12
DB11-DB10
0
0
0
0
data
A
Single Channel Store. The TMP register of channel A is updated.
0
0
1
0
data
B
Single Channel Store. The TMP register of channel B is updated.
0
1
0
0
data
A
Single Channel Update. The TMP and DAC registers of channel A are
updated.
0
1
1
0
data
B
Single Channel Update. The TMP and DAC registers of channel A are
updated and the DAC register of channel B is updated with input register data.
1
0
0
0
data
A
Single Channel Update. The TMP and DAC registers of channel B are
updated.
1
0
1
0
data
B
Single Channel Update. The TMP and DAC registers of channel B are
updated and the DAC register of channel A is updated with input register data.
1
1
0
0
data
AB
All Channel Update. The TMP and DAC registers of channels A and B are
updated.
1
1
1
0
data
AB
All Channel DAC Update. The DAC register of channels A and B are updated
with input register data.
In power-down mode, the DAC outputs are programmed to one of three output impedances, 1 k
, 100 k
, or
floating.
Table 2. Power-Down Mode Control
EXTENDED CONTROL
DATA BITS
FUNCTION
DB15
DB14
DB13
DB12
DB11
DB10
DB9-DB0
0
0
X
1
0
0
X
PWD Hi-Z (all channels)
0
0
X
1
0
1
X
PWD 1 k
(all channels)
0
0
X
1
1
0
X
PWD 100 k
(all channels)
0
0
X
1
1
1
X
PWD Hi-Z (all channels)
0
1
X
1
0
0
X
PWD Hi-Z (selected channel = A)
0
1
X
1
0
1
X
PWD 1 k
(selected channel = A)
0
1
X
1
1
0
X
PWD 100 k
(selected channel = A)
0
1
X
1
1
1
X
PWD Hi-Z (selected channel = A)
1
0
X
1
0
0
X
PWD Hi-Z (selected channel = B)
1
0
X
1
0
1
X
PWD 1 k
(selected channel = B)
1
0
X
1
1
0
X
PWD 100 k
(selected channel = B)
1
0
X
1
1
1
X
PWD Hi-Z (selected channel = B)
1
1
X
1
0
0
X
PWD Hi-Z (all channels)
1
1
X
1
0
1
X
PWD 1 k
(all channels)
1
1
X
1
1
0
X
PWD 100 k
(all channels)
1
1
X
1
1
1
X
PWD Hi-Z (all channels)
14
www.ti.com
PRODUCT PREVIEW
THEORY OF OPERATION
D/A SECTION
OUTPUT BUFFER AMPLIFIERS
DAC External Reference Input
_
+
Resistor String
Ref +
Ref -
DAC Register
V
OUT
V
REF
GND
V
FB
100 k
W
100 k
W
50 k
W
Amplifier Sense Input
V
REF
To Output
Amplifier
R
R
R
R
GND
RESISTOR STRING
Power-On Reset
DAC7553
SLAS477 AUGUST 2005
The architecture of the DAC7553 consists of a string
The output buffer amplifier is capable of generating
DAC followed by an output buffer amplifier.
Figure 29
rail-to-rail voltages on its output, which gives an
shows a generalized block diagram of the DAC
output range of 0 V to V
DD
. It is capable of driving a
architecture.
load of 2 k
in parallel with up to 1000 pF to GND.
The source and sink capabilities of the output ampli-
fier can be seen in the typical curves. The slew rate is
1.8 V/s with a typical settling time of 3 s with the
output unloaded.
Two separate reference pins are provided for two
DACs, providing maximum flexibility. VREFA serves
DAC A and VREFB serves DAC B. VREFA and
Figure 29. Typical DAC Architecture
VREFB can be externally shorted together for sim-
plicity.
The 2s-complement input coding to the DAC7553
It is recommended to use a buffered reference in the
gives the ideal output voltage as:
external circuit (e.g., REF3140). The input impedance
V
OUT
= VREF D/4096
is typically 100 k
for each reference input pin..
Where D = decimal equivalent of the 2s-complement
input that is loaded to the DAC register, which can
range from 0 to 4095.
The DAC7553 contains two amplifier feedback input
pins, VFBA and VFBB. For voltage output operation,
VFBA and VFBB must externally connect to VOUTA
and VOUTB, respectively. For better DC accuracy,
these connections should be made at load points.
The VFBA and VFBB pins are also useful for a
variety of applications, including digitally controlled
current sources. Each feedback input pin is internally
connected to the DAC amplifier's negative input
terminal through a 100-k
resistor; and, the ampli-
Figure 30. Typical Resistor String
fier's negative input terminal internally connects to
ground through another 100-k
resistor (See
Fig-
ure 29
). This forms a gain-of-two, noninverting ampli-
fier configuration. Overall gain remains one because
The resistor string section is shown in
Figure 30
. It is
the resistor string has a divide-by-two configuration.
simply a string of resistors, each of value R. The
The resistance seen at each VFBx pin is approxi-
digital code loaded to the DAC register determines at
mately 200 k
to ground.
which node on the string the voltage is tapped off to
be fed into the output amplifier. The voltage is tapped
off by closing one of the switches connecting the
On power up, all internal registers are cleared and all
string to the amplifier. Because it is a string of
channels are updated with midscale voltages. Until
resistors, it is specified monotonic. The DAC7553
valid data is written, all DAC outputs remain in this
architecture uses four separate resistor strings to
state. This is particularly useful in applications where
minimize channel-to-channel crosstalk.
it is important to know the state of the DAC outputs
while the device is powering up. In order not to turn
on ESD protection devices, V
DD
should be applied
before any other pin is brought high.
15
www.ti.com
PRODUCT PREVIEW
Power Down
Asynchronous Clear
IOVDD and Level Shifters
Daisy-Chain Operation
SERIAL INTERFACE
16-Bit Word and Input Shift Register
DAC7553
SLAS477 AUGUST 2005
register input data. Bit 13 (DB13) determines whether
the data is for DAC A, DAC B, or both DACs. Bit 12
The DAC7553 has a flexible power-down capability
(DB12)
determines
either
normal
mode
or
as described in
Table 2
. Individual channels could be
power-down mode (see
Table 2
). All channels are
powered down separately or all channels could be
updated when bits 15 and 14 (DB15 and DB14) are
powered down simultaneously. During a power-down
high.
condition, the user has flexibility to select the output
impedance of each channel. During power-down
The SYNC input is a level-triggered input that acts as
operation, each channel can have either 1-k
,
a frame synchronization signal and chip enable. Data
100-k
, or Hi-Z output impedance to ground.
can only be transferred into the device while SYNC is
low. To start the serial data transfer, SYNC should be
taken low, observing the minimum SYNC to SCLK
falling edge setup time, t
4
. After SYNC goes low,
The DAC7553 output is asynchronously set to
serial data is shifted into the device's input shift
midscale voltage immediately after the CLR pin is
register on the falling edges of SCLK for 16 clock
brought low. The CLR signal resets all internal
pulses.
registers and therefore behaves like the Power-On
Reset. The DAC7553 updates at the first rising edge
When DCEN is low, the SDO pin is brought to a Hi-Z
of the SYNC signal that occurs after the CLR pin is
state. The first 16 data bits that follow the falling edge
brought back to high.
of SYNC are stored in the shift register. The rising
edge of SYNC that follows the 16
th
data bit updates
the DAC(s). If SYNC is brought high before the 16
th
data bit, no action occurs.
The DAC7553 can be used with different logic famil-
ies that require a wide range of supply voltages (from
When DCEN is high, data can continuously be shifted
1.8 V to 5.5 V). To enable this useful feature, the
into the shift register, enabling the daisy-chain oper-
IOVDD pin must be connected to the logic supply
ation. The SDO pin becomes active and outputs
voltage of the system. All DAC7553 digital input and
SDIN data with 16 clock cycle delay. A rising edge of
output pins are equipped with level-shifter circuits.
SYNC loads the shift register data into the DAC(s).
Level shifters at the input pins ensure that external
The loaded data consists of the last 16 data bits
logic high voltages are translated to the internal logic
received into the shift register before the rising edge
high voltage, with no additional power dissipation.
of SYNC.
Similarly, the level shifter for the SDO pin translates
If daisy-chain operation is not needed, DCEN should
the internal logic high voltage (VDD) to the external
permanently be tied to a logic low voltage.
logic high level (IOVDD). For single-supply operation,
the IOVDD pin can be tied to the VDD pin.
When DCEN pin is brought high, daisy chaining is
enabled. The Serial Data Output (SDO) pin is pro-
The DAC7553 is controlled over a versatile 3-wire
vided to daisy-chain multiple DAC7553 devices in a
serial interface, which operates at clock rates up to
system.
50 MHz and is compatible with SPI, QSPI, Microwire,
and DSP interface standards.
As long as SYNC is high or DCEN is low, the SDO
pin is in a high-impedance state. When SYNC is
In daisy-chain mode (DCEN = 1) the DAC7553
brought low, the output of the internal shift register is
requires a falling SCLK edge after the rising SYNC, in
tied to the SDO pin. As long as SYNC is low and
order to initialize the serial interface for the next
DCEN is high, SDO duplicates the SDIN signal with a
update.
16-cycle delay. To support multiple devices in a daisy
chain, SCLK and SYNC signals are shared across all
devices, and SDO of one DAC7553 should be tied to
the SDIN of the next DAC7553. For n devices in such
The input shift register is 16 bits wide. DAC data is
a daisy chain, 16n SCLK cycles are required to shift
loaded into the device as a 16-bit word under the
the entire input data stream. After 16n SCLK falling
control of a serial clock input, SCLK, as shown in the
edges are received, following a falling SYNC, the
Figure 1
timing diagram. The 16-bit word, illustrated
data stream becomes complete and SYNC can be
in
Table 1
, consists of four control bits followed by 12
brought high to update n devices simultaneously.
bits of DAC data. The 12-bit data is in 2s-complement
SDO operation is specified at a maximum SCLK
format, with 800H corresponding to 0-V output and
speed of 10 MHz.
7FFH corresponding to full-scale output (V
REF
1
LSB). Data is loaded MSB first (Bit 15) where the first
two bits (DB15 and DB14) determine if the input
register, DAC register, or both are updated with shift
16
www.ti.com
PRODUCT PREVIEW
INTEGRAL AND DIFFERENTIAL LINEARITY
GLITCH ENERGY
CHANNEL-TO-CHANNEL CROSSTALK
APPLICATION INFORMATION
Waveform Generation
Generating 5-V, 10-V, and 12-V Outputs For
DAC7553
V
REF
H
DAC7553
_
+
V
dac
R2
R1
REF3140
V
REF
V
tail
V
OUT
OPA130
V
out
+
V
REF
R2
R1
)
1
Din
4096
*
V
tail
R2
R1
(1)
DAC7553
SLAS477 AUGUST 2005
change the loop can generate. A DNL error less than
1 LSB (non-monotonicity) can create loop instability.
The DAC7553 uses precision thin-film resistors pro-
A DNL error greater than +1 LSB implies unnecess-
viding exceptional linearity and monotonicity. Integral
arily large voltage steps and missed voltage targets.
linearity error is typically within (+/-) 0.35 LSBs, and
With high DNL errors, the loop loses its stability,
differential linearity error is typically within (+/-) 0.08
resolution, and accuracy. Offering 12-bit ensured
LSBs.
monotonicity and 0.08 LSB typical DNL error, 755X
DACs are great choices for precision control loops.
Loop Speed:
The DAC7553 uses a proprietary architecture that
Many factors determine control loop speed. Typically,
minimizes glitch energy. The code-to-code glitches
the conversion time of the ADC and the computation
are so low, they are usually buried within the
time of the MCU are the two major factors that
wide-band noise and cannot be easily detected. The
dominate the time constant of the loop. DAC settling
DAC7553 glitch is typically well under 0.1 nV-s. Such
time is rarely a dominant factor because ADC conver-
low glitch energy provides more than 10X improve-
sion times usually exceed DAC conversion times.
ment over industry alternatives.
DAC offset, gain, and linearity errors can slow the
loop down only during the start-up. Once the loop
reaches its steady-state operation, these errors do
The DAC7553 architecture is designed to minimize
not affect loop speed any further. Depending on the
channel-to-channel crosstalk. The voltage change in
ringing characteristics of the loop's transfer function,
one channel does not affect the voltage output in
DAC glitches can also slow the loop down. With its 1
another channel. The DC crosstalk is in the order of a
MSPS (small-signal) maximum data update rate,
few microvolts. AC crosstalk is also less than 100
DAC7553 can support high-speed control loops.
dBs. This provides orders of magnitude improvement
Ultralow glitch energy of the DAC7553 significantly
over certain competing architectures.
improves loop stability and loop settling time.
Generating Industrial Voltage Ranges:
For control loop applications, DAC gain and offset
errors are not important parameters. This could be
exploited to lower trim and calibration costs in a
Due to its exceptional linearity, low glitch, and low
high-voltage control circuit design. Using an oper-
crosstalk, the DAC7553 is well suited for waveform
ational amplifier (OPA130), and a voltage reference
generation (from DC to 10 kHz). The DAC7553
(REF3140), the DAC7553 can generate the wide
large-signal settling time is 5 s, supporting an
voltage swings required by the control loop.
update rate of 200 KSPS. However, the update rates
can exceed 1 MSPS if the waveform to be generated
consists of small voltage steps between consecutive
DAC updates. To obtain a high dynamic range,
REF3140 (4.096 V) or REF02 (5 V) are rec-
ommended for reference voltage generation.
Precision Industrial Control
Industrial control applications can require multiple
feedback loops consisting of sensors, ADCs, MCUs,
DACs, and actuators. Loop accuracy and loop speed
Figure 31. Low-cost, Wide-swing Voltage Gener-
are the two important parameters of such control
ator for Control Loop Applications
loops.
Loop Accuracy:
The output voltage of the configuration is given by:
In a control loop, the ADC has to be accurate. Offset,
gain, and the integral linearity errors of the DAC are
not factors in determining the accuracy of the loop.
Fixed R1 and R2 resistors can be used to coarsely
As long as a voltage exists in the transfer curve of a
set the gain required in the first term of the equation.
monotonic DAC, the loop can find it and settle to it.
Once R2 and R1 set the gain to include some
On the other hand, DAC resolution and differential
minimal over-range, a DAC7553 channel could be
linearity do determine the loop accuracy, because
used to set the required offset voltage. Residual
each DAC step determines the minimum incremental
17
www.ti.com
PRODUCT PREVIEW
DAC7553
SLAS477 AUGUST 2005
errors are not an issue for loop accuracy because
For 10-V operation: R1=10 k
, R2 = 39 k
, V
tail
=
offset and gain errors could be tolerated. One
2.56 V, V
REF
= 4.096 V
DAC7553 channel can provide the Vtail voltage, while
For 12-V operation: R1=10 k
, R2 = 49 k
, V
tail
=
the other DAC7553 channel can provide Vdac voltage
2.45 V, V
REF
= 4.096 V
to help generate the high-voltage outputs.
For 5-V operation: R1=10 k
, R2 = 15 k
, V
tail
=
3.33 V, V
REF
= 4.096 V
18
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