Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- PACKAGE/ORDERING INFORMATION
- PIN DESCRIPTIONS
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS
- TIMING CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- THEORY OF OPERATION
- D/A SECTION
- RESISTOR STRING
- Output Amplifier
- I2C Interface
- F/S-Mode Protocol
- H/S-Mode Protocol
- DAC7574 I2C Update Sequence
- Address Byte
- Broadcast Address Byte
- Control Byte
- Most Significant Byte
- Least Significant Byte
- Default Readback Condition
- LDAC Functionality
- DAC7574 Registers
- DAC7574 as a Slave Receiver - Standard and Fast Mode
- DAC7574 as a Slave Receiver - High-Speed Mode
- Master Transmitter Writing to a Slave Receiver (DAC7574) in Standard/F\
ast Modes
- Master Transmitter Writing to a Slave Receiver (DAC7574) in HS Mode
- DAC7574 as a Slave Transmitter - Standard and Fast Mode
- DAC7574 as a Slave Transmitter - High-Speed Mode
- Master Receiver Reading From a Slave Transmitter (DAC7574) in Standard\
/Fast Modes
- Master Receiver Reading From a Slave Transmitter (DAC7574) in HS-Mode
- Power-On Reset
- Power-Down Modes
- CURRENT CONSUMPTION
- DRIVING RESISTIVE AND CAPACITIVE LOADS
- CROSSTALK
- OUTPUT VOLTAGE STABILITY
- SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
- APPLICATION INFORMATION
- BASIC CONNNECTIONS
- USING GPIO PORTS FOR I2C
- POWER SUPPLY REJECTION
- USING REF02 AS A POWER SUPPLY FOR DAC7574
- LAYOUT
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Resistor
Network
8
14
Data
Buffer A
DAC
Register A
Data
Buffer D
DAC
Register D
DAC A
DAC D
Buffer
Control
Register
Control
Power-Down
Control Logic
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
A0
A1
GND
I
2
C Block
SCL
SDA
V
DD
DAC7574
SLAS375 JUNE 2003
QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT,
I
2
C INTERFACE DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
Micropower Operation: 600 A at 5 V V
DD
The DAC7574 is a low-power, quad channel, 12-bit
Power-On Reset to Zero
buffered voltage output DAC. Its on-chip precision out-
put amplifier allows rail-to-rail output swing to be
+2.7 V to +5.5 V Analog Power Supply
achieved. The DAC7574 utilizes an I
2
C compatible two
12-Bit Monotonic
wire serial interface supporting high-speed interface
I
2
CTM Interface Up to 3.4 Mbps
mode with address support of up to four DAC7574s for
a total of 16 channels on the bus.
Data Transmit Capability
On-Chip Output Buffer Amplifier, Rail-to-Rail
The DAC7574 uses V
DD
and GND to set the output
Operation
range of the DAC. The DAC7574 incorporates a
Double-Buffered Input Register
power-on-reset circuit that ensures that the DAC output
powers up at zero volts and remains there until a valid
Address Support for up to Four DAC7574s
write takes place to the device. The DAC7574 contains
Synchronous Update Support for up to 16
a power-down feature, accessed via the internal control
Channels
register, that reduces the current consumption of the
Operation From -40
C to 105C
device to 200 nA at 5 V.
Small 10 Lead MSOP Package
The low power consumption of this part in normal
operation makes it ideally suited to portable battery
APPLICATIONS
operated equipment. The power consumption is less
Process Control
than 3mW at V
DD
= 5 V reducing to 1 W in power-down
mode.
Data Acquisition Systems
The DAC7574 is available in a 10-lead MSOP package.
Closed-Loop Servo Control
PC Peripherals
Portable Instrumentation
I2C is a trademark of Philips Corporation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily in-
clude testing of all parameters.
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A1
A0
1
2
3
4
5
6
7
8
10
9
V
OUT
A
V
OUT
B
GND
V
OUT
C
V
OUT
D
V
DD
SDA
SCL
DAC7574
DAC7574
SLAS375 JUNE 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
SPECIFICATION
PACKAGE
ORDERING
TRANSPORT MEDIA
DRAWING
TEMPERATURE
MARKING
NUMBER
NUMBER
RANGE
DAC7574
10-MSOP
DGS
-40
C TO +105C
D774
DAC7574IDGS
80 Piece Tube
DAC7574IDGSR
2500 Piece Tape and Reel
DGS PACKAGE
PIN DESCRIPTIONS
(TOPVIEW)
PIN
NAME
DESCRIPTION
1
V
OUT
A
Analog output voltage from DAC A
2
V
OUT
B
Analog output voltage from DAC B
Ground reference point for all circuitry on the
3
GND
part
4
V
OUT
C
Analog output voltage from DAC C
5
V
OUT
D
Analog output voltage from DAC D
6
SCL
Serial clock input
7
SDA
Serial data input and output
8
V
DD
Analog voltage supply input
9
A0
Device address select - I
2
C
10
A1
Device address select - I
2
C
ABSOLUTE MAXIMUM RATINGS (1)
V
DD
to GND
0.3 V to +6 V
Digital input voltage to GND
0.3 V to V
DD
+ 0.3 V
V
OUT
to GND
0.3 V to V
DD
+ 0.3 V
Operating temperature range
40
C to +105C
Storage temperature range
65
C to +150C
Junction temperature range (T
J
max)
+150
C
Power dissipation:
Thermal impedance (
JA)
270
C/W
Thermal impedance (
JC)
77
C/W
Lead temperature, soldering:
Vapor phase (60s)
215
C
Infrared (15s)
220
C
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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DAC7574
SLAS375 JUNE 2003
ELECTRICAL CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V, R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications -40
C to +105C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (1)
Resolution
12
Bits
Relative accuracy
8
LSB
Differential nonlinearity
Specified monotonic by design
1
LSB
Zero-scale error
5
20
mV
Full-scale error
-0.15
1.0
% of FSR
Gain error
1.0
% of FSR
Zero code error drift
7
V/
C
Gain temperature coefficient
3
ppm of
FSR/
C
OUTPUT CHARACTERISTICS (2)
Output voltage range
0
V
DD
V
Output voltage settling time (full scale)
R
L
=
; 0 pF < C
L
< 200 pF
8
10
s
R
L
=
; C
L
= 500 pF
12
s
Slew rate
1
V/s
DC crosstalk (channel-to-channel)
0.25
LSB
AC crosstalk (channel-to-channel)
1 kHz Sine Wave
-100
dB
Capacitive load stability
R
L
=
470
pF
R
L
= 2 k
1000
pF
Digital-to-analog glitch impulse
1 LSB change around major
12
nV-s
carry
Digital feedthrough
0.3
nV-s
DC output impedance
1
Short-circuit current
V
DD
= 5 V
50
mA
V
DD
= 3 V
20
mA
Power-up time
Coming out of power-down
2.5
s
mode, V
DD
= +5 V
Coming out of power-down
5
s
mode, V
DD
= +3 V
LOGIC INPUTS (2)
Input current
1
A
V
IN_L
, Input low voltage
0.3xV
DD
V
V
IN_H
, Input high voltage
V
DD
= 3 V
0.7xV
DD
V
Pin Capacitance
3
pF
POWER REQUIREMENTS
V
DD
2.7
5.5
V
I
DD
(normal operation), including reference current
Excluding load current
I
DD
@ V
DD
=+3.6V to +5.5V
V
IH
= V
DD
and V
IL
=GND
600
900
A
I
DD
@ V
DD
=+2.7V to +3.6V
V
IH
= V
DD
and V
IL
=GND
550
750
A
I
DD
(all power-down modes)
I
DD
@ V
DD
=+3.6V to +5.5V
V
IH
= V
DD
and V
IL
=GND
0.2
1
A
I
DD
@ V
DD
=+2.7V to +3.6V
V
IH
= V
DD
and V
IL
=GND
0.05
1
A
POWER EFFICIENCY
I
OUT
/I
DD
I
LOAD
= 2 mA, V
DD
= +5 V
93%
(1)
Linearity tested using a reduced code range of 48 to 4047; output unloaded.
(2)
Specified by design and characterization, not production tested.
3
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DAC7574
SLAS375 JUNE 2003
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 2.7 V to 5.5 V, R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications -40
C to +105C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TEMPERATURE RANGE
Specified performance
-40
+105
C
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V, R
L
= 2 k
to GND; all specifications -40C to +105C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Standard mode
100
kHz
Fast mode
400
kHz
f
SCL
SCL clock frequency
High-Speed Mode, C
B
= 100 pF max
3.4
MHz
High-speed mode, C
B
= 400 pF max
1.7
MHz
Standard mode
4.7
s
Bus free time between a
t
BUF
STOP and START condition
Fast mode
1.3
s
Standard mode
4.0
s
Hold time (repeated) START
t
HD
; t
STA
Fast mode
600
ns
condition
High-speed mode
160
ns
Standard mode
4.7
s
Fast mode
1.3
s
t
LOW
LOW period of the SCL clock
High-speed mode, C
B
= 100 pF max
160
ns
High-speed mode, C
B
= 400 pF max
320
ns
Standard mode
4.0
s
Fast mode
600
ns
t
HIGH
HIGH period of the SCL clock
High-Speed Mode, C
B
= 100 pF max
60
ns
High-speed mode, C
B
= 400 pF max
120
ns
Standard mode
4.7
s
Setup time for a repeated
t
SU
; t
STA
Fast mode
600
ns
START condition
High-speed mode
160
ns
Standard mode
250
ns
t
SU
; t
DAT
Data setup time
Fast mode
100
ns
High-speed mode
10
ns
Standard mode
0
3.45
s
Fast mode
0
0.9
s
t
HD
; t
DAT
Data hold time
High-speed mode, C
B
= 100 pF max
0
70
ns
High-speed mode, C
B
= 400 pF max
0
150
ns
Standard mode
20
0.1C
B
1000
ns
Fast mode
20
0.1C
B
300
ns
t
RCL
Rise time of SCL signal
High-speed mode, C
B
= 100 pF max
10
40
ns
High-speed mode, C
B
= 400 pF max
20
80
ns
Standard mode
20
0.1C
B
1000
ns
Rise time of SCL signal after
Fast mode
20
0.1C
B
300
ns
a repeated START condition
t
RCL1
and after an acknowledge
High-speed mode, C
B
= 100 pF max
10
80
ns
BIT
High-speed mode, C
B
= 400 pF max
20
160
ns
Standard mode
20
0.1C
B
300
ns
Fast mode
20
0.1C
B
300
ns
t
FCL
Fall time of SCL signal
High-speed mode, C
B
= 100 pF max
10
40
ns
High-speed mode, C
B
= 400 pF max
20
80
ns
4
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DAC7574
SLAS375 JUNE 2003
TIMING CHARACTERISTICS (continued)
V
DD
= 2.7 V to 5.5 V, R
L
= 2 k
to GND; all specifications -40C to +105C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Standard mode
20
0.1C
B
1000
ns
Fast mode
20
0.1C
B
300
ns
t
RDA
Rise time of SDA signal
High-speed mode, C
B
= 100 pF max
10
80
ns
High-speed mode, C
B
= 400 pF max
20
160
ns
Standard mode
20
0.1C
B
300
ns
Fast mode
20
0.1C
B
300
ns
t
FDA
Fall time of SDA signal
High-speed mode, C
B
= 100 pF max
10
80
ns
High-speed mode, C
B
= 400 pF max
20
160
ns
Standard mode
4.0
s
Setup time for STOP con-
t
SU
; t
STO
Fast mode
600
ns
dition
High-speed mode
160
ns
Capacitive load for SDA and
C
B
400
pF
SCL
Fast mode
50
ns
Pulse width of spike sup-
t
SP
pressed
High-speed mode
10
ns
Standard mode
Noise margin at the HIGH
V
NH
level for each connected de-
Fast mode
0.2 V
DD
V
vice (including hysteresis)
High-speed mode
Standard mode
Noise margin at the LOW
V
NL
level for each connected de-
Fast mode
0.1 V
DD
V
vice (including hysteresis)
High-speed mode
5
www.ti.com
- 8
- 6
- 4
- 2
0
2
4
6
8
Channel A
LE
-
LSB
V
DD
= 5 V
- 1.0
- 0.5
0.0
0.5
1.0
0
512
1024
1536
2048
2560
3072
3584
DLE
-
LSB
Digital Input Code
- 8
- 6
- 4
- 2
0
2
4
6
8
Channel B
LE
-
LSB
V
DD
= 5 V
- 1.0
- 0.5
0.0
0.5
1.0
0
512
1024
1536
2048
2560
3072
3584
DLE
-
LSB
Digital Input Code
- 8
- 6
- 4
- 2
0
2
4
6
8
Channel C
LE
-
LSB
V
DD
= 5 V
- 1.0
- 0.5
0.0
0.5
1.0
0
512
1024
1536
2048
2560
3072
3584
DLE
-
LSB
Digital Input Code
- 8
- 6
- 4
- 2
0
2
4
6
8
Channel D
LE
-
LSB
V
DD
= 5 V
- 1.0
- 0.5
0.0
0.5
1.0
0
512
1024
1536
2048
2560
3072
3584
DLE
-
LSB
Digital Input Code
- 8
- 6
- 4
- 2
0
2
4
6
8
Channel A
LE
-
LSB
V
DD
= 2.7 V
- 1.0
- 0.5
0.0
0.5
1.0
0
512
1024
1536
2048
2560
3072
3584
DLE
-
LSB
Digital Input Code
- 8
- 6
- 4
- 2
0
2
4
6
8
Channel B
LE
-
LSB
V
DD
= 2.7 V
- 1.0
- 0.5
0.0
0.5
1.0
0
512
1024
1536
2048
2560
3072
3584
DLE
-
LSB
Digital Input Code
DAC7574
SLAS375 JUNE 2003
TYPICAL CHARACTERISTICS
At T
A
= +25
C, unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 1.
Figure 2.
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 3.
Figure 4.
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 5.
Figure 6.
6
www.ti.com
- 8
- 6
- 4
- 2
0
2
4
6
8
Channel C
LE
-
LSB
V
DD
= 2.7 V
- 1.0
- 0.5
0.0
0.5
1.0
0
512
1024
1536
2048
2560
3072
3584
DLE
-
LSB
Digital Input Code
- 8
- 6
- 4
- 2
0
2
4
6
8
Channel D
LE
-
LSB
V
DD
= 2.7 V
- 1.0
- 0.5
0.0
0.5
1.0
0
512
1024
1536
2048
2560
3072
3584
DLE
-
LSB
Digital Input Code
5
10
15
20
- 40
- 10
20
50
80
T
A
- Free - Air Temperature -
C
Zero-Scale Error
-
mV
V
DD
= 5 V
CH A
CH B
CH C
CH D
0
5
10
15
- 40
- 10
20
50
80
T
A
- Free - Air Temperature -
C
Zero-Scale Error
-
mV
V
DD
= 2.7 V
CH A
CH B
CH C
CH D
0
5
10
15
20
25
30
- 40
- 10
20
50
80
CH A
CH B
CH D
T
A
- Free - Air Temperature -
C
Full-Scale Error
-
mV
V
DD
= 5 V
CH C
0
5
10
15
20
- 40
- 10
20
50
80
T
A
- Free - Air Temperature -
C
Full-Scale Error
-
mV
V
DD
= 2.7 V
CH A
CH B
CH C
CH D
DAC7574
SLAS375 JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
LINEARITY ERROR vs DIGITAL INPUT CODE
Figure 7.
Figure 8.
ZERO-SCALE ERROR
ZERO-SCALE ERROR
vs TEMPERATURE
vs TEMPERATURE
Figure 9.
Figure 10.
FULL-SCALE ERROR
FULL-SCALE ERROR
vs TEMPERATURE
vs TEMPERATURE
Figure 11.
Figure 12.
7
www.ti.com
0.000
0.025
0.050
0.075
0.100
0.125
0.150
0
1
2
3
4
5
I
SINK
- Sink Current - mA
V
O
U
T
-
Output V
oltage
-
V
V
DD
= 2.7 V
V
DD
= 5.5 V
DAC Loaded With 000
H
Typical For All Channels
5.30
5.35
5.40
5.45
5.50
0
1
2
3
4
5
I
SOURCE
- Source Current - mA
V
O
U
T
-
Output V
oltage
-
V
DAC Loaded With FFF
H
V
DD
= 5.5 V
Typical For All Channels
2.3
2.4
2.5
2.6
2.7
0
1
2
3
4
5
I
SOURCE
- Source Current - mA
V
O
U
T
-
Output V
oltage
-
V
DAC Loaded With FFF
H
V
DD
= 2.7 V
Typical For All Channels
Digital Input Code
0
100
200
300
400
500
600
700
800
0
512
1024
1536
2048
2560
3072
3584
4096
I
D
D
-
Supply Current
-
A
V
DD
= 2.7 V
V
DD
= 5.5 V
All Channels Powered, No Load
T
A
- Free - Air Temperature -
C
0
100
200
300
400
500
600
700
- 40
- 10
20
50
80
110
I
D
D
-
Supply Current
-
A
V
DD
= 2.7 V
V
DD
= 5.5 V
All Channels Powered, No Load
V
DD
- Supply Voltage - V
200
250
300
350
400
450
500
550
600
650
700
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
I
D
D
-
Supply Current
-
A
All DACs Powered, No Load
DAC7574
SLAS375 JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
SINK CURRENT CAPABILITY
SOURCE CURRENT CAPABILITY
AT NEGATIVE RAIL
AT POSITIVE RAIL
Figure 13.
Figure 14.
SOURCE CURRENT CAPABILITY
SUPPLY CURRENT
AT POSITIVE RAIL
vs DIGITAL INPUT CODE
Figure 15.
Figure 16.
SUPPLY CURRENT
SUPPLY CURRENT
vs TEMPERATURE
vs SUPPLY VOLTAGE
Figure 17.
Figure 18.
8
www.ti.com
I
DD
- Current Consumption -
A
0
500
1000
1500
2000
500 520 540 560 580 600 620 640 660 680 700 720 740
V
DD
= 5 V
Frequency
V
Logic
- Logic Input Voltage - V
200
400
600
800
1000
1200
0
1
2
3
4
5
I
D
D
-
Supply Current
-
A
T
A
= 25
C
SCL Input (All Other Inputs = GND)
V
DD
= 2.7 V
V
DD
= 5.5 V
- 1
0
1
2
3
4
5
6
Time (2
s/div)
V
O
U
T
-
Output V
oltage
-
V
V
DD
= 5 V
Powerup to Code 4000
I
DD
- Current Consumption -
A
0
500
1000
1500
2000
400 420 440 460 480 500 520 540 560 580 600 620
V
DD
= 2.7 V
Frequency
2.40
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
Time (15
s/div)
V
O
U
T
-
Output V
oltage
-
V (20 mV/div)
V
DD
= 5 V
Code 7FF
H
to 800
H
to 7FF
H
(Glitch Occurs Every N*256 Code Boundary)
4.56
4.58
4.60
4.62
4.64
4.66
4.68
4.70
4.72
4.74
Time (15
s/div)
V
O
U
T
-
Output V
oltage
-
V (20 mV/div)
V
DD
= 5 V
Code EFF
H
to F00
H
to EFF
H
(Glitch Occurs Every N*256 Code
Boundary)
DAC7574
SLAS375 JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
SUPPLY CURRENT
HISTOGRAM
vs LOGIC INPUT VOLTAGE
OF CURRENT CONSUMPTION
Figure 19.
Figure 20.
HISTOGRAM
EXITING
OF CURRENT CONSUMPTION
POWER-DOWN MODE
Figure 21.
Figure 22.
OUTPUT GLITCH (Mid-Scale)
OUTPUT GLITCH (Worst Case)
Figure 23.
Figure 24.
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Digital Input Code
0
4
8
12
16
20
24
0
512
1024
1536
2048
2560
3072
3584
Output Error
-
mV
V
DD
= 5 V
T
A
= 25
C
Channel A Output
Channel B Output
Channel C Output
Channel D Output
Digital Input Code
- 6
- 2
2
6
10
14
18
0
512
1024
1536
2048
2560
3072
3584
Output Error
-
mV
V
DD
= 2.7 V
T
A
= 25
C
Channel B Output
Channel C Output
Channel D Output
Channel A Output
0
1
2
3
4
5
Time (25
s/div)
V
O
U
T
-
Output V
oltage
-
V
V
DD
= 5 V
Output Loaded with
200 pF to GND
10% to 90% FSR
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Time (25
s/div)
V
O
U
T
-
Output V
oltage
-
V
V
DD
= 2.7 V
Output Loaded with
200 pF to GND
10% to 90% FSR
DAC7574
SLAS375 JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25
C, unless otherwise noted.
ABSOLUTE ERROR
ABSOLUTE ERROR
Figure 25.
Figure 26.
LARGE SIGNAL
LARGE SIGNAL
SETTLING TIME
SETTLING TIME
Figure 27.
Figure 28.
10
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_
+
Resistor String
Ref+
Ref-
DAC Register
V
OUT
50 k
W
50 k
W
V
DD
GND
70 k
W
V
OUT
+
V
DD
D
4096
(1)
V
DD
To Output
Amplifier
R
R
R
R
GND
DAC7574
SLAS375 JUNE 2003
THEORY OF OPERATION
D/A SECTION
The architecture of the DAC7574 consists of a string DAC followed by an output buffer amplifier. Figure 29
shows a generalized block diagram of the DAC architecture.
Figure 29. R-String DAC Architecture
The input coding to the DAC7574 is unsigned binary, which gives the ideal output voltage as:
Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 4095.
RESISTOR STRING
The resistor string section is shown in Figure 30. It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
Figure 30. Typical Resistor String
Output Amplifier
The output buffer is a gain-of-2 noninverting amplifiers, capable of generating rail-to-rail voltages on its output,
which gives an output range of 0V to V
DD
. It is capable of driving a load of 2 k
in parallel with 1000 pF to GND.
The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/s
with a half-scale settling time of 8 s with the output unloaded.
I
2
C Interface
I
2
C is a 2-wire serial interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is idle, both SDA and SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C bus through
open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or
transmits data on the bus under control of the master device.
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DAC7574
SLAS375 JUNE 2003
THEORY OF OPERATION (continued)
The DAC7574 works as a slave and supports the following data transfer modes, as defined in the I
2
C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data
transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in
this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as
H/S-mode. The DAC7574 supports 7-bit addressing; 10-bit addressing and general call address are not
supported.
F/S-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 31. All I
2
C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 32). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 33) by pulling the SDA line low
during the entire high period of the 9
th
SCL cycle. Upon detecting this acknowledge, the master knows that
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 31). This releases the bus and stops the communication link
with the addressed slave. All I
2
C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition
, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
H/S-Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices.
The master generates a start condition followed by a valid serial byte containing H/S master code
00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to
acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to
support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the
start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that
transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the
internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated
start conditions should be used to secure the bus in H/S-mode.
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Start
Condition
SDA
Stop
Condition
SDA
SCL
S
P
SCL
Change of Data Allowed
Data Line
Stable;
Data Valid
SDA
SCL
Not Acknowledge
Acknowledge
1
2
8
9
Clock Pulse for
Acknowledgement
S
START
Condition
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
DAC7574
SLAS375 JUNE 2003
THEORY OF OPERATION (continued)
Figure 31. START and STOP Conditions
Figure 32. Bit Transfer on the I
2
C Bus
Figure 33. Acknowledge on the I
2
C Bus
13
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Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1
2
7
8
9
ACK
1
2
3 - 8
9
ACK
Address
R/W
DAC7574
SLAS375 JUNE 2003
Figure 34. Bus Protocol
DAC7574 I
2
C Update Sequence
The DAC7574 requires a start condition, a valid I
2
C address, a control byte, an MSB byte, and an LSB byte for a
single update. After the receipt of each byte, DAC7574 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I
2
C address selects the DAC7574. The control byte sets the operational
mode of the selected DAC7574. Once the operational mode is selected by the control byte, DAC7574 expects an
MSB byte followed by an LSB byte for data update to occur. DAC7574 performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
Control byte needs not to be resent until a change in operational mode is required. The bits of the control byte
continuously determine the type of update performed. Thus, for the first update, DAC7574 requires a start
condition, a valid I
2
C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,
DAC7574 needs an MSB byte and an LSB byte as long as the control command remains the same.
Using the I
2
C high-speed mode (f
scl
= 3.4 MHz), the clock running at 3.4 MHz, each 12-bit DAC update other than
the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge
signal), at 188.88 KSPS. Using the fast mode (f
scl
= 400 kHz), clock running at 400 kHz, maximum DAC update
rate is limited to 22.22 KSPS. Once a stop condition is received DAC7574 releases the I
2
C bus and awaits a new
start condition.
Address Byte
MSB
LSB
1
0
0
1
1
A1
A0
R/W
The address byte is the first byte received following the START condition from the master device. The first five
bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select
bits A1 and A0. The A1, A0 address inputs can be connected to V
DD
or digital GND, or can be actively driven by
TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of
the DAC7574. Up to 4 devices (DAC7574) can still be connected to the same I
2
C-Bus.
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DAC7574
SLAS375 JUNE 2003
Broadcast Address Byte
MSB
LSB
1
0
0
1
0
0
0
0
Broadcast addressing is also supported by DAC7574. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC7574 devices. DAC7574 is designed to work with other members of the
DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address,
DAC7574 responds regardless of the states of the address pins. Broadcast is supported only in write mode
(Master writes to DAC7574).
Control Byte
MSB
LSB
0
0
L1
L0
X
Sel1
Sel0
PD0
Table 1. Control Register Bit Descriptions
Bit Name
Bit Number/Description
L1
Load1 (Mode Select) Bit
Are used for selecting the update mode.
L2
Load0 (Mode Select) Bit
00
Store I
2
C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the
temporary register of a selected channel. This mode does not change the DAC output of the selected
channel.
01
Update selected DAC with I
2
C data. Most commonly utilized mode. The contents of MS-BYTE and
LS-BYTE (or power down information) are stored in the temporary register and in the DAC register of
the selected channel. This mode changes the DAC output of the selected channel with the new data.
10
4-Channel synchronous update. The contents of MS-BYTE and LS-BYTE (or power down information)
are stored in the temporary register and in the DAC register of the selected channel. Simultaneously,
the other three channels get updated with previously stored data from the temporary register. This
mode updates all four channels together.
11
Broadcast update mode. This mode has two functions. In broadcast mode, DAC7574 responds
regardless of local address matching, and channel selection becomes irrelevant as all channels update.
This mode is intended to enable up to 16 channels simultaneous update, if used with the I
2
C broadcast
address (1001 0000).
If Sel1=0
All four channels are updated with the contents of their temporary register
data.
If Sel1=1
All four channels are updated with the MS-BYTE and LS-BYTE data or
powerdown.
Sel1
Buff Sel1 Bit
Channel Select Bits
Sel0
Buff Sel0 Bit
00
Channel A
01
Channel B
10
Channel C
11
Channel D
PD0
Power Down Flag
0
Normal operation
1
Power-down flag (MSB7 and MSB6 indicate a power-down operation, as shown in Table 2).
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DAC7574
SLAS375 JUNE 2003
Table 2. Control Byte
C7
C6
C5
C4
C3
C2
C1
C0
MSB7
MSB6
MSB5...
Don't
MSB
MSB-1
MSB-2
0
0
Load1
Load0
Ch Sel 1
Ch Sel 0
PD0
Care
(PD1)
(PD2)
...LSB
DESCRIPTION
(Address
Select)
Write to temporary
0
0
X
0
0
0
Data
register A (TRA) with
data
Write to temporary
0
0
X
0
1
0
Data
register B (TRB) with
data
Write to temporary
0
0
X
1
0
0
Data
register C (TRC) with
data
Write to temporary
0
0
X
1
1
0
Data
register D (TRD) with
data
(00, 01, 10, or 11)
Write to TRx (selected
by C2 &C1
0
0
X
1
see Table 8
0
w/Powerdown Com-
mand
(00, 01, 10, or 11)
Write to TRx (selected
0
1
X
0
Data
by C2 &C1 and load
DACx w/data
(00, 01, 10, or 11)
Power-down DACx
0
1
X
1
see Table 8
0
(selected by C2 and
C1)
(00, 01, 10, or 11)
Write to TRx (selected
1
0
X
0
Data
by C2 &C1 w/ data and
load all DACs
(00, 01, 10, or 11)
Power-down DACx
1
0
X
1
see Table 8
0
(selected by C2 and
C1) & load all DACs
Broadcast Modes (controls up to 4 devices on a single serial bus)
Update all DACs, all
X
X
1
1
X
0
X
X
X
devices with previously
stored TRx data
Update all DACs, all
X
X
1
1
X
1
X
0
Data
devices with MSB[7:0]
and LSB[7:0] data
Power-down all DACs,
X
X
1
1
X
1
X
1
see Table 8
0
all devices
Most Significant Byte
Most Significant Byte MSB[7:0] consists of eight most significant bits of 12-bit unsigned binary D/A conversion
data. C0=1, MSB[7], MSB[6] indicate a powerdown operation as shown in Table 8.
Least Significant Byte
Least Significant Byte LSB[7:0] consists of the 4 least significant bits of the 12-bit unsigned binary D/A
conversion data, followed by 4 don't care bits. DAC7574 updates at the falling edge of the acknowledge signal
that follows the LSB[0] bit.
Default Readback Condition
If the user initiates a readback of a specified channel without first writing data to that specified channel, the
default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase.
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SLAVE ADDRESS R/W
A Ctrl-Byte
A MS-Byte A
LS-Byte
A/A
P
"0" (write)
Data Transferred
(n* Words + Acknowledge)
Word = 12 Bit
From Master to DAC7574
From DAC7574 to Master
A = Acknowledge (SDA LOW)
A = Not Acknowledge (SDA HIGH)
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
DAC7574 I
2
C-SLAVE ADDRESS:
1
0
0
1
1
A1
A0
R/W
MSB
LSB
Factory Preset
A0 = I
2
C Address Pin
A1 = I
2
C Address Pin
S
`0' = Write to DAC7574
`1' = Read from DAC7574
DAC7574
SLAS375 JUNE 2003
LDAC Functionality
Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal
that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the
channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four
DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only
be used after the buffers temporary registers are properly updated through software.
DAC7574 Registers
Table 3. DAC7574 Architecture Register Descriptions
Register
Description
CTRL[7:0]
Stores 8-bit wide control byte sent by the master
Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit
MSB[7:0]
power-down data.
LSB[7:0]
Stores the 4 least significant bits of unsigned binary data sent by the master.
TRA[13:0], TRB[13:0],
14-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 12
TRC[13:0], TRD[13:0]
LSBs store data.
DRA[13:0], DRB[13:0],
14-bit DAC registers for each channel. Two MSBs store power-down information, 12 LSBs store DAC data.
DRC[13:0], DRD[13:0]
An update of this register means a DAC update with data or power-down.
DAC7574 as a Slave Receiver - Standard and Fast Mode
Figure 35 shows the standard and fast mode master transmitter addressing a DAC7574 Slave Receiver with a
7-bit address.
Figure 35. Standard and Fast Mode: Slave Receiver
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HS-Master Code
R/W
A Ctrl-Byte
A MS-Byte A
LS-Byte
A/A
P
"0" (write)
Data Transferred
(n* Words + Acknowledge)
Word = 12 Bit
S
A Sr Slave Address
HS-Mode Continues
F/S-Mode
HS-Mode
F/S-Mode
Sr Slave Address
0
0
0
0
1
X
X
R/X
MSB
LSB
HS-Mode Master Code:
0
0
L1
L0
X
Sel1 Sel2 PD0
MSB
LSB
Control Byte:
L1
= Load1 (Mode Select) Bit
L0
= Load0 (Mode Select) Bit
Sel1 = Buff Sel1 (Channel) Select Bit
Sel0 = Buff Sel0 (Channel) Select Bit
PD0 = Power Down Flag
X
= Don't Care
D11
D10
D9
D8
D7
D6
D5
D4
MSB
LSB
MS-Byte:
D3
D2
D1
D0
X
X
X
X
MSB
LSB
LS-Byte:
D11 - D0 = Data Bits
DAC7574
SLAS375 JUNE 2003
DAC7574 as a Slave Receiver - High-Speed Mode
Figure 36 shows the high-speed mode master transmitter addressing a DAC7574 Slave Receiver with a 7-bit
address.
Figure 36. High-Speed Mode: Slave Receiver
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DAC7574
SLAS375 JUNE 2003
Master Transmitter Writing to a Slave Receiver (DAC7574) in Standard/Fast Modes
All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This
control byte specifies the operation mode of DAC7574 and determines which channel of DAC7574 is being
accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the
following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC7574 expects to receive data in the following sequence HIGH-BYTE LOW-BYTE
HIGH-BYTE LOW-BYTE
..., until a STOP Condition or REPEATED START Condition on the I
2
C-Bus is
recognized (refer to the DATA INPUT MODE section of Table 4).
With (PD0-Bit = 1) the DAC7574 expects to receive 2 Bytes of power-down data (refer to the POWER DOWN
MODE section of Table 4).
Table 4. Write Sequence in F/S Mode
DATA INPUT MODE
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (R/W=0)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 0
x
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=0)
DAC7574
DAC7574 Acknowledges
Master
D11
D10
D9
D8
D7
D6
D5
D4
Writing data word, high byte
DAC7574
DAC7574 Acknowledges
Master
D3
D2
D1
D0
x
x
x
x
Writing data word, low byte
DAC7574
DAC7574 Acknowledges
Master
Data or Stop or Repeated Start (1)
Data or done (2)
POWER DOWN MODE
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (R/W=0)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 0
x
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0 = 1)
DAC7574
DAC7574 Acknowledges
Master
PD1
PD2
0
0
0
0
0
0
Writing data word, high byte
DAC7574
DAC7574 Acknowledges
Master
0
0
0
0
x
x
x
x
Writing data word, low byte
DAC7574
DAC7574 Acknowledges
Master
Stop or Repeated Start (1)
Done
(1)
Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write.
(2)
Once DAC7574 is properly addressed and control byte is sent, HIGHBYTELOWBYTE sequences can repeat until a STOP
condition or repeated START condition is received.
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DAC7574
SLAS375 JUNE 2003
Master Transmitter Writing to a Slave Receiver (DAC7574) in HS Mode
When writing data to the DAC7574 in HS-mode, the master begins to transmit what is called the HS-Master
Code
(0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code
is followed by a NOT acknowledge.
The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with
R/W = 0) after which the DAC7574 acknowledges by pulling SDA low. This address byte is usually followed by
the control byte, which is also acknowledged by the DAC7574. The LSB of the control byte (PD0-Bit) determines
if the following data is power-down data or regular data.
With (PD0-Bit = 0) the DAC7574 expects to receive data in the following sequence HIGH-BYTE LOW-BYTE
HIGH-BYTE LOW-BYTE...., until a STOP condition or repeated start condition on the I
2
C-Bus is recognized
(refer to Table 5 HS-MODE WRITE SEQUENCE - DATA).
With (PD0-Bit = 1) the DAC7574 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE
WRITE SEQUENCE - POWER DOWN).
Table 5. Master Transmitter Writes to Slave Receiver (DAC7574) in HS-Mode
HS MODE WRITE SEQUENCE - DATA
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
0
0
0
0
1
X
X
X
HS Mode Master Code
No device may acknowledge HS mas-
NONE
Not Acknowledge
ter code
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (R/W=0)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 0
0
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=0)
DAC7574
DAC7574 Acknowledges
Master
D11
D10
D9
D8
D7
D6
D5
D4
Writing data word, MSB
DAC7574
DAC7574 Acknowledges
Master
D3
D2
D1
D0
x
x
x
x
Writing data word, LSB
DAC7574
DAC7574 Acknowledges
Master
Data or Stop or Repeated Start (1)
Data or done (2)
HS MODE WRITE SEQUENCE - POWER DOWN
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
0
0
0
0
1
X
X
X
HS Mode Master Code
No device may acknowledge HS mas-
NONE
Not Acknowledge
ter code
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (R/W = 0)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 2
0
Buff Sel 1
Buff Sel 0
PD0
Control Byte (PD0=1)
DAC7574
DAC7574 Acknowledges
Master
PD1
PD2
0
0
0
0
0
0
Writing data word, high byte
DAC7574
DAC7574 Acknowledges
Master
0
0
0
0
x
x
x
x
Writing data word, low byte
DAC7574
DAC7574 Acknowledges
Master
Stop or repeated start (1)
Done
(1)
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
(2)
Once DAC7574 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start
condition is received.
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SLAVE ADDRESS R/W
A Ctrl <7:1>
A
MS-Byte A
LS-Byte
A P
'0' (write)
Data Transferred
(2 Bytes + Acknowledge)
PDN-Byte:
PD1
PD2
1
1
1
1
1
1
MSB
LSB
S
PD0
Sr Slave Address
R/W A
'1' (read)
'0' = (Normal Mode)
A
PDN-Byte A
LS-Byte
A P
PD0
Sr Slave Address
R/W
A
MS-Byte A
(DAC7574)
(MASTER)
(MASTER)
'1' = (Power Down Flag)
Data Transferred
(3 Bytes + Acknowledge)
(DAC7574)
(MASTER)
(MASTER)
(MASTER)
PD1 = Power-Down Bit
PD2 = Power-Down Bit
'1' (read)
(DAC7574)
(DAC7574)
Slave Address
R/W A Ctrl <7:1>
A
MS-Byte A
LS-Byte
A P
'0' (write)
Data Transferred
(2 Bytes + Acknowledge)
PD0
Sr
Slave Address
R/W A
'1' (read)
'0' = (Normal Mode)
A
PDN-Byte A
LS-Byte
A P
PD0
Sr Slave Address
R/W
A
MS-Byte A
(DAC7574)
(DAC7574)
(DAC7574)
(MASTER)
(MASTER)
'1' = (Power -Down Flag)
Data Transferred
(3 Bytes + Acknowledge)
(DAC7574)
(MASTER)
(MASTER)
(MASTER)
Sr
HS-Mode
A
S
F/S-Mode
'1' (read)
HS-Master Code
DAC7574
SLAS375 JUNE 2003
DAC7574 as a Slave Transmitter - Standard and Fast Mode
Figure 37 shows the standard and fast mode master transmitter addressing a DAC7574 Slave Transmitter with a
7-bit address.
Figure 37. Standard and Fast Mode: Slave Transmitter
DAC7574 as a Slave Transmitter - High-Speed Mode
Figure 38 shows an I
2
C-Master addressing DAC7574 in high-speed mode (with a 7-bit address), as a Slave
Transmitter
.
Figure 38. High-Speed Mode: Slave Transmitter
21
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DAC7574
SLAS375 JUNE 2003
Master Receiver Reading From a Slave Transmitter (DAC7574) in Standard/Fast Modes
When reading data back from the DAC7574, the user begins with an address byte (with R/W = 0) after which the
DAC7574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which
is also acknowledged by the DAC7574. Following this there is a REPEATED START condition by the Master and
the address is resent with (R/W = 1). This is acknowledged by the DAC7574, indicating that it is prepared to
transmit data. Two or three bytes of data are then read back from the DAC7574, depending on the (PD0-Bit).
The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP Condition follows.
With the (PD0-Bit = 0) the DAC7574 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to
Table 2. Data Readback Mode - 2 bytes).
With the (PD0-Bit = 1) the DAC7574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE
followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 3 bytes).
Table 6. Read Sequence in F/S Mode
DATA READBACK MODE - 2 BYTES
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (R/W=0)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 0
x
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=0)
DAC7574
DAC7574 Acknowledges
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Read addressing (R/W = 1)
DAC7574
DAC7574 Acknowledges
DAC7574
D11
D10
D9
D8
D7
D6
D5
D4
Reading data word, high byte
Master
Master Acknowledges
DAC7574
D3
D2
D1
D0
x
x
x
x
Reading data word, low byte
Master
Master Not Acknowledges
Master signal end of read
Master
Stop or Repeated Start (1)
Done
DATA READBACK MODE - 3 BYTES
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (R/W=0)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 0
x
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0=1)
DAC7574
DAC7574 Acknowledges
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Read addressing (R/W = 1)
DAC7574
DAC7574 Acknowledges
DAC7574
PD1
PD2
1
1
1
1
1
1
Read power down byte
Master
Master Acknowledges
DAC7574
D11
D10
D9
D8
D7
D6
D5
D4
Reading data word, high byte
Master
Master Acknowledges
DAC7574
D3
D2
D1
D0
x
x
x
x
Reading data word, low byte
Master
Master Not Acknowledges
Master signal end of read
Master
Stop or Repeated Start (1)
Done
(1)
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
22
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DAC7574
SLAS375 JUNE 2003
Master Receiver Reading From a Slave Transmitter (DAC7574) in HS-Mode
When reading data to the DAC7574 in HS-MODE, the master begins to transmit, what is called the HS-Master
Code
(0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master
Code
is followed by a NOT acknowledge.
The Master then switches to HS-mode and issues a REPEATED START condition, followed by the address byte
(with R/W = 0) after which the DAC7574 acknowledges by pulling SDA low. This address byte is usually followed
by the control byte, which is also acknowledged by the DAC7574.
Then there is a REPEATED START condition initiated by the master and the address is resent with (R/W = 1).
This is acknowledged by the DAC7574, indicating that it is prepared to transmit data. Two or Three bytes of data
are then read back from the DAC7574, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0
determines, which channel data is read back. A STOP condition follows.
With the (PD0-Bit = 0) the DAC7574 transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to
Table 7 HS-Mode Readback Sequence).
With the (PD0-Bit = 1) the DAC7574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the
HIGH-BYTE
followed by the LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence).
Table 7. Master Receiver Reading Slave Transmitter (DAC7574) in HS-Mode
HS MODE READBACK SEQUENCE
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
0
0
0
0
1
X
X
X
HS Mode Master Code
No device may acknowledge HS
NONE
Not Acknowledge
master code
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (R/W=0)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 0
X
Buff Sel 1
Buff Sel 0
PD0
Control byte (PD0 = 1)
DAC7574
DAC7574 Acknowledges
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Read addressing (R/W=1)
DAC7574
DAC7574 Acknowledges
DAC7574
PD1
PD2
1
1
1
1
1
1
Power-down byte
Master
Master Acknowledges
DAC7574
D11
D10
D9
D8
D7
D6
D5
D4
Reading data word, high byte
Master
Master Acknowledges
DAC7574
D3
D2
D1
D0
x
x
x
x
Reading data word, low byte
Master
Master Not Acknowledges
Master signal end of read
Master
Stop or Repeated Start
Done
Power-On Reset
The DAC7574 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC
while it is in the process of powering up. No device pin should be brought high before supply is applied.
23
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Resistor
String DAC
Powerdown
Circuitry
V
OUT
Amplifier
Resistor
Network
DAC7574
SLAS375 JUNE 2003
Power-Down Modes
The DAC7574 contains four separate power-down modes of operation. The modes are programmable via two
most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits
correspond to the mode of operation of the device.
Table 8. Power-Down Modes of Operation for the DAC7574
CTRL[0]
MSB[7]
MSB[6]
OPERATING MODE
1
0
0
High Impedance Output
1
0
1
1 k
to GND
1
1
0
100 k
to GND
1
1
1
High Impedance
When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 A at 5 V per
channel. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not
only does the supply current fall but also the output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the advantage that the output impedance of the device
is known while in power-down mode. There are three different options: The output is connected internally to GND
through a 1 k
resistor, a 100 k resistor or left open-circuit (high impedance). The output stage is illustrated in
Figure 39.
Figure 39. Output Stage During Power Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power down is typically 2.5 s for V
DD
= 5 V and 5
s for V
DD
= 3 V. (See the Typical Curves section for additional information.)
The DAC7574 offers a flexible power-down interface based on channel register operation. A channel consists of
a single 12 bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR
and DR are both 14 bits wide. Two MSBs represent the power-down condition and the 12 LSBs represent data
for TR and DR. By using bits 13 and 14 of TR and DR, a power-down condition can be temporarily stored and
used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[13] and TR[12] (DR[13]
and DR[12]) when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC7574 treats power-down
conditions like data and all the operational modes are still valid for power down. It is possible to broadcast a
power-down condition to all the DAC7574s in the system, or it is possible to simultaneously power down a
channel while updating data on other channels.
CURRENT CONSUMPTION
The DAC7574 typically consumes 150A at V
DD
= 5 V and 125A at V
DD
= 3 V for each active channel, including
reference current consumption. Additional current consumption can occur at the digital inputs if V
IH
<< V
DD
. For
most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In
power-down mode, typical current consumption is 200 nA. A delay time of 10 to 20 ms after a power-down
command is issued to the DAC is typically sufficient for the power-down current to drop below 10 A.
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DAC7574
SLAS375 JUNE 2003
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC7574 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC7574 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2
k
can be driven by the DAC7574 while achieving a typical load regulation of 1%. As the load resistance drops
below 2 k
, the load regulation error increases. When the outputs of the DAC are driven to the positive rail under
resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this
occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within
approximately the top 20 mV of the DAC's digital input-to-voltage output transfer characteristic. The reference
voltage applied to the DAC7574 may be reduced below the supply voltage applied to V
DD
in order to eliminate
this condition if good linearity is a requirement at full scale (under resistive loading conditions).
CROSSTALK
The DAC7574 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low
crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel
is typically less than 0.5 LSBs. The ac crosstalk measured (for a full-scale, 1 kHz sine wave output generated at
one channel, and measured at the remaining output channel) is typically under -100 dB.
OUTPUT VOLTAGE STABILITY
The DAC7574 exhibits excellent temperature stability of
3 ppm/C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage of each channel to stay within a
25 V window
for a
1C ambient temperature change. Combined with good dc noise performance and true 12-bit differential
linearity, the DAC7574 becomes a perfect choice for closed-loop control applications.
SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
Settling time to within the 12-bit accurate range of the DAC7574 is achievable within 10 s for a full-scale code
change at the input. Worst case settling times between consecutive code changes is typically less than 2 s. The
high-speed serial interface of the DAC7574 is designed in order to support up to 188ksps update rate. For
full-scale output swings, the output stage of each DAC7574 channel typically exhibits less than 100 mV of
overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely
low (~10 V) given that the code-to-code transition does not cross an Nx256 code boundary. Due to internal
segmentation of the DAC7574, code-to-code glitches occur at each crossing of an Nx256 code boundary. These
glitches can approach 100 mVs for N = 15, but settle out within ~2 s. Sufficient bypass capacitance is required
to ensure 10 s settling under capacitive loading. To observe the settling performance under resistive load
conditions, the power supply (hence DAC7574 reference supply) must settle quicker than the DAC7574.
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www.ti.com
4
5
1
2
3
6
8
7
10
9
DAC7574
V
OUT
A
V
OUT
B
V
DD
V
OUT
C
GND
V
OUT
D
A1
A0
SDA
SCL
SDA
SCL
I
2
C Pullup Resistors
1 k
to 10 k
(typical)
V
DD
Microcontroller or
Microprocessor With
I
2
C Port
NOTE: DAC7574 power and input/output connections are omitted for clarity, except I
2
C Inputs.
DAC7574
SLAS375 JUNE 2003
APPLICATION INFORMATION
The following sections give example circuits and tips for using the DAC7574 in various applications. For more
information, contact your local TI representative, or visit the Texas Instruments website at http://www.ti.com.
BASIC CONNNECTIONS
For many applications, connecting the DAC7574 is extremely simple. A basic connection diagram for the
DAC7574 is shown in Figure 40. The 0.1 F bypass capacitors help provide the momentary bursts of extra
current needed from the supplies.
Figure 40. Typical DAC7574 Connections
The DAC7574 interfaces directly to standard mode, fast mode and high-speed mode I
2
C controllers. Any
microcontroller's I
2
C peripheral, including master-only and non-multiple-master I
2
C peripherals, work with the
DAC7574. The DAC7574 does not perform clock-stretching (i.e., it never pulls the clock line low), so it is not
necessary to provide for this unless other devices are on the same I
2
C bus.
Pullup resistors are necessary on both the SDA and SCL lines because I
2
C bus drivers are open-drain. The size
of the these resistors depend on the bus operating speed and capacitance on the bus lines. Higher-value
resistors consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value
resistors allow higher speed at the expense of higher power consumption. Long bus lines have higher
capacitance and require smaller pullup resistors to compensate. If the pullup resistors are too small the bus
drivers may not be able to pull the bus line low.
USING GPIO PORTS FOR I
2
C
Most microcontrollers have programmable input/output pins that can be set in software to act as inputs or
outputs. If an I
2
C controller is not available, the DAC7574 can be connected to GPIO pins, and the I
2
C bus
protocol simulated, or bit-banged, in software. An example of this for a single DAC7574 is shown in Figure 41.
26
www.ti.com
1
2
3
6
8
7
10
9
DAC7574
V
OUT
A
V
OUT
B
V
DD
GND
V
OUT
C
V
OUT
D
A1
A0
SDA
SCL
GPIO-2
GPIO-1
V
DD
Microcontroller or
Microprocessor
NOTE: DAC7574 power and input/output connections are omitted for clarity, except I
2
C Inputs.
4
5
DAC7574
SLAS375 JUNE 2003
APPLICATION INFORMATION (continued)
Figure 41. Using GPIO With a Single DAC7574
Bit-banging I
2
C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and
output modes to apply the proper bus states. To drive the line low, the pin is set to output a zero; to let the line
go high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is
pulling the line low, this reads as a zero in the port's input register.
Note that no pullup resistor is shown on the SCL line. In this simple case the resistor is not needed. The
microcontroller can simply leave the line on output, and set it to one or zero as appropriate. It can do this
because the DAC7574 never drives its clock line low. This technique can also be used with multiple devices, and
has the advantage of lower current consumption due to the absence of a resistive pullup.
If there are any devices on the bus that may drive their clock lines low, the above method should not be used.
The SCL line should be high-Z or zero, and a pullup resistor provided as usual. Note also that this cannot be
done on the SDA line in any case, because the DAC7574 drives the SDA line low from time to time, as all I
2
C
devices do.
Some microcontrollers have selectable strong pullup circuits built in to their GPIO ports. In some cases, these
can be switched on and used in place of an external pullup resistor. Weak pullups are also provided on some
microcontrollers, but usually these are too weak for I
2
C communication. Test any circuit before committing it to
production.
27
www.ti.com
REF02
15 V
5 V
1.6 mA
V
DD
SCL
SDA
I
2
C
Interface
V
OUT
= 0 V to 5 V
DAC7574
DAC7574
SLAS375 JUNE 2003
APPLICATION INFORMATION (continued)
POWER SUPPLY REJECTION
The positive reference voltage input of DAC7574 is internally tied to the power supply pin of the device. This
increases I
2
C system flexibility, creating room for an extra I
2
C address pin in a low pin-count package. To
eliminate the supply noise appearing at the DAC output, the user must pay close attention to how DAC7574 is
powered. The supply to DAC7574 must be clean and well regulated. For best performance, use of a precision
voltage reference is recommended to supply power to DAC7574. This is equivalent to providing a precision
external reference to the device. Due to low power consumption of DAC7574, load regulation errors are
negligible. In order to avoid excess power consumption at the Schmitt-triggered inputs of DAC7574, the precision
reference voltage should be close to the I
2
C bus pullup voltage. For 3-V, 3.3-V and 5-V I
2
C bus pullup voltages,
REF2930, REF2933 and REF02 precision voltage references are recommended respectively. These precision
voltage references can be used to supply power for multiple devices on a system.
USING REF02 AS A POWER SUPPLY FOR DAC7574
Due to the extremely low supply current required by the DAC7574, a possible configuration is to use a REF02
+5 V precision voltage reference to supply the required voltage to the DAC7574's supply input as well as the
reference input, as shown in Figure 42. This is especially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V. The REF02 outputs a steady supply voltage for the DAC7574.
If the REF02 is used, the current it needs to supply to the DAC7574 is 600 A typical and 900 A max for
V
DD
= 5 V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total
typical current required (with a 5-k
load on a single DAC output) is:
600 A + (5 V / 5 k
) = 1.6 mA
The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 400V for 1.6-mA of current
drawn from it. This corresponds to a 0.33 LSB error for a 0 V to 5 V output range.
Figure 42. REF02 Power Supply
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The power applied to V
DD
should be well-regulated and low noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
28
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DAC7574
SLAS375 JUNE 2003
As with the GND connection, V
DD
should be connected to a positive power-supply plane or trace that is separate
from the connection for digital logic until they are connected at the power-entry point. In addition, a 1 F to 10 F
capacitor in parallel with a 0.1 F bypass capacitor is strongly recommended. In some situations, additional
bypassing may be required, such as a 100 F electrolytic capacitor or even a Pi filter made up of inductors and
capacitors--all designed to essentially low-pass filter the 5 V supply, removing the high-frequency noise.
29
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