12-Bit, Parallel Input
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
The DAC7621 is a 12-bit digital-to-analog converter
(DAC) with guaranteed 12-bit monotonicity perfor-
mance over the industrial temperature range. It re-
quires a single +5V supply and contains an input
register, latch, 2.435V reference, DAC, and high speed
rail-to-rail output amplifier. For a full-scale step, the
output will settle to 1 LSB within 7
s. The device
consumes 2.5mW (0.5mA at 5V).
The parallel interface is compatible with a wide variety
of microcontrollers. The DAC7621 accepts a 12-bit
parallel word, has a double-buffered input logic struc-
ture and provides data readback. In addition, two
control pins provide a chip select (CS) function and
asynchronous clear (CLR) input. The CLR input can
be used to ensure that the DAC7621 output is 0V on
power-up or as required by the application.
The DAC7621 is available in a 20-lead SSOP package
and is fully specified over the industrial temperature
range of 40
C to +85
C.
FEATURES
q
LOW POWER: 2.5mW
q
FAST SETTLING: 7
s to 1 LSB
q
1mV LSB WITH 4.095V FULL-SCALE
RANGE
q
COMPLETE WITH REFERENCE
q
12-BIT LINEARITY AND MONOTONICITY
OVER INDUSTRIAL TEMP RANGE
q
ASYNCHRONOUS RESET TO 0V
APPLICATIONS
q
PROCESS CONTROL
q
DATA ACQUISITION SYSTEMS
q
CLOSED-LOOP SERVO-CONTROL
q
PC PERIPHERALS
q
PORTABLE INSTRUMENTATION
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
DAC7621
12-Bit DAC
Ref
DAC Register
Input Register
I/O Buffer
12
12
12
CLR
LOADDAC
CS
R/W
V
DD
V
OUT
DGND
DAC7621
D0
D1 D2
D3
D4
D5
D6
D7
D8
D9 D10 D11
DAC7621
1998 Burr-Brown Corporation
PDS-1502B
Printed in U.S.A. March, 1999
For most current data sheet and other product
information, visit www.burr-brown.com
SBAS107
2
DAC7621
SPECIFICATIONS
ELECTRICAL
At T
A
= 40
C to +85
C, and V
DD
= +5V, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
DAC7621E
DAC7621EB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
RESOLUTION
12
T
Bits
ACCURACY
Relative Accuracy
(1)
2
1/2
+2
1
1/4
+1
LSB
Differential Nonlinearity
Guaranteed Monotonic
1
1/2
+1
1
1/4
+1
LSB
Zero-Scale Error
Code 000
H
1
+1
+3
T
T
T
LSB
Full Scale Voltage
Code FFF
H
4.079
4.095
4.111
4.087
4.095
4.103
V
ANALOG OUTPUT
Output Current
Code 800
H
5
7
T
T
mA
Load Regulation
R
LOAD
402
, Code 800
H
1
3
T
T
LSB
Capacitive Load
No Oscillation
500
T
pF
Short-Circuit Current
20
T
mA
Short-Circuit Duration
GND or V
DD
Indefinite
T
DIGITAL INPUT
Data Format
Parallel
T
Data Coding
Straight Binary
T
Logic Family
CMOS
T
Logic Levels
V
IH
0.7 V
DD
T
V
V
IL
0.3 V
DD
T
V
I
IH
10
T
A
I
IL
10
T
A
DYNAMIC PERFORMANCE
Settling Time
(2)
(t
S
)
To
1 LSB of Final Value
7
T
s
DAC Glitch
5
T
nV-s
Digital Feedthrough
2
T
nV-s
POWER SUPPLY
V
DD
+4.75
+5.0
+5.25
T
T
T
V
I
DD
V
IH
= 5V, V
IL
= 0V, No Load, at Code 000
H
0.5
1
T
T
mA
Power Dissipation
V
IH
= 5V, V
IL
= 0V, No Load
2.5
5
T
T
mW
Power Supply Sensitivity
V
DD
=
5%
0.001
0.004
T
T
%/%
TEMPERATURE RANGE
Specified Performance
40
+85
T
T
C
T
Same specification as for DAC7621E.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where
the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.
3
DAC7621
PIN CONFIGURATION
Top View
SSOP
V
DD
to GND .......................................................................... 0.3V to 6V
Digital Inputs to GND .............................................. 0.3V to V
DD
+ 0.3V
V
OUT
to GND ........................................................... 0.3V to V
DD
+ 0.3V
Power Dissipation ........................................................................ 325mW
Thermal Resistance,
JA
........................................................... 150
C/W
Maximum Junction Temperature .................................................. +150
C
Operating Temperature Range ...................................... 40
C to +85
C
Storage Temperature Range ....................................... 65
C to +150
C
Lead Temperature (soldering, 10s) .............................................. +300
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
1
CLR
Reset. Resets the DAC register to zero. Active
LOW. Asynchronous input.
2
V
DD
Postive Power Supply
3
V
OUT
DAC Output Voltage
4
AGND
Analog Ground
5
DGND
Digital Ground
6
DB11
Data Bit 11, MSB
7
DB10
Data Bit 10
8
DB9
Data Bit 9
9
DB8
Data Bit 8
10
DB7
Data Bit 7
11
DB6
Data Bit 6
12
DB5
Data Bit 5
13
DB4
Data Bit 4
14
DB3
Data Bit 3
15
DB2
Data Bit 2
16
DB1
Data Bit 1
17
DB0
Data Bit 0, LSB
18
R/W
Read and Write Control
19
CS
Chip Select. Active LOW.
20
LOADDAC
Loads the internal DAC register. The DAC register
is a transparent latch and is transparent when
LOADDAC is LOW (regardless of the state of CS or
CLK).
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
DIFFERENTIAL
SPECIFICATION
PACKAGE
ACCURACY
NONLINEARITY
TEMPERATURE
DRAWING
ORDERING
TRANSPORT
PRODUCT
(LSB)
(LSB)
RANGE
PACKAGE
NUMBER
(1)
NUMBER
(2)
MEDIA
DAC7621E
2
1
40
C to +85
C
20-Lead SSOP
334
DAC7621E
Rails
"
"
"
"
"
"
DAC7621E/1K
Tape and Reel
DAC7621EB
1
1
40
C to +85
C
20-Lead SSOP
334
DAC7621EB
Rails
"
"
"
"
"
"
DAC7621EB/1K
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of "DAC7621E/1K" will get a single
1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
V
DD
V
OUT
AGND
DGND
DB11 (MSB)
DB10
DB9
DB8
DB7
LOADDAC
CS
R/W
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DAC7621E
4
DAC7621
TIMING DIAGRAMS
LOGIC TRUTH TABLE
TIMING SPECIFICATIONS
T
A
= 40
C to +85
C
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
t
RCS
CS LOW for Read
200
ns
t
RDS
R/W HIGH to CS LOW
10
ns
t
RDH
R/W HIGH after CS HIGH
0
ns
t
DZ
CS HIGH to Data Bus
100
ns
in High Impedance
t
CSD
CS LOW to Data Bus Valid
100
160
ns
t
WCS
CS LOW for Write
50
t
WS
R/W LOW to CS LOW
0
ns
t
WH
R/W LOW after CS HIGH
5
ns
t
DS
Data Valid to CS LOW
0
ns
t
DH
Data Valid after CS HIGH
5
ns
t
LWD
LOADDAC LOW
50
ns
INPUT
DAC
R/W
CS
LOADDAC
REGISTER
REGISTER
MODE
L
L
L
Write
Write
Write
L
L
H
Write
Hold
Write Input
H
L
H
Read
Hold
Read Input
X
H
L
Hold
Update
Update
X
H
H
Hold
Hold
Hold
X = Don't Care.
t
RCS
CS
t
RDS
t
RDH
t
CSD
t
DZ
R/W
Data Out
Data Valid
t
WCS
CS
t
WS
t
WH
R/W
t
LWD
LOADDAC
t
DS
t
DH
Data In
Data Output Timing
Digital Input Timing
5
DAC7621
TYPICAL PERFORMANCE CURVES
At T
A
= +25
, and V
DD
= 5V, unless otherwise specified.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
OUTPUT SWING vs LOAD
Output Voltage (V)
Load Resistance (
)
10
100
1k
10k
100k
1k
100
10
1
0.1
0.01
PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT
Delta V
OUT
(mV)
Current (mA)
0.001
0.01
0.1
1
10
100
85
C (mV)
40
C
Data = 000
H
25
C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
Supply Current (mA)
Logic Voltage (V)
5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
70
60
50
40
30
20
10
0
POWER SUPPLY REJECTION vs FREQUENCY
PSR (dB)
Frequency (Hz)
10
100
1k
10k
100k
1M
Data = FFF
H
V
DD
= 5V
200mV AC
5.0
4.8
4.6
4.4
4.2
4.0
MINIMUM SUPPLY VOLTAGE vs LOAD
V
DD
Minimum (V)
Output Load Current (mA)
0.010
0.100
1.000
10.000
V
FS
= 1 LSB
Data = FFF
H
BROADBAND NOISE
Noise Voltage (1mV/div)
Time (2
s/div)
Code = FFF
H
BW = 2MHz
6
DAC7621
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
, and V
DD
= 5V, unless otherwise specified.
80
60
40
20
0
20
40
60
80
SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE
Output Current (mA)
Output Voltage (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Positive
Current
Limit
Data = 800
H
Output tied to I
SOURCE
Negative
Current
Limit
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SUPPLY CURRENT vs TEMPERATURE
Supply Current (mA)
Temperature (
C)
40 30 20 10
0
10
20
30
40
50
60
70
80
90
V
LOGIC
= 3.5V
Data = FFF
H
No Load
V
DD
= 4.75V
V
DD
= 5.25V
V
DD
= 5.0V
LARGE-SIGNAL SETTLING TIME
1V/div
Time (20
s/div)
C
L
= 110pF
R
L
= No Load
LD
V
OUT
RISE TIME DETAIL
Output Voltage (1mV/div)
Time (10
s/div)
LD
V
OUT
MID-SCALE GLITCH PERFORMANCE
V
OUT
(2mV/div)
Time (500ns/div)
V
OUT
LOADDAC
7FF
H
to 800
H
MID-SCALE GLITCH PERFORMANCE
V
OUT
(2mV/div)
Time (500ns/div)
LOADDAC
800
H to
7FF
H
V
OUT
7
DAC7621
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
, and V
DD
= 5V, unless otherwise specified.
FALL TIME DETAIL
Output Voltage (1mV/div)
Time (10
s/div)
LD
V
OUT
10.000
1.000
0.100
0.010
OUTPUT VOLTAGE NOISE vs FREQUENCY
Noise (
V/
Hz)
Frequency (Hz)
10
100
1k
10k
100k
Data = FFF
H
8
6
4
2
0
2
4
6
8
Output Voltage Change (mV)
Hours of Operation at +150
C
LONG-TERM DRIFT ACCELERATED BY BURN-IN
0
400
200
600
800
1000
1200
avg
max
min
144 Units
0
10
20
30
40
50
60
12
8
4
0
4
8
12
T.U.E =
INL = Z
S
+ FS
Sample Size = 300 Units
T
A
= +25
C
Number of Units
TOTAL UNADJUSTED ERROR HISTOGRAM
4.115
4.110
4.105
4.100
4.095
4.090
4.085
4.080
4.075
FULL-SCALE VOLTAGE vs TEMPERATURE
Full-Scale Output (V)
Temperature (
C)
50
0
25
25
50
75
100
125
No Load
Sample Size = 300
Avg + 3
Avg 3
Avg
3
2
1
0
1
ZERO-SCALE VOLTAGE vs TEMPERATURE
Zero-Scale (mV)
Temperature (
C)
50
0
25
25
50
75
100
125
8
DAC7621
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
, and V
DD
= 5V, unless otherwise specified.
LINEARITY ERROR vs DIGITAL CODE
(at +25
C)
Linearity Error (LSBs)
0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
512
1024
1536
2048
2560
3072
3584
4096
Code
DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE
(at +25
C)
Differential Linearity Error (LSBs)
0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
512
1024
1536
2048
2560
3072
3584
4096
Code
LINEARITY ERROR vs DIGITAL CODE
(at +85
C)
Linearity Error (LSBs)
0
1
0.5
0
0.5
1.0
512
1024
1536
2048
2560
3072
3584
4096
Code
DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE
(at +85
C)
Differential Linearity Error (LSBs)
0
1
0.5
0
0.5
1.0
512
1024
1536
2048
2560
3072
3584
4096
Code
LINEARITY ERROR vs DIGITAL CODE
(at 40
C)
Linearity Error (LSBs)
0
1
0.5
0
0.5
1.0
512
1024
1536
2048
2560
3072
3584
4096
Code
DIFFERENTIAL LINEARITY ERROR vs DIGITAL CODE
(at 40
C)
Differential Linearity Error (LSBs)
0
1
0.5
0
0.5
1.0
512
1024
1536
2048
2560
3072
3584
4096
Code
9
DAC7621
The digital data into the DAC7621 is double-buffered. This
means that new data can be entered into the DAC without
disturbing the old data and the analog output of the con-
verter. At some point after the data has been entered into the
serial shift register, this data can be transferred into the DAC
register. This transfer is accomplished with a HIGH to LOW
transition of the LOADDAC pin. However, the LOADDAC
pin makes the DAC register transparent. If new data be-
comes available on the bus register while LOADDAC is
LOW, the DAC output voltage will change as the data
changes. To prevent this, CS must be returned HIGH prior
to changing data on the bus.
At any time, the contents of the DAC register can be set to
000
H
(analog output equals 0V) by taking the CLR input
LOW. The DAC register will remain at this value until CLR
is returned HIGH and LOADDAC is taken LOW to allow
the contents of the input register to be transferred to the
DAC register. If LOADDAC is LOW when CLR is taken
LOW, the DAC register will be set to 000
H
and the analog
output driven to 0V. When CLR is returned HIGH, the DAC
register and the analog output will respond accordingly.
DIGITAL-TO-ANALOG CONVERTER
The internal DAC section is a 12-bit voltage output
device that swings between ground and the internal ref-
erence voltage. The DAC is realized by a laser-trimmed
R-2R ladder network which is switched by N-channel
MOSFETs. The DAC output is internally connected to
the rail-to-rail output operational amplifier.
OPERATION
The DAC7621 is a 12-bit digital-to-analog converter (DAC)
complete with an input shift register, DAC register, laser-
trimmed 12-bit DAC, on-board reference, and a rail-to-rail
output amplifier. Figure 1 shows the basic operation of the
DAC7621.
INTERFACE
Figure 1 shows the basic connection between a
microcontroller and the DAC7621. The interface consists of
a Read/Write (R/W), data, and a load DAC signal
(LOADDAC). In addition, a chip select (CS) input is avail-
able to enable the DAC7621 when there are multiple de-
vices. The data format is Straight Binary. An asynchronous
clear input (CLR) is provided to simplify start-up or periodic
resets. Table I shows the relationship between input code
and output voltage.
DAC7621 Full-Scale Range = 4.095V
Least Significant Bit = 1mV
DIGITAL INPUT CODE
ANALOG OUTPUT
STRAIGHT OFFSET BINARY
(V)
DESCRIPTION
FFF
H
+4.095
Full Scale
801
H
+2.049
Midscale + 1 LSB
800
H
+2.048
Midscale
7FF
H
+2.047
Midscale 1 LSB
000
H
0
Zero Scale
TABLE I. Digital Input Code and Corresponding Ideal
Analog Output.
FIGURE 1. Basic Operation of the DAC7621.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
V
DD
V
OUT
AGND
DGND
DB11
DB10
DB9
DB8
DB7
LOADDAC
CS
R/W
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DAC7621E
Load DAC
Chip Select
Read/Write
10
F
+5V
Clear
Data Bus
Data Bus
0V to
+4.095V
0.1
F
+
10
DAC7621
OUTPUT AMPLIFIER
A precision, low-power amplifier buffers the output of the
DAC section and provides additional gain to achieve a 0V
to 4.095V range. The amplifier has low offset voltage, low
noise, and a set gain of 1.682V/V (4.095/2.435). See Figure
2 for an equivalent circuit schematic of the analog portion
of the DAC7621.
The output amplifier has a 7
s typical settling time to
1
LSB of the final value. Note that there are differences in the
settling time for negative-going signals versus positive-
going signals.
The rail-to-rail output stage of the amplifier provides the
full-scale range of 0V to 4.095V while operating on a
supply voltage as low as 4.75V. In addition to its ability to
drive resistive loads, the amplifier will remain stable while
driving capacitive loads of up to 500pF. See Figure 3 for an
equivalent circuit schematic of the amplifier's output driver
and the Typical Performance Curves section for more infor-
mation regarding settling time, load driving capability, and
output noise.
POWER SUPPLY
A BiCMOS process and careful design of the bipolar and
CMOS sections of the DAC7621 result in a very low power
device. Bipolar transistors are used where tight matching
and low noise are needed to achieve analog accuracy, and
CMOS transistors are used for logic, switching functions
and for other low power stages.
If power consumption is critical, it is important to keep the
logic levels on the digital inputs (R/W, CLK, CS, LOADDAC,
CLR) as close as possible to either V
DD
or ground. This will
keep the CMOS inputs (see "Supply Current vs Logic Input
Voltages" in the Typical Performance Curves) from shunt-
ing current between V
DD
and ground.
The DAC7621 power supply should be bypassed as shown
in Figure 1. The bypass capacitors should be placed as close
to the device as possible, with the 0.1
F capacitor taking
priority in this regard. The "Power Supply Rejection vs
Frequency" graph in the Typical Performance Curves sec-
tion shows the PSRR performance of the DAC7621. This
should be taken into account when using switching power
supplies or DC/DC converters.
In addition to offering guaranteed performance with V
DD
in
the 4.75V to 5.25V range, the DAC7621 will operate with
reduced performance down to 4.5V. Operation between
4.5V and 4.75V will result in longer settling time, reduced
performance, and current sourcing capability. Consult the
"V
DD
vs Load Current" graph in the Typical Performance
Curves section for more information.
FIGURE 3. Simplified Driver Section of Output Amplifier.
N-Channel
P-Channel
V
DD
V
OUT
AGND
2R
2R
2R
R
2R
2R
R
R
1
R
R
2
Output Amplifier
R-2R DAC
Bandgap
Reference
2.435V
Buffer
FIGURE 2. Simplified Schematic of Analog Portion.
11
DAC7621
FIGURE 4. Suggested Power and Ground Connections for a DAC7621 Sharing a +5V Supply with a Digital System with a
Single Ground Plane.
APPLICATIONS
POWER AND GROUNDING
The DAC7621 can be used in a wide variety of situations--
from low power, battery operated systems to large-scale
industrial process control systems. In addition, some appli-
cations require better performance than others, or are par-
ticularly sensitive to one or two specific parameters. This
diversity makes it difficult to define definite rules to follow
concerning the power supply, bypassing, and grounding.
The following discussion must be considered in relation to
the desired performance and needs of the particular system.
A precision analog component requires careful layout, ad-
equate bypassing, and a clean, well-regulated power supply.
As the DAC7621 is a single-supply, +5V component, it will
often be used in conjunction with digital logic,
microcontrollers, microprocessors, and digital signal proces-
sors. The more digital logic present in the design and the
higher the switching speed, the more difficult it will be to
achieve good performance.
The DAC7621 has separate analog ground and digital ground
pins. The current through DGND is mostly switching tran-
sients and are up to 4mA peak in amplitude. The current
through AGND is typically 0.5mA.
For best performance, separate analog and digital ground
planes with a single interconnection point to minimize
ground loops. The analog pins are located adjacent to each
other to help isolate analog from digital signals. Analog
signals should be routed as far as possible from digital
signals and should cross them at right angles. A solid analog
ground plane around the D/A package, as well as under it in
the vicinity of the analog and power supply pins, will isolate
the D/A from switching currents. It is recommended that
DGND and AGND be connected directly to the ground
planes under the package.
If several DAC7621s are used, or if sharing supplies with
other components, connecting the AGND and DGND lines
together at the power supplies once, rather than at each chip,
may produce better results.
The power applied to V
DD
should be well regulated and low-
noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between V
DD
and V
OUT
.
As with the GND connection, V
DD
should be connected to
a +5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 10
F and 0.1
F capaci-
tors shown in Figure 4 are strongly recommended and
should be installed as close to V
DD
and ground as possible.
In some situations, additional bypassing may be required
such as a 100
F electrolytic capacitor or even a "Pi" filter
made up of inductors and capacitors--all designed to essen-
tially lowpass filter the +5V supply, removing the high
frequency noise (see Figure 4).
+
+5V
GND
100
F
Digital Circuits
+5V
GND
+5V
Power
Supply
Other
Analog
Components
V
DD
AGND
DGND
DAC7621
+
10
F
0.1
F
Optional
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
DAC7621E
ACTIVE
SSOP
DB
20
68
DAC7621E/1K
ACTIVE
SSOP
DB
20
1000
DAC7621EB
ACTIVE
SSOP
DB
20
68
DAC7621EB/1K
ACTIVE
SSOP
DB
20
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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