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Электронный компонент: DAC7742Y/2K

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DAC7
742
16-Bit, Single Channel
DIGITAL-TO-ANALOG CONVERTER
With Internal Reference and Parallel Interface
DAC7742
SBAS256 DECEMBER 2002
www.ti.com
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Buffer
+10V
Reference
Control
Logic
Input
Register
I/O
Buffer
DAC
Register
DAC
REFEN
CS
R/W
RSTSEL
Data I/O
V
DD
V
REF
V
SS
V
CC
REFADJ
REF
OUT
REF
IN
R
OFFSET
RFB2
RFB1
SJ
V
OUT
AGND
DGND
LDAC
RST
16
DESCRIPTION
The DAC7742 is a 16-bit Digital-to-Analog Converter (DAC)
that provides 16 bits of monotonic performance over the
specified operating temperature range and offers a +10V,
low-drift internal reference. Designed for automatic test equip-
ment and industrial process control applications, the DAC7742
output swing can be configured in a
10V,
5V, or +10V
range. The flexibility of the output configuration allows the
DAC7742 to provide both unipolar and bipolar operation by
pin strapping. The DAC7742 includes a high-speed output
amplifier with a maximum settling time of 5
s to
0.003%
FSR for a 20V full-scale change and only consumes 100mW
(typical) of power.
The DAC7742 features a standard 16-bit parallel interface with
double buffering to allow asynchronous updates of the analog
output, and data read-back to support data integrity verification
prior to an update. A user-programmable reset control allows
the DAC output to reset to min-scale (FFFF
H
) or mid-scale
(7FFF
H
) overriding the DAC register values. The DAC7742 is
available in an LQFP-48 package and three performance
grades specified to operate from 40
C to +85
C.
FEATURES
q
LOW POWER: 150mW Maximum
q
+10V INTERNAL REFERENCE
q
UNIPOLAR OR BIPOLAR OPERATION
q
SETTLING TIME: 5
s to
0.003% FSR
q
16-BIT MONOTINICITY, 40
C TO +85
C
q
10V,
5V OR +10V CONFIGURABLE VOLTAGE
OUTPUT
q
RESET TO MIN-SCALE OR MID-SCALE
q
DOUBLE-BUFFERED DATA INPUT
q
INPUT REGISTER DATA READBACK
q
SMALL LQFP-48 PACKAGE
q
SUPPORTS TRANSPARENT DATA INPUT
OPERATION
APPLICATIONS
q
PROCESS CONTROL
q
ATE PIN ELECTRONICS
q
CLOSED-LOOP SERVO CONTROL
q
MOTOR CONTROL
q
DATA ACQUISITION SYSTEMS
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DAC7742
2
SBAS256
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
ABSOLUTE MAXIMUM RATINGS
(1)
V
CC
to V
SS
........................................................................... 0.3V to +32V
V
CC
to AGND ...................................................................... 0.3V to +16V
V
SS
to AGND ...................................................................... 16V to +0.3V
AGND
to DGND ................................................................. 0.3V to +0.3V
REF
IN
to AGND ..................................................................... 9V to +11V
V
DD
to DGND ................................................................. 0V to V
CC
1.4V
Digital Input Voltage to DGND ................................. 0.3V to V
DD
+ 0.3V
Digital Output Voltage to DGND .............................. 0.3V to V
DD
+ 0.3V
Operating Temperature Range ........................................ 40
C to +85
C
Storage Temperature Range ......................................... 65
C to +150
C
Junction Temperature .................................................................... +150
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
LINEARITY
DIFFERENTIAL
SPECIFIED
ERROR
NONLINEARITY
PACKAGE
TEMPERATURE
ORDERING
PACKAGE
TRANSPORT
PRODUCT
(LSB)
(LSB)
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
NUMBER
MARKING
MEDIA, QUANTITY
DAC7742
6
4
LQFP-48
PT
40
C to +85
C
DAC7742Y/250
DAC7742Y
Tape and Reel, 250
"
"
"
"
"
"
DAC7742Y/2K
"
Tape and Reel, 2000
DAC7742
4
2
LQFP-48
PT
40
C to +85
C
DAC7742YB/250
DAC7742YB
Tape and Reel, 250
"
"
"
"
"
"
DAC7742YB/2K
"
Tape and Reel, 2000
DAC7742
3
1
LQFP-48
PT
40
C to +85
C
DAC7742YC/250
DAC7742YC
Tape and Reel, 250
"
"
"
"
"
"
DAC7742YC/2K
"
Tape and Reel, 2000
NOTE: (1) For the most current specifications and package information refer to our web site at www.ti.com.
DAC7742Y
DAC7742YB
DAC7742YC
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ACCURACY
Linearity Error (INL)
6
4
3
LSB
T
A
= 25
C
5
3
2
LSB
Differential Linearity Error (DNL)
4
2
1
LSB
Monotonicity
14
15
16
Bits
Offset Error
0.1
% of FSR
Offset Error Drift
2
ppm/
C
Gain Error
With Internal REF
0.4
0.25
0.2
% of FSR
With External REF
0.25
0.1
% of FSR
Gain Error Drift
With Internal REF
15
10
7
ppm/
C
PSRR (V
CC
or V
SS
)
At Full-Scale
50
200
ppm/V
ANALOG OUTPUT
(1)
Voltage Output
(2)
+11.4/4.75
0 to 10
V
+11.4/11.4
10
V
+11.4/6.4
5
V
Output Current
5
mA
Output Impedance
0.1
Maximum Load Capacitance
200
pF
Short-Circuit Current
15
mA
Short-Circuit Duration
AGND
Indefinite
REFERENCE
Reference Output
9.96
10
10.04
9.975
10.025
V
REF
OUT
Impedance
400
REF
OUT
Voltage Drift
15
10
7
ppm/
C
REF
OUT
Voltage Adjustment
(3)
25
mV
REF
IN
Input Range
(4)
4.75
V
CC
1.4
V
REF
IN
Input Current
10
nA
REFADJ Input Range
Absolute Max Value that
0
10
V
can be applied is V
CC
REFADJ Input Impedance
50
k
V
REF
Output Current
2
+2
mA
V
REF
Impedance
1
ELECTRICAL CHARACTERISTICS
All specifications at T
A
= T
MIN
to T
MAX
, V
CC
= +15V, V
SS
= 15V, V
DD
= +5V, Internal reference enabled, unless otherwise noted.
DAC7742
3
SBAS256
www.ti.com
ELECTRICAL CHARACTERISTICS
(Cont.)
All specifications at T
A
= T
MIN
to T
MAX
, V
CC
= +15V, V
SS
= 15V, V
DD
= +5V, Internal reference enabled, unless otherwise noted.
DAC7742Y
DAC7742YB
DAC7742YC
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Settling Time to
0.003%
20V Output Step
3
4
s
R
L
= 5k
, C
L
= 200pF,
with external REF
OUT
to REF
IN
filter
(5)
Digital Feedthrough
2
nV-s
Output Noise Voltage
at 10kHz
100
nV/
Hz
DIGITAL INPUT
V
IH
|I
H
| < 10
A
0.7 V
DD
V
V
IL
|I
L
| < 10
A
0.3 V
DD
V
Input Coding
See Table III
DIGITAL OUTPUT
V
OH
I
OH
= 0.8mA
3.6
V
V
OL
I
OL
= 1.6mA
0.4
V
POWER SUPPLY
V
DD
+4.75
+5.0
+5.25
V
V
CC
+11.4
+15.75
V
V
SS
Bipolar Operation
15.75
11.4
V
Unipolar Operation
15.75
4.75
V
I
DD
100
A
I
CC
Unloaded
4
6
mA
I
SS
Unloaded
4
2.5
mA
Power
No Load, Ext. Reference
85
mW
No Load, Int. Reference
100
150
mW
TEMPERATURE RANGE
Specified Performance
40
+85
C
Specifications same as DAC7742Y.
NOTES: (1) With minimum V
CC
/V
SS
requirements, internal reference enabled. (2) Please refer to the "Theory of Operation" section for more information with respect to output
voltage configurations. (3) See Figure 7 for gain and offset adjustment connection diagrams when using the internal reference. (4) The minimum value for REF
IN
must be equal
to the greater of V
SS
+14V and +4.75V, where +4.75V is the minimum voltage allowed. (5) Reference low-pass filter values: 100k
, 1.0
F (See Figure 10).
DAC7742
4
SBAS256
www.ti.com
Top View
LQFP
PIN CONFIGURATION
PIN
NAME
DESCRIPTION
1
NC
No Connection
2
V
SS
Negative Analog Power Supply
3
V
CC
Positive Analog Power Supply
4
V
REF
Buffered Output from REF
IN
; can be used to
drive external devices. Internally, this pin
directly drives the DAC's circuitry.
5
R
OFFSET
Offsetting Resistor
6
AGND
Analog Ground (Must be tied to analog ground.)
7
AGND
Analog Ground (Must be tied to analog ground.)
8
RFB2
Feedback Resistor 2, used to configure DAC
output range.
9
RFB1
Feedback Resistor 1, used to configure DAC
output range.
10
SJ
Summing Junction of the Output Amplifier
11
V
OUT
DAC Voltage Output
12
NC
No Connection
13
NC
No Connection
14
NC
No Connection
15
NC
No Connection
16
DB0
Data Bit 0 (LSB)
17
DB1
Data Bit 1
18
DB2
Data Bit 2
19
DB3
Data Bit 3
20
DB4
Data Bit 4
21
DB5
Data Bit 5
22
DB6
Data Bit 6
23
NC
No Connection
24
NC
No Connection
25
NC
No Connection
26
TEST
Reserved, Connect to DGND
27
DB7
Data Bit 7
PIN DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
NC
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
TEST
NC
NC
REF
IN
REFADJ
REF
OUT
REFEN
RSTSEL
R/W
CS
LDAC
RST
V
DD
DGND
NC
NC
NC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
NC
V
SS
V
CC
V
REF
R
OFFSET
AGND
AGND
RFB2
RFB1
SJ
V
OUT
NC
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
DAC7742
28
DB8
Data Bit 8
29
DB9
Data Bit 9
30
DB10
Data Bit 10
31
DB11
Data Bit 11
32
DB12
Data Bit 12
33
DB13
Data Bit 13
34
DB14
Data Bit 14
35
DB15
Data Bit 15 (MSB)
36
NC
No Connection
37
DGND
Digital Ground
38
V
DD
Digital Power Supply
39
RST
V
OUT
reset; active LOW, depending on the state of
RSTSEL, the DAC register is either reset to mid-
scale or min-scale.
40
LDAC
DAC register load control, active LOW. Data is
loaded from the input register to the DAC register.
41
CS
Chip Select, Active LOW
42
R/W
Enabled by CS, controls data read (HIGH) and
write (LOW) from or to the input register.
43
RSTSEL
Reset Select; determines the action of RST. If
HIGH, RST will reset the DAC register to mid-
scale. If LOW, RST will reset the DAC register to
min-scale.
44
REFEN
Enables internal +10V reference (REF
OUT
), active
LOW.
45
REF
OUT
Internal Reference Output
46
REFADJ
Internal Reference Trim. (Acts as a gain
adjustment input when the internal reference is
used.)
47
REF
IN
Reference Input
48
NC
No Connection
PIN
NAME
DESCRIPTION
DAC7742
5
SBAS256
www.ti.com
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNITS
READ
t
RCS
CS LOW for Read
90
ns
t
RDS
R/W HIGH to CS LOW
10
ns
t
RDH
R/W HIGH After CS HIGH
10
ns
t
DZ
CS HIGH to Data Bus High Impedance
10
70
ns
t
CSD
CS LOW to Data Bus Valid
70
100
ns
WRITE
t
WS
R/W LOW to CS LOW
10
ns
t
WH
R/W LOW After CS HIGH
10
ns
t
WCS
CS LOW for Write
25
ns
t
LWD
LDAC LOW for Write
20
ns
t
LS
CS LOW to LDAC HIGH for Direct Update
30
ns
t
LH
CS LOW After LDAC HIGH
0
ns
t
DS
Data Valid to CS LOW
0
ns
t
DH
Data Valid After CS HIGH
20
ns
RESET
t
RSS
RST LOW
30
ns
t
SS
RSTSEL Valid Before RST LOW
0
ns
t
SH
RSTSEL Valid After RST HIGH
10
ns
ANALOG
t
S
Voltage Output Settling Time
5
s
TIMING CHARACTERISTICS
DAC7742Y
TIMING DIAGRAMS
READ CYCLE
RSTSEL
(RSTSEL = LOW)
(RSTSEL = HIGH)
RST
V
OUT
V
OUT
t
SS
t
SH
t
RSS
t
S
+FS
+FS
FS
FS
Min-Scale
Mid-Scale
RESET TIMING
DATA WRITE CYCLE
Data In
DB15-DB0
Data Valid
Data Valid
CS
R/W
LDAC
V
OUT
t
WCS
t
S
t
LS
t
LH
t
WH
t
LWD
t
WS
t
DH
t
DS
t
DS
t
DH
t
RCS
t
RDS
t
RDH
t
CSD
t
DZ
Data Valid
Data Out
DB15-DB0
R/W
CS
DAC7742
6
SBAS256
www.ti.com
TYPICAL CHARACTERISTICS
T
A
= +25
C (unless otherwise noted).
6
4
2
0
2
4
6
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
INL (LSB)
DNL (LSB)
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
FFFF
H
DFFF
H
BFFF
H
9FFF
H
7FFF
H
Digital Input Code
5FFF
H
3FFF
H
1FFF
H
0000
H
Bipolar Configuration: V
OUT
= 10V to +10V
T
A
= 85
C, Internal Reference Enabled
6
4
2
0
2
4
6
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
INL (LSB)
DNL (LSB)
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
Digital Input Code
Bipolar Configuration: V
OUT
= 10V to +10V
T
A
= 25
C, Internal Reference Enabled
FFFF
H
DFFF
H
BFFF
H
9FFF
H
7FFF
H
5FFF
H
3FFF
H
1FFF
H
0000
H
6
4
2
0
2
4
6
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
INL (LSB)
DNL (LSB)
LINEARITY ERROR AND DIFFERENTIAL
LINEARITY ERROR vs DIGITAL INPUT CODE
Digital Input Code
FFFF
H
DFFF
H
BFFF
H
9FFF
H
7FFF
H
5FFF
H
3FFF
H
1FFF
H
0000
H
Bipolar Configuration: V
OUT
= 10V to +10V
T
A
= 40
C, Internal Reference Enabled
5
4
3
2
1
0
1
2
3
4
5
Error (mV)
OFFSET ERROR vs TEMPERATURE
40
15
10
35
60
85
Temperature (
C)
V
OUT
= 10V to +10V
V
OUT
= 0V to +10V
0.15
0.10
0.05
0
0.05
Error (%)
40
15
10
35
60
85
Temperature (
C)
GAIN ERROR vs TEMPERATURE
Int. Ref, Unipolar Mode:
V
OUT
= 0V to +10V
Int. Ref, Bipolar Mode:
V
OUT
= 10V to +10V
Ext. Ref, Unipolar Mode:
V
OUT
= 0V to +10V
Ext. Ref, Bipolar Mode:
V
OUT
= 10V to +10V
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
I
CC
(mA)
Digital Input Code
V
CC
SUPPLY CURRENT vs DIGITAL INPUT CODE
Bipolar Configuration: V
OUT
= 10V to +10V
Internal Reference Enabled, T
A
= 25
C
FFFF
H
DFFF
H
BFFF
H
9FFF
H
7FFF
H
5FFF
H
3FFF
H
1FFF
H
0000
H
DAC7742
7
SBAS256
www.ti.com
TYPICAL CHARACTERISTICS
(Cont.)
T
A
= +25
C (unless otherwise noted).
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
I
CC
(mA)
Digital Input Code
V
CC
SUPPLY CURRENT vs DIGITAL INPUT CODE
Bipolar Configuration: V
OUT
= 10V to +10V
External Reference, REFEN = 5V, T
A
= 25
C
FFFF
H
DFFF
H
BFFF
H
9FFF
H
7FFF
H
5FFF
H
3FFF
H
1FFF
H
0000
H
1.50
1.75
2.00
2.25
2.50
2.75
I
SS
(mA)
Digital Input Code
V
SS
SUPPLY CURRENT vs DIGITAL INPUT CODE
Bipolar Configuration: V
OUT
= 10V to +10V
T
A
= 25
C
FFFF
H
DFFF
H
BFFF
H
9FFF
H
7FFF
H
5FFF
H
3FFF
H
1FFF
H
0000
H
SUPPLY CURRENT vs TEMPERATURE
Load Current Excluded, V
CC
= +15V, V
SS
= 15V
Bipolar V
OUT
Configuration: 10V to +10V
I
CC
I
SS
6
5
4
3
2
1
0
1
2
3
4
I
CC
, I
SS
(mA)
40
15
10
35
60
85
Temperature (
C)
1000
800
600
400
200
0
I
DD
(
A)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
LOGIC
(V)
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
T
A
= 25
C, Transition
Shown for One Data
Input (CS = 5V, R/W = 0)
100
90
80
70
60
50
40
30
20
10
0
Frequency
HISTOGRAM OF V
CC
CURRENT CONSUMPTION
3.000
3.500
4.000
4.500
5.000
I
CC
(mA)
Bipolar Output Configuration
Internal Reference Enabled
Code = AAAA
H
100
90
80
70
60
50
40
30
20
10
0
Frequency
HISTOGRAM OF V
SS
CURRENT CONSUMPTION
3.50
3.00
2.50
2.00
1.50
I
SS
(mA)
Bipolar Output Configuration
Internal Reference Enabled
Code = AAAA
H
DAC7742
8
SBAS256
www.ti.com
TYPICAL CHARACTERISTICS
(Cont.)
T
A
= +25
C (unless otherwise noted).
INTERNAL REFERENCE START-UP
V
CC
(5V/div)
REF
OUT
(2V/div)
Time (2ms/div)
0V
15V
0V
10V
10.015
10.010
10.005
10.000
9.995
9.990
9.985
REF
OUT
(V)
40
15
10
35
60
85
Temperature (
C)
INTERNAL REFERENCE OUTPUT vs TEMPERATURE
Source
Sink
OUTPUT VOLTAGE vs R
LOAD
12
8
4
0
4
8
12
V
OUT
(V)
0.0
0.1
1.0
10.0
100.0
R
LOAD
(k
)
10
0
10
20
30
40
50
60
70
80
PSRR (dB)
0.1k
1k
10k
100k
1M
10M
Frequency (Hz)
Bipolar Configuration:
10V V
OUT
Code 7FFF
H
V
SS
, V
CC
= 15V + 1Vp-p
V
DD
= 5V + 0.5Vp-p
V
SS
V
CC
V
DD
POWER-SUPPY REJECTION RATIO vs FREQUENCY
(Measured at V
OUT
)
10
0
10
20
30
40
50
60
70
80
PSRR (dB)
0.01k
0.1k
1k
10k
100k
1M
10M
POWER-SUPPY REJECTION RATIO vs FREQUENCY
(Measured at V
OUT
)
Frequency (Hz)
V
SS
V
CC
V
DD
Bipolar Configuration:
10V V
OUT
, Code 0000
H
V
SS
, V
CC
= 15V + 1Vp-p, V
DD
= 5V + 0.5Vp-p
Loaded to V
CC
V
CC
= +15V
Loaded to AGND
11.0
10.5
10.0
9.5
9.0
8.5
REF
OUT
(V)
REF
OUT
LOAD (k
)
REF
OUT
VOLTAGE vs LOAD
1
10
100
1k
DAC7742
9
SBAS256
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TYPICAL CHARACTERISTICS
(Cont.)
T
A
= +25
C (unless otherwise noted).
10
0
10
20
30
40
50
60
70
80
PSRR (dB)
1
10
100
1k
10k
100k
1M
10M
POWER-SUPPY REJECTION RATIO vs FREQUENCY
(Measured at REF
OUT
)
Frequency (Hz)
V
SS
V
CC
V
DD
Internal Reference Enabled
V
SS
, V
CC
= 15V + 1Vp-p,
V
DD
= 5V + 0.5Vp-p
900
800
700
600
500
400
300
200
100
0
Output Noise (nV/Hz)
0.01k
0.1k
1k
10k
100k
1M
10M
OUTPUT NOISE vs FREQUENCY
Frequency (Hz)
Unipolar Configuration, Internal Reference Enabled
Code 0000
H
Code FFFF
H
800
700
600
500
400
300
200
100
0
Output Noise (nV/rtHz)
0.01k
0.1k
1k
10k
100k
1M
10M
OUTPUT NOISE vs FREQUENCY
Frequency (Hz)
Bipolar Configuration:
10V, Internal Reference Enabled
Code FFFF
H
Code 0000
H
Code 7FFF
H
UNIPOLAR FULL-SCALE SETTLING TIME
Time (2
s/div)
Unipolar Configurtaion: V
OUT
= 0V to +10V
+ Full-Scale to Zero-Scale
5k
,
200pF Load
Large-Signal Output (5V/div)
Small-Signal Error (150
V/div)
BIPOLAR FULL-SCALE SETTLING TIME
Time (2
s/div)
Bipolar Configurtaion: V
OUT
= 10V to +10V
+Full-Scale to Full-Scale
5k
,
200pF Load
Large-Signal Output (5V/div)
Small-Signal Error (300
V/div)
BROADBAND NOISE
V
OUT
(V, 50
V/div)
Time (100
s/div)
Internal Reference Enabled
Filtered with 1.6Hz Low-Pass
Code 0000
H
, Bipolar
10V Configuration
10kHz Measurement BW
DAC7742
10
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TYPICAL CHARACTERISTICS
(Cont.)
T
A
= +25
C (unless otherwise noted).
Unipolar Configuration: V
OUT
= 0V to +10V
Zero-Scale to +Full-Scale
5k
, 200pF Load
Large-Signal Output (5V/div)
UNIPOLAR FULL-SCALE SETTLING TIME
Time (2
s/div)
Small-Signal Error (150
V/div)
Bipolar Configuration: V
OUT
= 10 to +10V
Full-Scale to +Full-Scale
5k
, 200pF Load
Large-Signal Output (5V/div)
BIPOLAR FULL-SCALE SETTLING TIME
Time (2
s/div)
Small-Signal Error (300
V/div)
Code 7FFF
H
to 8000
H
Bipolar Configuration:
10V V
OUT
MID-SCALE GLITCH
Time (1
s/div)
V
OUT
(V, 200mV/div)
MID-SCALE GLITCH
Time (1
s/div)
V
OUT
(V, 200mV/div)
Code 8000
H
to 7FFF
H
Bipolar Configuration:
10V V
OUT
DIGITAL FEEDTHROUGH
Time (200ns/div)
V
OUT
= 7FFF
H
(100mV/div)
All Data Bits Toggling (5V/div)
CS = 5V
DAC7742
11
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THEORY OF OPERATION
The DAC7742 is a voltage output, 16-bit DAC with a +10V built-
in internal reference. The architecture is an R-2R ladder con-
figuration with the three MSBs segmented, followed by an
operational amplifier that serves as a buffer, as shown in Figure
1. The output buffer is designed to allow user-configurable
output adjustments giving the DAC7742 output voltage ranges
of 0V to +10V, 5V to +5V, or 10V to +10V. Please refer to
Figures 2, 3, and 4 for pin configuration information.
The digital input is a parallel word made up of the 16-bit DAC
code and is loaded into the DAC register using the LDAC
input pin. The converter can be powered from
12V to
15V
dual analog supplies and a +5V logic supply. The device
offers a reset function, which immediately sets the DAC
output voltage and DAC register to min-scale (code FFFF
H
)
or mid-scale (code 7FFF
H
). The data I/O and reset functions
are discussed in more detail in the following sections.
FIGURE 1. DAC7742 Architecture.
FIGURE 2. Basic Operation: V
OUT
= 0V to +10V.
2R
2R
2R
2R
2R
2R
2R
2R
2R
R/4
R/2
R/2
R/4
R/4
R
R
OFFSET
RFB2
RFB1
SJ
V
OUT
V
REF
V
REF
AGND
REF
IN
REF
ADJ
REF
OUT
+10V Internal
Reference
Buffer
1
F
0.1
F
V
DD
1
F
0.1
F
V
SS
1
F
0.1
F
V
CC
Control Bus
Data Bus
Data Bus
36
35
34
33
32
31
30
29
28
27
26
25
NC
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
TEST
NC
DGND
V
DD
RST
LDAC
CS
R/W
RSTSEL
REFEN
REF
OUT
REFADJ
REF
IN
NC
NC
NC
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
NC
V
SS
V
CC
V
REF
R
OFFSET
AGND
AGND
RFB2
RFB1
SJ
V
OUT
NC
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
DAC7742
(0V to +10V)
DAC7742
12
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FIGURE 3. Basic Operation: V
OUT
= 5V to +5V.
FIGURE 4. Basic Operation: V
OUT
= 10V to +10V.
1
F
0.1
F
V
DD
1
F
0.1
F
V
SS
1
F
0.1
F
V
CC
Control Bus
Data Bus
Data Bus
36
35
34
33
32
31
30
29
28
27
26
25
NC
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
TEST
NC
1
2
3
4
5
6
7
8
9
10
11
12
NC
V
SS
V
CC
V
REF
R
OFFSET
AGND
AGND
RFB2
RFB1
SJ
V
OUT
NC
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
DAC7742
(5V to +5V)
DGND
V
DD
RST
LDAC
CS
R/W
RSTSEL
REFEN
REF
OUT
REFADJ
REF
IN
NC
NC
NC
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
NC
1
F
0.1
F
V
DD
1
F
0.1
F
V
SS
1
F
0.1
F
V
CC
Control Bus
Data Bus
Data Bus
36
35
34
33
32
31
30
29
28
27
26
25
NC
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
TEST
NC
1
2
3
4
5
6
7
8
9
10
11
12
NC
V
SS
V
CC
V
REF
R
OFFSET
AGND
AGND
RFB2
RFB1
SJ
V
OUT
NC
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
DAC7742
(10V to +10V)
DGND
V
DD
RST
LDAC
CS
R/W
RSTSEL
REFEN
REF
OUT
REFADJ
REF
IN
NC
NC
NC
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
NC
DAC7742
13
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CONTROL STATUS
COMMAND
R/W
CS
RST
RSTSEL
LDAC
Input Register
DAC Register
Mode
L
L
H
X
H
Write
Hold
Write Data to Input Register
X
H
H
X
L
Hold
Write
Update DAC Register with Data from Input
Register
L
L
H
X
L
Transparent
Write
Write DAC Register Directly from Data Bus
H
L
H
X
H, L
Read
Hold
Read Data in Input Register
X
H
H
X
H
Hold
Hold
No Change
X
X
L
L
X
Reset to Min-Scale
Reset to Min-Scale
Reset to Input and DAC Register (FFFF
H
)
Min-Scale
X
X
L
H
X
Reset to Mid-Scale
Reset to Mid-Scale
Reset to Input and DAC Register (7FFF
H
)
Mid-Scale
ANALOG OUTPUTS
The output amplifier can swing to within 1.4V of the supply
rails, specified over the 40
C to +85
C temperature range.
This allows for a
10V DAC voltage output operation from
12V supplies with a typical 5% tolerance.
When the DAC7742 is configured for a unipolar, 0V to 10V
output, a negative voltage supply is required. This is due to
internal biasing of the output stage. Please refer to the
"Electrical Characteristics" table for more information.
The minimum and maximum voltage output values are de-
pendent upon the output configuration implemented and
reference voltage applied to the DAC7742. Please note that
V
SS
(the negative power supply) must be in the range of
4.75V to 15.75V for unipolar operation. The voltage on V
SS
sets several bias points within the converter and is required
in all modes of operation. If V
SS
is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not ensured.
Supply sequence is important in establishing correct startup
of the DAC.
The digital supply (V
DD
) needs to establish correct bias
conditions before the analog supplies (V
CC
, V
SS
) are brought
up. If the digital supply cannot be brought up first, it must
come up before either analog supply (V
CC
or V
SS
), with the
preferred sequence of: V
SS
(device substrate), V
DD
, and then
V
CC
.
REFERENCE INPUTS
The DAC7742 provides a built-in +10V voltage reference and
on-chip buffer to allow external component reference drive. To
use the internal reference, REFEN must be LOW, enabling the
reference circuitry of the DAC7742 (as shown in Table I) and
the REF
OUT
pin must be connected to REF
IN
. This is the input
to the on-chip reference buffer. The buffer's output is provided
REFEN
ACTION
1
Internal Reference disabled;
REF
OUT
= High Impedance
0
Internal Reference enabled;
REF
OUT
= +10V
TABLE I. REFEN Action.
TABLE II. DAC7742 Logic Truth Table.
at the V
REF
pin. In this configuration, V
REF
is used to setup the
DAC7742 output amplifier into one of three voltage output
modes as discussed earlier. V
REF
can also be used to drive
other system components requiring an external reference.
The internal reference of the DAC7742 can be disabled when
use of an external reference is desired. When using an
external reference, the reference input, REF
IN
, can be any
voltage between 4.75V (or V
SS
+ 14V, whichever is greater)
and V
CC
1.4V.
DIGITAL INTERFACE
Table III shows the data format for the DAC7742 and
Table II illustrates the basic control logic of the device. The
interface consists of a chip select input (CS), read/write
control input (R/W), data inputs (DB0-DB15), and a load DAC
input (LDAC). An asynchronous reset input (RST) which is
active LOW, is provided to simplify start-up conditions, peri-
odic resets, or emergency resets to a known state, depend-
ing on the status of the reset select (RSTSEL) signal. The
DAC code is provided via a 16-bit parallel interface, as
shown in Table II. The input word makes up the DAC code
to be loaded into the data input register of the device. The
data is latched into the input register on rising CS and is
loaded into the DAC register upon reception of a LOW level
on the LDAC input. This action updates the analog output,
V
OUT
, to the desired value. LDAC inputs of multiple DAC7742s
can be connected when a synchronized update of numerous
DAC outputs is desired. Please refer to the timing section for
more detailed data I/O information.
TABLE III. DAC7742 Data Format.
ANALOG OUTPUT
DIGITAL INPUT
Unipolar Configuration
Bipolar Configuration
Complementary Straight Binary Complementary Offset Binary
0xFFFF
Zero (0V)
Full-Scale (V
REF
or V
REF
/2)
0xFFFE
Zero + 1LSB
Full-Scale + 1LSB
:
:
:
0x7FFF
1/2 Full-Scale
Bipolar Zero
0x7FFE
1/2 Full-Scale + 1LSB
Bipolar Zero + 1LSB
:
:
:
0x0000
Full-Scale (V
REF
1LSB)
+Full-Scale (+V
REF
1LSB
or +V
REF
/2 1LSB)
DAC7742
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DAC RESET
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a LOW signal
on RST. Once RST is LOW, the DAC output will begin settling
to the mid-scale or min-scale code depending on the state of
the RSTSEL input. A HIGH value on RSTSEL will cause V
OUT
to reset to the mid-scale code (7FFF
H
) and a LOW value will
reset V
OUT
to min-scale (FFFF
H
). A change in the state of the
RSTSEL input while RST is LOW will cause a corresponding
change in the reset command selected internally and conse-
quently change the output value of V
OUT
of the DAC. Note that
a valid reset signal also resets the input register of the DAC to
the value specified by the state of RSTSEL.
GAIN AND OFFSET CALIBRATION
The architecture of the DAC7742 is designed in such a way
as to allow for easily configurable offset and gain calibration
using a minimum of external components. The DAC7742
has built-in feedback resistors and output amplifier summing
points brought out of the package in order to make the
absolute calibration possible. Figures 5 and 6 illustrate the
relationship of offset and gain adjustments for the DAC7742
in a unipolar configuration and in a bipolar configuration,
respectively.
When calibrating the DAC's output, offset should be adjusted
first to avoid 1st-order interaction of adjustments. In unipolar
mode, the DAC7742's offset is adjusted from code FFFF
H
and for either bipolar mode, offset adjustments are made at
code 7FFF
H
. Gain adjustment can then be made at code
0000
H
for each configuration, where the output of the DAC
should be at +10V for the 0V to +10V 1LSB or
10V output
range and +5V 1LSB for the
5V output range. Figure 7
shows the generalized external offset and gain adjustment
circuitry using potentiometers.
Digital Input
H
Input =
0000
H
Input =
FFFF
Gain Adjust
Rotates
the Line
1LSB
+ Full-Scale
Full Scale Range
Analog Output
(+V
REF
)
Zero Scale
(AGND)
Offset Adjust Translates the Line
Digital Input
Input =
FFFF
H
Gain
Adjust
Rotates
the Line
1LSB
Full-Scale
Range
+ Full-
Scale
Full-Scale
(V
REF
OR V
REF
/2)
Offset
Adjust
Translates
the Line
H
Input =
0000
Input = 7FFF
H
Analog Output
(+V
REF
or +V
REF
/2)
FIGURE 5. Relationship of Offset and Gain Adjustments for
V
OUT
= 0V to +10V Output Configuration.
FIGURE 6. Relationship of Offset and Gain Adjustments for
V
OUT
= 10V to +10V Output Configuration. (Same
Theory Applies for V
OUT
= 5V to +5V.)
FIGURE 7. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment.
NC
V
SS
V
CC
V
REF
R
OFFSET
AGND
AGND
RFB2
RFB1
SJ
V
OUT
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
Optional Gain
Adjust
(Other Connections Omitted
for Clarity)
REF
OUT
REFADJ
REF
IN
NC
Optional Offset
Adjust
R
POT1
R
S
V
OADJ
+
I
SJ
R
1
R
POT2
DAC7742
15
SBAS256
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When the DAC7742's internal reference is not used, gain
adjustments can be made via trimming the external refer-
ence applied to the DAC at REF
IN
. This can be accomplished
through using a potentiometer, unipolar DAC, or other means
of precision voltage adjustment to control the voltage pre-
sented to the DAC7742 by the external reference. Figure 9
and Table VI summarize the range of adjustment of the
internal reference via REFADJ.
FIGURE 8. Offset Adjustment Transfer Characteristic.
OFFSET ADJUSTMENT
Offset adjustment is accomplished by introducing a small
current into the summing junction (SJ) of the DAC7742. The
voltage at SJ, or V
SJ
, is dependent on the output configura-
tion of the DAC7742. Table IV shows the required pin
strapping for a given configuration and the nominal values of
V
SJ
for each output range.
REFERENCE
OUTPUT
PIN STRAPPING
V
SJ
(1)
CONFIGURATION CONFIGURATION R
OFFSET
RFB1
RFB2
Internal
0V to +10V
to V
REF
to V
OUT
to V
OUT
+5V
Reference
10V to +10V
NC
NC
to V
OUT
+3.333V
5V to +5V
to AGND to V
OUT
to V
OUT
+2.5V
External
0V to V
REF
to V
REF
to V
OUT
to V
OUT
V
REF
/2
Reference
V
REF
to V
REF
NC
NC
to V
OUT
V
REF
/3
V
REF
/2 to V
REF
/2
to AGND to V
OUT
to V
OUT
V
REF
/4
NOTE: (1) Voltage measured at V
SJ
for a given configuration.
TABLE IV. Nominal V
SJ
vs V
OUT
and Reference Configuration.
OUTPUT
R
POT2
R
1
R
S
I
SJ
NOMINAL
CONFIGURATION
RANGE
OFFSET
ADJUSTMENT
0V to +10V
10k
0
2.5M
2
A
25mV
10V to +10V
10k
5k
1.5M
2.2
A
55mV
5V to +5V
10k
10k
1.5M
1.7
A
21mV
TABLE V. Recommended External Component Values for
Symmetrical Offset Adjustment (V
REF
= 10V).
The current level required to adjust the DAC7742's offset can
be created by using a potentiometer divider, see Figure 7.
Another alternative is to use a unipolar DAC in order to apply
a voltage, V
OADJ
, to the resistor R
S
. A
1.2
A current range
applied to SJ will ensure offset adjustment coverage of the
0.1% maximum offset specification of the DAC7742.
When in a unipolar configuration (V
SJ
= 5V), only a single
resistor, R
S
, is needed for symmetrical offset adjustment with
a 0V to 10V V
OADJ
range. When in one of the two bipolar
configurations, V
SJ
is either +3.333v (
10V range) or +2.5V
(
5V range), and circuit values chosen to match those given
in Table V will provide symmetrical offset adjust. Please refer
to Figure 7 for component configuration.
OFFSET ADJUST RANGE
10V to +10V V
OUT
Configuration
min (75% of typ)
min (75% of typ)
typ
typ
50
25
0
25
50
Of
fset
Adjustment at V
OUT
(mV)
2
2
0
1
1
I
SJ
(
A)
0V to 10V and 5V to +5V
V
OUT
Configuration
Figure 8 illustrates the typical and minimum offset adjustment
ranges provided by forcing a current at SJ for a given output
voltage configuration.
GAIN ADJUSTMENT
When using the internal reference of the DAC7742, gain
adjustment is performed by adjusting the device's internal
reference voltage via the reference adjust pin, REFADJ.
The effect of a reference voltage change on the gain of the
DAC output can be seen in the generic equation (for
unipolar configuration):
V
V
N
OUT
REFIN
=
(
)




65535
65536
Where N is represented in decimal format and ranges from
0 to 65535.
REFADJ can be driven by a low impedance voltage source
such as a unipolar, 0V to +10V DAC or a potentiometer (less
than 100k
), see Figure 7. Since the input impedance of
REFADJ is typically 50k
, the smaller the resistance of the
potentiometer, the more linear the adjustment will be. A 10k
potentiometer is suggested if linearity of the reference adjust-
ment is of concern.
REF
OUT
ADJUST RANGE
40
30
20
10
0
10
20
30
40
REF
OUT
Adjustment
(mV)
0
2
4
6
8
10
REFADJ (V)
Typical REF
OUT
Adjustment Range
Minimum REF
OUT
Adjustment Range
FIGURE 9. Internal Reference Adjustment Transfer Charac-
teristic.
VOLTAGE AT REFADJ
REF
OUT
VOLTAGE
REFADJ = 0V
10V + 25mV (min)
REFADJ = 5V or NC
(1)
10V
REFADJ = 10V
10V 25mV (max)
NOTE: "NC" is "Not Connected".
TABLE VI. Minimum Internal Reference Adjustment Range.
DAC7742
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LAYOUT
A precision analog component requires careful layout, adequate
bypassing, and clean, well-regulated power supplies. The
DAC7742 offers separate digital and analog supplies, as it will
often be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more digital
logic present in the design and the higher the switching speed,
the more important it will become to separate the analog and
digital ground and supply planes at the device.
Since the DAC7742 has both analog and digital ground pins,
return currents can be better controlled and have less effect
on the DAC output error. Ideally, AGND would be connected
directly to an analog ground plane and DGND to the digital
ground plane. The analog ground plane would be separate
from the ground connection for the digital components until
they were connected at the power entry point of the system.
The voltages applied to V
CC
and V
SS
should be well regulated
and low noise. Switching power supplies and DC/DC con-
verters will often have high-frequency glitches or spikes
riding on the output voltage. In addition, digital components
can create similar high-frequency spikes as their internal
logic switches states. This noise can easily couple into the
DAC output voltage through various paths between the
power connections and analog output.
In addition, a 1
F to 10
F bypass capacitor in parallel with a
0.1
F bypass capacitor is strongly recommended for each
supply input. In some situations, additional bypassing may
be required, such as a 100
F electrolytic capacitor or even
a "Pi" filter made up of inductors and capacitorsall designed
to essentially low-pass filter the analog supplies, removing
any high frequency noise components.
NOISE PERFORMANCE
Increased noise performance of the DAC output can be
achieved by filtering the voltage reference input to the
DAC7742. Figure 10 shows a typical internal reference filter
schematic. A low-pass filter applied between the REF
OUT
and
REF
IN
pins can increase noise immunity at the DAC and
output amplifier. The REF
OUT
pin can source a maximum of
50
A so care should be taken in order to avoid overloading
the internal reference output
.
NC
V
SS
V
CC
1
2
3
43
44
45
46
47
48
(Other Connections
Omitted for Clarity)
RSTSEL
REFEN
REF
OUT
REFADJ
REF
IN
NC
100k
1
F
FIGURE 10. Internal Reference Filter.
DAC7742
17
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MTQF003A - OCTOBER 1994 - REVISED DECEMBER 1996
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
4040052 / C 11/96
0,13 NOM
0,17
0,27
25
24
SQ
12
13
36
37
6,80
7,20
1
48
5,50 TYP
0,25
0,45
0,75
0,05 MIN
SQ
9,20
8,80
1,35
1,45
1,60 MAX
Gage Plane
Seating Plane
0,10
0
5
7
5
0,50
M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
PACKAGE DRAWING
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
DAC7742Y/250
ACTIVE
LQFP
PT
48
250
DAC7742Y/2K
ACTIVE
LQFP
PT
48
2000
DAC7742YB/250
ACTIVE
LQFP
PT
48
250
DAC7742YB/2K
ACTIVE
LQFP
PT
48
2000
DAC7742YC/250
ACTIVE
LQFP
PT
48
250
DAC7742YC/2K
ACTIVE
LQFP
PT
48
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2004
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