DESCRIPTION

The DAC7800, DAC7801 and DAC7802 are members of a
new family of monolithic dual 12-bit CMOS multiplying Digi-
tal-to-Analog Converters (DACs). The digital interface speed
and the AC multiplying performance are achieved by using
an advanced CMOS process optimized for data conversion
circuits. High stability on-chip resistors provide true 12-bit
integral and differential linearity over the wide industrial
temperature range of 40

C to +85

DAC7800 features a serial interface capable of clocking-in
data at a rate of at least 10MHz. Serial data is clocked (edge
triggered) MSB first into a 24-bit shift register and then
latched into each DAC separately or simultaneously as
required by the application. An asynchronous CLEAR control
is provided for power-on reset or system calibration func-
tions. It is packaged in a 16-pin 0.3" wide plastic DIP.

DAC7801 has a 2-byte (8 + 4) double-buffered interface.
Data is first loaded (level transferred) into the input registers
in two steps for each DAC. Then both DACs are updated
simultaneously. DAC7801 features an asynchronous CLEAR
control. DAC7801 is packaged in a 24-pin 0.3" wide plastic
DIP.

DAC7802 has a single-buffered 12-bit data word interface.
Parallel data is loaded (edge triggered) into the single DAC
register for each DAC. DAC7802 is packaged in a 24-pin 0.3"
wide plastic DIP.

FEATURES

TWO DACs IN A 0.3" WIDE PACKAGE

SINGLE +5V SUPPLY

HIGH SPEED DIGITAL INTERFACE:

Serial--DAC7800
8 + 4-Bit Parallel--DAC7801
12-Bit Parallel--DAC7802

MONOTONIC OVER TEMPERATURE

LOW CROSSTALK: 94dB min

FULLY SPECIFIED OVER 40

C TO +85

APPLICATIONS

PROCESS CONTROL OUTPUTS

ATE PIN ELECTRONICS LEVEL SETTING

PROGRAMMABLE FILTERS

PROGRAMMABLE GAIN CIRCUITS

AUTO-CALIBRATION CIRCUITS

Dual Monolithic CMOS 12-Bit Multiplying

DIGITAL-TO-ANALOG CONVERTERS

Serial Interface

8-Bit Interface

8 Bits + 4 Bits

Serial

DAC7801

DAC7800

12-Bit MDAC

DAC A

FB B

OUT B

CLR

UPD

UPD A

UPD B

CLK

CLR

12-Bit MDAC

DAC B

12-Bit Interface

DAC7802

CSA

CSB

AGND B

REF B

FB A

OUT A

AGND A

REF A

DAC7800
DAC7801
DAC7802

SBAS005A DECEMBER 2001

www.ti.com

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DAC7800, 7801, 7802

SBAS005A

www.ti.com

SPECIFIED

RELATIVE

GAIN

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

ACCURACY

ERROR

PACKAGE-LEAD

DESIGNATOR

(1)

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

DAC7800KP

1LSB

3LSB

DIP-16

C to +85

DAC7800KP

Rails, 25

DAC7800LP

1/2 LSB

1LSB

DIP-16

DAC7800LP

Rails, 25

DAC7800KU

SO-16

C to +85

DAC7800KU DAC7800KU/1K Tape and Reel, 1000

DAC7800LU

SO-16

DAC7800LU

DAC7800LU/1K Tape and Reel, 1000

DAC7801KP

1LSB

3LSB

DIP-24

C to +85

DAC7801KP

Rails, 15

DAC7801LP

1/2 LSB

1LSB

DIP-24

DAC7801LP

Rails, 15

DAC7801KU

SO-24

C to +85

DAC7801KU DAC7801KU/1K Tape and Reel, 1000

DAC7801LU

SO-24

DAC7801LU

DAC7801LU/1K Tape and Reel, 1000

DAC7802KP

1LSB

3LSB

DIP-24

NTG

C to +85

DAC7802KP

Rails, 15

DAC7802LP

1/2 LSB

1LSB

DIP-24

NTG

DAC7802LP

Rails, 15

DAC7802KU

SO-24

C to +85

DAC7802KU DAC7802KU/1K Tape and Reel, 1000

DAC7802LU

SO-24

DAC7802LU

DAC7802LU/1K Tape and Reel, 1000

NOTE: (1 ) For the most current specifications and package information, refer to our web site at www.ti.com.

ELECTRICAL CHARACTERISTICS

At V

= +5VDC, V

REF A

= V

REF B

= +10V, T

= 40

C to +85

C, unless otherwise noted.

DAC7800, 7801, 7802K

DAC7800, 7801, 7802L

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ACCURACY
Resolution

Bits

Relative Accuracy

1/2

LSB

Differential Nonlinearity

LSB

Gain Error

Measured Using R

FB A

and R

FB B

LSB

All Registers Loaded with All 1s.

Gain Temperature Coefficient

(1)

ppm/

Output Leakage Current

= +25

0.005

= 40

C to +85

150

REFERENCE INPUT
Input Resistance

Input Resistance Match

0.5

DIGITAL INPUTS
V

(Input HIGH Voltage)

(Input LOW Voltage)

0.8

(Input Current)

= +25

= 40

C to +85

(Input Capacitance)

0.8

POWER SUPPLY
V

4.5

5.5

0.2

Power-Supply Rejection

from 4.5V to 5.5V

0.002

%/%

Same specification as for DAC7800, 7801, 7802K.

to AGND .................................................................................. 0V, +7V

to DGND .................................................................................. 0V, +7V

AGND to DGND .......................................................................... 0.3, V

Digital Input to DGND ........................................................ 0.3, V

+ 0.3

REF A

, V

REF B

to AGND .....................................................................

16V

REF A

, V

REF B

to DGND .....................................................................

16V

OUT A

, I

OUT B

to AGND ................................................................. 0.3, V

Storage Temperature Range ........................................... 55

C to +125

Operating Temperature Range ......................................... 40

C to +85

Lead Temperature (soldering, 10s) ................................................. +300

Junction Temperature ...................................................................... +175

ABSOLUTE MAXIMUM RATINGS

At T

= +25

C, unless otherwise noted.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION

DAC7800, 7801, 7802

SBAS005A

www.ti.com

AC PERFORMANCE

OUTPUT OP AMP IS OPA602.
At V

= +5VDC, V

REF A

= V

REF B

= +10V, T

= +25

C, unless otherwise noted. These specifications are fully characterized but not subject to test.

NOTE: (1) Ensured but not tested.

DAC7800, 7801, 7802K

DAC7800, 7801, 7802L

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

OUTPUT CURRENT SETTLING TIME

To 0.01% of Full-Scale

0.4

0.8

= 100

, C

= 13pF

DIGITAL-TO-ANALOG GLITCH IMPULSE

REF A

= V

REF B

= 0V

0.9

nV-s

= 100

, C

= 13pF

AC FEEDTHROUGH

VREF

= 10kHz

OUTPUT CAPACITANCE

DAC Loaded with All 0s

DAC Loaded with All 1s

100

CHANNEL-TO-CHANNEL ISOLATION
V

REF A

to I

OUT B

VREF A

= 10kHz

REF B

= 0V,

Both DACs Loaded with 1s

REF B

to I

OUT A

VREF B

= 10kHz

101

REF A

= 0V,

Both DACs Loaded with 1s

DIGITAL CROSSTALK

Full-Scale Transition

0.9

nV-s

= 100

, C

= 13pF

Same specification as for DAC7800, 7801, and 7802K.

DAC7800

BLOCK DIAGRAM

DAC A

DAC B

DAC A Register

UPD B

AGND B

AGND A

UPD A

OUT B

FB B

REF B

REF A

FB A

OUT A

DGND

DAC B Register

Bit 0

Bit 11

Bit 12

Bit 23

Control Logic and Shift Register

CLR

DAC7800

Data

CLK

PIN CONFIGURATION

AGND A

CLK

UPD A

Data In

AGND B

CLR

UPD B

DGND

OUT A

FB A

REF A

OUT B

DAC7800

FB B

REF B

CLK

UPD A

UPD B

CLR

FUNCTION

All register contents set to 0's (asynchronous).

No data transfer.

Input data is clocked into input register (location Bit 23) and previous data shifts.

Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A.

Input register bits 11 (LSB) - 0 (MSB) are loaded into DAC B.

Input register bits 23 (LSB) - 12 (MSB) are loaded into DAC A, and input register bits 11 (LSB) - 0 (MSB)
are loaded into DAC B.

X = Don't care.

means falling edge triggered.

LOGIC TRUTH TABLE

Top View

DIP

DAC7800, 7801, 7802

SBAS005A

www.ti.com

DATA

CLK

UPD A
UPD B

CLR

5V
0V

NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns.

(2) Timing measurement reference level is V + V

PARAMETER

MINIMUM

-- Data Setup Time

15ns

-- Data Hold Time

15ns

-- Chip Select to CLK,

15ns

Update, Data Setup Time

-- Chip Select to CLK,

40ns

Update, Data Hold Time

-- CLK Pulse Width

40ns

-- Clear Pulse Width

40ns

-- Update Pulse Width

40ns

-- CLK Edge to UPD A

15ns

or UPD B

TIMING CHARACTERISTICS

= +5V, V

REF A

= V

REF B

= +10V, T

= 40

C to +85

Data In

Bit 0

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

DAC A

MSB
DAC A

LSB

DAC B

MSB

DAC B

DAC7800 Data Input Sequence

DAC7800 Digital Interface Block Diagram

24-Bit

Shift Register

DAC A Register

UPD A

Data In

CLK

UPD B

LSB

MSB

DAC B Register

LSB

MSB

Bit
23

Bit
12

Bit
11

Bit

CLK

DATA INPUT FORMAT

DAC7800

(Cont.)

DAC7800, 7801, 7802

SBAS005A

www.ti.com

LOGIC TRUTH TABLE

BLOCK DIAGRAM

PIN CONFIGURATION

AGND A

DB0

DB1

DB2

DB3

DB4

DB5

DGND

AGND B

UPD

CLR

DB7

DB6

OUT A

FB A

REF A

FB B

REF B

OUT B

DAC7801

CLR

UPD

FUNCTION

No Data Transfer

All Registers Cleared

DAC A LS Input Register Loaded with DB7 - DB0 (LSB)

DAC A MS Input Register Loaded with DB3 (MSB) - DB0

DAC B LS Input Register Loaded with DB7 - DB0 (LSB)

DAC B MS Input Register Loaded with DB3 (MSB) - DB0

DAC A, DAC B Registers Updated Simultaneously from Input Registers

DAC A, DAC B Registers are Transparent

X = Don't care.

TIMING CHARACTERISTICS

= +5V, V

REF A

= V

REF B

= +10V, T

= 40

C to +85

PARAMETER

MINIMUM

-- Address Valid to Write Setup Time

10ns

-- Address Valid to Write Hold Time

10ns

-- Data Setup Time

30ns

-- Data Hold Time

10ns

-- Chip Select or Update to Write Setup Time

0ns

-- Chip Select or Update to Write Hold Time

0ns

-- Write Pulse Width

40ns

-- Clear Pulse Width

40ns

A0A1

CLR

CS, UPD

DATA

5V
0V

NOTES: (1) All input signal rise and fall times are measured from 10% to 90%

of +5V. t

= t

= 5ns. (2) Timing measurement reference level is .

+ V

DAC A

AGND A

AGND B

OUT A

FB A

REF A

REF B

FB B

OUT B

DAC A Register

DAC A

Input

Reg

DAC A

Input

Reg

Control Logic

DAC B

DAC B Register

DGND

DAC B

Input

Reg

DAC B

Input

Reg

UPD

CLR

DAC7801

DB7DB0

Top View

DIP

DAC7800, 7801, 7802

SBAS005A

www.ti.com

BLOCK DIAGRAM

AGND

CS A

(LSB) DB0

DB1

DB2

DB3

DB4

DB5

DGND

CS B

DB11 (MSB)

DB10

DB9

DB8

DB7

DB6

OUT A

FB A

REF A

FB B

REF B

OUT B

DAC7802

TIMING CHARACTERISTICS

At V

= +5V, and T

= 40

C to +85

PARAMETER

MINIMUM

- Data Setup Time

20ns

- Data Hold Time

15ns

- Chip Select to Write Setup Time

30ns

- Chip Select to Write Hold Time

0ns

- Write Pulse Width

30ns

LOGIC TRUTH TABLE

CSA

CSB

FUNCTION

No Data Transfer

A Rising Edge on CSA or CSB Loads
Data to the Respective DAC

DAC A Register Loaded from Data Bus

DAC B Register Loaded from Data Bus

DAC A and DAC B Registers Loaded
from Data Bus

X = Don't care.

means rising edge triggered.

PIN CONFIGURATION

DAC7802

DATA

5V
0V

CSA, CSB

NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. t

= t

= 5ns. (2) Timing measurement reference level

+ V

DAC B

DAC A

DGND

CS A

CS B

DAC7802

2 I

3 R

OUT A

FB A

23 R

24 I

1 AGND

FB B

OUT B

DAC A Register

DAC B Register

DB11DB0

REF A

REF B

Top View

DIP

DAC7800, 7801, 7802

SBAS005A

www.ti.com

TYPICAL CHARACTERISTICS

OUTPUT OP AMP IS OPA602.
T

= +25

C, V

= +5V.

Output Leakage Current (A)

OUTPUT LEAKAGE CURRENT

vs TEMPERATURE

1µ

100n

10n

100p

10p

+25

+50

+75

+100

+125

Temperature (°C)

100

THD + Noise (dB)

THD + NOISE vs FREQUENCY

Frequency (Hz)

100

10k

100k

1Vrms

3Vrms

6Vrms

100

110

120

Crosstalk (dB)

CHANNEL-TO-CHANNEL ISOLATION

vs FREQUENCY

Frequency (Hz)

100k

10k

10M

100

Feedthrough (dB)

FEEDTHROUGH vs FREQUENCY

Frequency (Hz)

100k

10k

10M

+30

+20

+10

Gain (dB)

FREQUENCY RESPONSE

Frequency (Hz)

100k

10k

10M

= 5pF

= 10pF

= 0pF

Frequency (Hz)

PSRR (dB)

PSRR vs FREQUENCY

10k

100k

DAC Loaded w/0s

DAC Loaded w/1s

DAC7800, 7801, 7802

SBAS005A

www.ti.com

DISCUSSION OF
SPECIFICATIONS

RELATIVE ACCURACY

This term, also known as end point linearity or integral
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation
from a straight line, after zero and full-scale errors have been
adjusted to zero.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB.
A differential nonlinearity specification of 1LSB maximum
ensures monotonicity.

GAIN ERROR

Gain error is the difference between the full-scale DAC output
and the ideal value. The ideal full scale output value for the
DAC780x is (4095/4096)V

REF

. Gain error may be adjusted

to zero using external trims, see Figures 5 and 7.

OUTPUT LEAKAGE CURRENT

The current which appears at I

OUT A

and I

OUT B

with the DAC

loaded with all zeros.

OUTPUT CAPACITANCE

The parasitic capacitance measured from I

OUT A

or I

OUT B

AGND.

CHANNEL-TO-CHANNEL ISOLATION

The AC output error due to capacitive coupling from DAC A
to DAC B or DAC B to DAC A.

MULTIPLYING FEEDTHROUGH ERROR

The AC output error due to capacitive coupling from V

REF

OUT

with the DAC loaded with all zeros.

OUTPUT CURRENT SETTLING TIME

The time required for the output current to settle to within
+0.01% of final value for a full-scale step.

DIGITAL-TO-ANALOG GLITCH ENERGY

The integrated area of the glitch pulse measured in nanovolt-
seconds. The key contributor to DAC glitch is charge injected
by digital logic switching transients.

DIGITAL CROSSTALK

Glitch impulse measured at the output of one DAC but caused
by a full-scale transition on the other DAC. The integrated
area of the glitch pulse is measured in nanovolt-seconds.

CIRCUIT DESCRIPTION

Figure 1 shows a simplified schematic of one half of a DAC780x.
The current from the V

REF

pin is switched between I

OUT A

and

AGND by 12 single-pole double-throw CMOS switches. This
maintains a constant current in each leg of the ladder regard-
less of the input code. The input resistance at V

REF

is therefore

A CMOS switch transistor, included in series with the ladder
terminating resistor and in series with the feedback resistor,
R

FB A

, compensates for the temperature drift of the ON resis-

tance of the ladder switches.

Figure 2 shows an equivalent circuit for DAC A. C

OUT

is the

output capacitance due to the N-channel switches and varies
from about 30pF to 70pF with digital input code. The current
source I

LKG

is the combination of surface and junction leak-

ages to the substrate. I

LKG

approximately doubles every 10

is the equivalent output resistance of the DAC and it varies

with input code.

constant and can be driven by either a voltage or current, AC
or DC, positive or negative polarity, and have a voltage range
up to

20V.

OUT A

AGND

FB A

REF A

DB11

(MSB)

DB10

DB9

DB0

(LSB)

FIGURE 1. Simplified Circuit Diagram for DAC A.

FIGURE 2. Equivalent Circuit for DAC A.

FB A

OUT A

REF A

LKG

OUT

AGND A

4096

REF

INSTALLATION

ESD PROTECTION

All digital inputs of the DAC780x incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
2.5kV (using the Human Body Model, 100pF and 1500

However, industry standard ESD protection methods should
be used when handling or storing these components. When
not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destina-
tion socket potential before devices are removed.

POWER-SUPPLY CONNECTIONS

The DAC780x are designed to operate on V

= +5V +10%.

For optimum performance and noise rejection, power-supply
decoupling capacitors C

should be added as shown in the

application circuits. These capacitors (1

F tantalum recom-

mended) should be located close to the DAC. AGND and

DAC7800, 7801, 7802

SBAS005A

www.ti.com

DGND should be connected together at one point only,
preferably at the power-supply ground point. Separate re-
turns minimize current flow in low-level signal paths if properly
connected. Output op amp analog common (+ input) should
be connected as near to the AGND pins of the DAC780x as
possible.

WIRING PRECAUTIONS

To minimize AC feedthrough when designing a PC board,
care should be taken to minimize capacitive coupling be-
tween the V

REF

lines and the I

OUT

lines. Similarly, capacitive

coupling between DACs may compromise the channel-to-
channel isolation. Coupling from any of the digital control or
data lines might degrade the glitch and digital crosstalk
performance. Solder the DAC780x directly into the PC board
without a socket. Sockets add parasitic capacitance (which
can degrade AC performance).

AMPLIFIER OFFSET VOLTAGE

The output amplifier used with the DAC780x should have low
input offset voltage to preserve the transfer function linearity.
The voltage output of the amplifier has an error component
which is the offset voltage of the op amp multiplied by
the "noise gain" of the circuit. This "noise gain" is equal to
(R

/ R

+ 1) where R

is the output impedance of the DAC

OUT

terminal and R

is the feedback network impedance. The

nonlinearity occurs due to the output impedance varying with
code. If the 0 code case is excluded (where R

= infinity), the

will vary from R-3R providing a "noise gain" variation

between 4/3 and 2. In addition, the variation of R

is nonlinear

with code, and the largest steps in R

occur at major code

transitions where the worst differential nonlinearity is also
likely to be experienced. The nonlinearity seen at the amplifier
output is 2V

/ 3 = 2V

/3. Thus, to maintain good

nonlinearity the op amp offset should be much less than
1/2 LSB.

UNIPOLAR CONFIGURATION

Figure 3 shows DAC780x in a typical unipolar (two-quadrant)
multiplying configuration. The analog output values versus
digital input code are listed in Table II. The operational
amplifiers used in this circuit can be single amplifiers such as
the OPA602, or a dual amplifier such as the OPA2107. C1
and C2 provide phase compensation to minimize settling time
and overshoot when using a high speed operational amplifier.

If an application requires the DAC to have zero gain error, the
circuit shown in Figure 4 may be used. Resistors R

and R

induce a positive gain error greater than worst-case initial
negative gain error. Trim resistors R

and R

provide a

variable negative gain error and have sufficient trim range to
correct for the worst-case initial positive gain error plus the
error produced by R

and R

BIPOLAR CONFIGURATION

See Figure 5 for the DAC780x in a typical bipolar (four-
quadrant) multiplying configuration. See Table III for the
listing of the analog output values versus digital input code.

DATA INPUT

ANALOG OUTPUT

MSB

LSB

1111 1111 1111

REF

(4095/4096)

1000 0000 0000

REF

(2048/4096) = 1/2V

REF

0000 0000 0001

REF

(1/4096)

0000 0000 0000

0 Volts

TABLE II. Unipolar Output Code.

The operational amplifiers used in this circuit can be single
amplifiers such as the OPA602, a dual amplifier such as the
OPA2107, or a quad amplifier like the OPA404. C1 and C2
provide phase compensation to minimize settling time and
overshoot when using a high speed operational amplifier. The
bipolar offset resistors R

and R

should be ratio-

matched to 0.01% to ensure the specified gain error perfor-
mance.

DAC A

OUT A

DAC B

AGND A

OUT B

FB B

FB A

C1
10pF

C2
10pF

DAC780X

OUT A

OUT B

DGND

REF B

REF A

+5V

A1, A2 OPA602 or 1/2 OPA2107.
DAC7802 has a single analog
common, AGND.

1µF

AGND B

R
100

REF B

DAC A

OUT A

DAC B

AGND A

OUT B

FB B

FB A

C1 10pF

C2 10pF

DAC780X

OUT A

OUT B

DGND

+5V

A1, A2 OPA602 or 1/2 OPA2107.
DAC7802 has a single analog
common, AGND.

1µF

AGND B

IN A

R
100

REF A

IN B

FIGURE 4. Unipolar Configuration with Gain Trim.

FIGURE 3. Unipolar Configuration.

DAC7800, 7801, 7802

SBAS005A

www.ti.com

If an application requires the DAC to have zero gain error, the
circuit may be used, see Figure 6. Resistors R

and R

induce

a positive gain error greater than worst-case initial negative
gain error. Trim resistors R

and R

provide a variable

negative gain error and have sufficient trim range to correct
for the worst-case initial positive gain error plus the error
produced by R

and R

DATA INPUT

ANALOG OUTPUT

MSB

LSB

1111 1111 1111

REF

(2047/2048)

1000 0000 0001

REF

(1/2048)

1000 0000 0000

0 Volts

0111 1111 1111

REF

(1/2048)

0000 0000 0000

REF

(2048/2048)

TABLE III. Bipolar Output Code.

FIGURE 5. Bipolar Configuration.

10k

C
10pF

DAC A

DAC B

R
10k

DAC780X

DGND

REF A

+5V

20k

R
10k

C
10pF

OUT A

OUT B

DAC7802 has a single analog common, AGND.
A1A4, OPA602 or 1/2 OPA2107.

20k

REF B

OUT B

FB B

AGND B

OUT A

FB A

AGND A

1µF

APPLICATIONS

12-BIT PLUS SIGN DACS

For a bipolar DAC with 13 bits of resolution, two solutions are
possible. The addition of a precision difference amplifier and
a high speed JFET switch provides a 12-bit plus sign voltage-
output DAC, see Figure 7. When the switch selects the op
amp output, the difference amplifier serves as a noninverting
output buffer. If the analog ground side of the switch is
selected, the output of the difference amplifier is inverted.

Another option, see Figure 8, also produces a 12-bit plus sign
output without the additional switch and digital control line.

DIGITALLY PROGRAMMABLE ACTIVE FILTER

See Figure 9 for the DAC780x in a digitally programmable
active filter application. The design is based on the state-
variable filter, Texas Instruments UAF42, an active filter topol-
ogy that offers stable and repeatable filter characteristics.

DAC1 and DAC2 can be updated in parallel with a single word
to set the center frequency of the filter. DAC 4, which makes
use of the uncommitted op amp in UAF42, sets the Q of the
filter. DAC3 sets the gain of the filter transfer function without
changing the Q of the filter. The reverse is also true.

The center frequency is determined by f

= 1/2

RC where R is

the ladder resistance of the DAC (typical value, 10k

) and C

the internal capacitor value (1000pF) of the UAF42. External
capacitors can be added to lower the center frequency of the
filter. But the highest center frequency for this circuit will be
about 16kHz because the effective series resistance of the
DAC cannot be less than 10k

Note that the ladder resistance of the DAC may vary from
device to device. Thus, for best tracking, DAC2 and DAC3
should be in the same package. Some calibration may be
necessary from one filter to another.

DAC7800, 7801, 7802

SBAS005A

www.ti.com

PACKAGE DRAWINGS

MPDI002B JANUARY 1995 REVISED FEBRUARY 2000

N (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

0.325 (8,26)
0.300 (7,62)

0.010 (0,25) NOM

Gauge Plane

0.015 (0,38)

0.430 (10,92) MAX

0.975

(24,77)

0.940

(23,88)

0.920

0.850

0.775

0.745

(19,69)

(18,92)

0.775

(19,69)

(18,92)

0.745

A MIN

DIM

A MAX

PINS **

(23,37)

(21,59)

Seating Plane

14/18 PIN ONLY

4040049/D 02/00

0.070 (1,78) MAX

0.035 (0,89) MAX

0.020 (0,51) MIN

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

0.010 (0,25)

0.100 (2,54)

16 PINS SHOWN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).

DAC7800, 7801, 7802

SBAS005A

www.ti.com

PACKAGE DRAWINGS (Cont)

MSOI003E JANUARY 1995 REVISED SEPTEMBER 2001

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

4040000 / E 08/01

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

0.012 (0,30)

0.004 (0,10)

0.020 (0,51)

0.014 (0,35)

0.291 (7,39)

0.299 (7,59)

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

0.600

0.610

(17,78)

0.700

(18,03)

0.710

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

0 ñ8

(11,51)

(11,73)

0.453

0.462

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

DAC7800, 7801, 7802

SBAS005A

www.ti.com

PACKAGE DRAWINGS (Cont)

MPDI066 AUGUST 2001

NTG (R-PDIP-T24)

PLASTIC DUAL-IN-LINE

4202642/A 08/01

0.150 (3,81)

0.115 (2,92)

C

0.005 (0,13) MIN
1/2 Lead 4 PL

1.195 (30,35)

1.160 (29,46)

0.240 (6,10)

0.280 (7,11)

0.070 (1,78)

0.045 (1,14)

0.030 (0,76)

0.045 (1,14)

0.014 (0,36)

0.022 (0,56)

0.010 (0,25) M

0.210 (5,33)

0.195 (4,95)

0.115 (2,92)

0.300 (7,62)

MAX

0.430 (10,92)

0.000 (0,00)

0.060 (1,52)

0.014 (0,36)

0.008 (0,20)

0.325 (8,26)

0.300 (7,62)

Index
Area

0.015 (0,38)
MIN

0.100 (2,54)

Seating Plane

Base Plane

MAX

4 PL

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Dimensions are measured with the package

seated in JEDEC seating plane gauge GS-3.

D. Dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 (0,25).

E. Dimensions measured with the leads constrained to be

perpendicular to Datum C.

F. Dimensions are measured at the lead tips with the

leads unconstrained.

G. Pointed or rounded lead tips are preferred to ease

insertion.

H. Maximum dimensions do not include dambar

protrusions. Dambar protrusions shall not exceed
0.010 (0,25).

I. Distance between leads including dambar protrusions

to be 0.005 (0,13) minumum.

J. A visual index feature must be located within the

crosshatched area.

K. For automatic insertion, any raised irregularity on the

top surface (step, mesa, etc.) shall be symmetrical
about the lateral and longitudinal package centerlines.

L. Controlling dimension in inches.

M. Falls within JEDEC MS-011-AB.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding thirdparty products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

2001, Texas Instruments Incorporated

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC7801LU

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC7801LU