DAC7821
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FEATURES
DESCRIPTION
APPLICATIONS
DAC Register
Power-On
Reset
Control
Logic
DAC7821
R
R
FB
V
REF
V
DD
I
1
OUT
I
2
OUT
GND
DB0
DB11
12-Bit
R-2R DAC
Input Latch
Parallel Bus
CS
R/W
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
12-Bit, Parallel Input, Multiplying
Digital-to-Analog Converter
2.5 V to 5.5 V Supply Operation
The DAC7821 is a CMOS 12-bit current output
digital-to-analog
converter
(DAC).
This
device
Fast Parallel Interface:
operates from a single 2.5 V to 5.5 V power supply,
17ns Write Cycle
making it suitable to battery-powered and many other
Update Rate of 20.4 MSPS
applications.
10 MHz Multiplying Bandwidth
This DAC operates with a fast parallel interface. Data
10 V Reference Input
readback allows the user to read the contents of the
Low Glitch Energy: 5 nV-s
DAC register via the DB pins. On power-up, the
internal register and latches are filled with zeroes and
Extended Temperature Range:
the DAC outputs are at zero scale.
40
C to +125
C
The
DAC7821
offers
excellent
4-quadrant
20-Lead QFN and 20-Lead TSSOP Packages
multiplication
characteristics,
with
large
signal
12-Bit Monotonic
multiplying bandwidth of 10 MHz. The applied
1 LSB INL
external reference input voltage (V
REF
) determines
4-Quadrant Multiplication
the full-scale output current. An integrated feedback
resistor (R
FB
) provides temperature tracking and
Power-On Reset with Brownout Detection
full-scale voltage output when combined with an
Readback Function
external current-to-voltage precision amplifier.
Industry-Standard Pin Configuration
The DAC7821 is available in a 20-lead TSSOP
package as well as a small 20-lead QFN package
(available Q2 2006).
Portable Battery-Powered Instruments
Waveform Generators
Analog Processing
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 20052006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT MEDIA,
PRODUCT
PACKAGE
DESIGNATOR
RANGE
MARKING
NUMBER
QUANTITY
DAC7821IPW
70, Tube
DAC7821
20-TSSOP
PW
40
C to +125
C
DAC7821
DAC7821IPWR
2000, Tape and Reel
DAC7821IRGPT
250, Tape and Reel
DAC7821
20-QFN
(2)
RGP
40
C to +125
C
DAC7821
DAC7821IRGPR
3000, Tape and Reel
(1)
For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at
www.ti.com
.
(2)
Available 2Q 2006.
over operating free-air temperature range (unless otherwise noted)
(1)
DAC7821
UNIT
V
DD
to GND
0.3 to +7.0
V
Digital input voltage to GND
0.3 to V
DD
+ 0.3
V
V
OUT
to GND
0.3 to V
DD
+ 0.3
V
Operating temperature range
40 to +125
C
Storage temperature range
65 to +150
C
Junction temperature (T
J
max)
+150
C
ESD Rating, HBM
3000
V
ESD Rating, CDM
1000
V
(1)
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2
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ELECTRICAL CHARACTERISTICS
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
V
DD
= +2.5 V to +5.5 V; I
OUT
1 = Virtual GND; I
OUT
2 = 0V; V
REF
= +10 V; T
A
= full operating temperature. All specifications
40
C to +125
C, unless otherwise noted.
DAC7821
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
12
Bits
Relative accuracy
1
LSB
Differential nonlinearity
1
LSB
Output leakage current
Data = 000h, T
A
= +25
C
10
nA
Output leakage current
Data = 000h, T
A
= T
MAX
20
nA
Full-scale gain error
All ones loaded to DAC register
5
10
mV
Full-scale tempco
5
ppm/
C
Output capacitance
Code dependent
30
pF
REFERENCE INPUT
V
REF
range
15
15
V
Input resistance
8
10
12
k
R
FB
resistance
8
10
12
k
LOGIC INPUTS AND OUTPUT
(1)
Input low voltage
V
IL
V
DD
= +2.7V
0.6
V
V
IL
V
DD
= +5V
0.8
V
Input high voltage
V
IH
V
DD
= +2.7V
2.1
V
V
IH
V
DD
= +5V
2.4
V
Input leakage current
I
IL
10
A
Input capacitance
C
IL
10
pF
POWER REQUIREMENTS
V
DD
2.7
5.5
V
I
DD
(normal operation)
Logic inputs = 0 V
5
A
V
DD
= +4.5 V to +5.5 V
V
IH
= V
DD
and V
IL
= GND
0.8
5
A
V
DD
= +2.5 V to +3.6 V
V
IH
= V
DD
and V
IL
= GND
0.4
2.5
A
AC CHARACTERISTICS
Output voltage settling time
0.2
s
Reference multiplying BW
V
REF
= 7 V
PP
, Data = FFFh
10
MHz
V
REF
= 0 V to 10 V,
DAC glitch impulse
5
nV-s
Data = 7FFh to 800h to 7FFh
Feedthrough error V
OUT
/V
REF
Data = 000h, V
REF
= 100kHz
70
dB
Digital feedthrough
2
nV-s
Total harmonic distortion
105
dB
Output spot noise voltage
18
nV/
Hz
(1)
Specified by design and characterization; not production tested.
3
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DATA VALID
DATA VALID
R/W
CS
DATA
t
1
t
2
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
TIMING REQUIREMENTS: 2.5 V to 4.5 V
TIMING REQUIREMENTS: 4.5 V to 5.5 V
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
TIMING INFORMATION
At t
r
= t
f
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2; V
DD
= +2.5 V to +4.5 V, V
REF
= +10 V,
I
OUT
2 = 0 V. All specifications 40
C to +125
C, unless otherwise noted.
DAC7821
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
1
R/W to CS setup time
0
ns
t
2
R/W to CS hold time
0
ns
t
3
CS low time (write cycle)
10
ns
t
4
Data setup time
6
ns
t
5
Data hold time
0
ns
t
6
R/W high to CS low
5
ns
t
7
CS min high time
9
ns
t
8
Data access time
20
40
ns
t
9
Bus relinquish time
5
10
ns
(1)
Ensured by design; not production tested.
At t
r
= t
f
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2; V
DD
= +4.5 V to +5.5 V, V
REF
= +10 V,
I
OUT
2 = 0 V. All specifications 40
C to +125
C, unless otherwise noted.
DAC7821
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
1
R/W to CS setup time
0
ns
t
2
R/W to CS hold time
0
ns
t
3
CS low time (write cycle)
10
ns
t
4
Data setup time
6
ns
t
5
Data hold time
0
ns
t
6
R/W high to CS low
5
ns
t
7
CS min high time
7
ns
t
8
Data access time
10
20
ns
t
9
Bus relinquish time
5
10
ns
(1)
Ensured by design; not production tested.
4
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DEVICE INFORMATION
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB0 (LSB)
DB1
DB2
DB3
DB4
DAC7821
TSSOP-20
I
1
OUT
R
FB
V
REF
V
DD
I
2
OUT
R/W
CS
QFN-20
(1)
GND
DB11
DB10
DB9
DB8
DB0
DB1
DB2
DAC7821
1
2
3
4
5
15
14
13
12
11
R/W
CS
DB7
DB6
DB5
DB4
DB3
I
2
O
U
T
I
1
O
U
T
R
F
B
V
R
EF
V
D
D
20
19
18
17
16
6
7
8
9
10
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
(1)
QFN-20 package available 2Q 2006.
TERMINAL FUNCTIONS
TERMINAL
TSSOP
QFN
NO.
NO.
NAME
DESCRIPTION
1
19
I
OUT
1
DAC current output.
2
20
I
OUT
2
DAC analog ground. This pin is normally tied to the analog ground of the system.
3
1
GND
Ground pin.
415
213
DB11 DB0
Parallel data bits 11 to 0.
Chip select input. Active low. Used in conjunction with R/W to load parallel data to the input
16
14
CS
latch or read data from the DAC register. Rising edge of CS loads data.
Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with
17
15
R/W
CS to read back contents of DAC register.
18
16
V
DD
Positive power supply input. These parts can be operated from a supply of 2.5 V to 5.5 V.
19
17
V
REF
DAC reference voltage input.
DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external
20
18
R
FB
amplifier output.
5
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TYPICAL CHARACTERISTICS: V
DD
= +5 V
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
INL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = +25 C
A
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
DNL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = +25 C
A
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
INL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = 40 C
A
-
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
DNL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = 40 C
A
-
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
INL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = +125 C
A
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
DNL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = +125 C
A
V
= 10 V
REF
+
Digital Input Code
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
At T
A
= +25
C, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 1.
Figure 2.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 3.
Figure 4.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 5.
Figure 6.
6
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3.0
2.5
2.0
1.5
1.0
0.5
0
Supply Current (mA)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Logic Input Voltage (V)
V
= 2.5 V
DD
V
= 3.0 V
DD
V
= 5.0 V
DD
6
0
6
12
18
24
30
36
42
48
56
60
66
72
78
84
90
96
102
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0xFFF
0x800
0x400
0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
Attenuation (dB)
10
100
1k
10k
100k
1M
10M
100M
Bandwidth (Hz)
0x000
Output V
oltage (50mV/div)
Code 2047 to 2048
DAC Update
Time (50ns/div)
Time (50ns/div)
Output V
oltage (50mV/div)
Code 2048 to 2047
DAC Update
Time (20 ns/div)
Output V
oltage (%)
Small Signal Settling
DAC Update
10
90
V
= I
x 100 W
OUT
OUT
Gain Error (mV)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-2.0
-
-
-
-
-
-
-
-
-
-
-40
-20
0
20
40
60
80
100
120
Temperature ( C)
V
= +10 V
REF
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)
At T
A
= +25
C, unless otherwise noted.
SUPPLY CURRENT
REFERENCE MULTIPLYING BANDWIDTH
vs LOGIC INPUT VOLTAGE
Figure 7.
Figure 8.
MIDSCALE DAC GLITCH
MIDSCALE DAC GLITCH
Figure 9.
Figure 10.
DAC SETTLING TIME
GAIN ERROR
vs TEMPERATURE
Figure 11.
Figure 12.
7
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2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Quiescent Current (
A)
m
-40
-20
0
20
40
60
80
100
120
Temperature ( C)
V
= +10 V
REF
V
= +2.5 V
DD
V
= +5.0 V
DD
Leakage Current (nA)
0.2
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
-40
-20
0
20
40
60
80
100
120
Temperature ( C)
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: V
DD
= +5 V (continued)
At T
A
= +25
C, unless otherwise noted.
SUPPLY CURRENT
LEAKAGE CURRENT
vs TEMPERATURE
vs TEMPERATURE
Figure 13.
Figure 14.
8
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TYPICAL CHARACTERISTICS: V
DD
= +2.5 V
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
INL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = +25 C
A
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
DNL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = +25 C
A
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
INL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = 40 C
A
-
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
DNL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = 40 C
A
-
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
INL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = +125 C
A
V
= 10 V
REF
+
Digital Input Code
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
-
-
-
-
-
DNL (LSB)
0
512
1024
1536
2048
2560
3072
3584
4095
T = +125 C
A
V
= 10 V
REF
+
Digital Input Code
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
At T
A
= +25
C, unless otherwise noted.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 15.
Figure 16.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 17.
Figure 18.
LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
vs DIGITAL INPUT CODE
Figure 19.
Figure 20.
9
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Output V
oltage (50mV/div)
Code 2047 to 2048
DAC Update
Time (50ns/div)
Output V
oltage (50mV/div)
Code 2048 to 2047
DAC Update
Time (50ns/div)
Gain Error (mV)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100
120
Temperature ( C)
V
= +10 V
REF
Leakage Current (nA)
0.2
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
-40
-20
0
20
40
60
80
100
120
Temperature ( C)
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS: V
DD
= +2.5 V (continued)
At T
A
= +25
C, unless otherwise noted.
MIDSCALE DAC GLITCH
MIDSCALE DAC GLITCH
Figure 21.
Figure 22.
GAIN ERROR
LEAKAGE CURRENT
vs TEMPERATURE
vs TEMPERATURE
Figure 23.
Figure 24.
10
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THEORY OF OPERATION
R
R
R
R
2R
2R
2R
2R
2R
DB0
(LSB)
DB9
DB10
DB11
(MSB)
I
1
OUT
R
FB
V
REF
I
2
OUT
)(
V
OUT
+ )
V
REF
CODE
4096
(1)
OPA277
DAC7821
15V
V+
V-
-15V
GND
I
1
OUT
R
FB
V
REF
V
DD
V
DD
V
OUT
I
2
OUT
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
The DAC7821 is a single channel current output, 12-bit digital-to-analog converter (DAC). The architecture,
illustrated in
Figure 25
, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to I
OUT
1 or the I
OUT
2 terminal. The I
OUT
1 terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input V
REF
that determines the DAC full-scale current. The R-2R ladder presents a code-independent load
impedance to the external reference of 10 k
20%. The external reference voltage can vary over a range of
15 V to +15 V, thus providing bipolar I
OUT
current operation. By using an external I/V converter and the
DAC7821 R
FB
resistor, output voltage ranges of V
REF
to V
REF
can be generated.
Figure 25. Equivalent R-2R DAC Circuit
When using an external I/V converter and the DAC7821 R
FB
resistor, the DAC output voltage is given by
Equation 1
:
Each DAC code determines the 2R leg switch position to either GND or I
OUT
. Because the DAC output
impedance as seen looking into the I
OUT
1 terminal changes versus code, the external I/V converter noise gain
will also change. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage
such that the amplifier offset is not modulated by the DAC I
OUT
1 terminal impedance change. External op amps
with large offset voltages can produce INL errors in the transfer function of the DAC7821 as a result of offset
modulation versus DAC code.
For best linearity performance of the DAC7821, an op amp with a low input offset voltage (OPA277) is
recommended (see
Figure 26
). This circuit allows V
REF
swinging from 10 V to +10 V.
Figure 26. Voltage Output Configuration
11
www.ti.com
APPLICATION INFORMATION
Stability Circuit
GND
I
1
OUT
R
FB
V
REF
V
REF
V
DD
V
DD
V
OUT
I
2
OUT
C
1
U1
U2
Positive Voltage Output Circuit
GND
-2.5V
+2.5 V Reference
OPA277
GND
I
1
OUT
R
FB
0
V
<
OUT
+2.5 V
<
V
OUT
V
REF
V
DD
V
IN
V
DD
V
OUT
I
2
OUT
C
1
OPA277
DAC7821
Bipolar Output Section
)(
V
OUT
+
D
0.5
2
N
)
1
V
REF
(2)
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
For a current-to-voltage design (see
Figure 27
), the DAC7821 current output (I
OUT
) and the connection with the
inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)
layout design. For each code change, there is a step function. If the gain bandwidth product (GBP) of the op amp
is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible. Therefore,
for circuit stability, a compensation capacitor C
1
(1 pF to 5 pF typ) can be added to the design, as shown in
Figure 27
.
Figure 27. Gain Peaking Prevention Circuit with Compensation Capacitor
As
Figure 28
illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC7821. This design is suggested instead of using an inverting amp to invert the output as a result of resistor
tolerance errors. For a negative reference, V
OUT
and GND of the reference are level-shifted to a virtual ground
and a 2.5 V input to the DAC7821 with an op amp.
Figure 28. Positive Voltage Output Circuit
The DAC7821, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output I
OUT
is the inverse of the input reference voltage at V
REF
.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in
Figure 29
,
external op amp U4 is added as a summing amp and has a gain of 2X that widens the output span to 5 V. A
4-quadrant multiplying circuit is implemented by using a 2.5 V offset of the reference voltage to bias U4.
According to the circuit transfer equation given in
Equation 2
, input data (D) from code 0 to full-scale produces
output voltages of V
OUT
= 2.5 V to V
OUT
= +2.5 V.
12
www.ti.com
+2.5 V
(+10 V)
U4
OPA277
10 kW
10 kW
5 kW
-
2.5 V
+2.5 V
V
OUT
( 10 V
-
+10 V)
V
OUT
U2
GND
I
1
OUT
R
FB
V
REF
V
DD
V
DD
V
OUT
I
2
OUT
C
1
OPA277
DAC7821
C
2
Programmable Current Source Circuit
I
L
+
(
R2
)
R3
)
R1
R3
V
REF
D
(3)
Z
O
+
R1 R3
(
R1
R2
)
R1
(
R2
R3
) )
R1
(
R2
R3
)
(4)
R2
15 kW
I
L
LOAD
C
1
10 pF
U3
OPA277
R1
150 kW
R3
50 W
R3
50 W
R1
150 kW
R2
15 kW
OPA277
DAC7821
GND
I
1
OUT
R
FB
V
REF
V
DD
V
DD
V
OUT
I
2
OUT
U1
U2
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
APPLICATION INFORMATION (continued)
External resistance mismatching is the significant error in
Figure 29
.
Figure 29. Bipolar Output Circuit
A DAC7821 can be integrated into the circuit in
Figure 30
to implement an improved Howland current pump for
precise voltage-to-current conversions. Bidirectional current flow and high voltage compliance are two features of
the circuit. With a matched resistor network, the load current of the circuit is shown by
Equation 3
:
The value of R3 in the previous equation can be reduced to increase the output current drive of U3. U3 can drive
20 mA in both directions with voltage compliance limited up to 15 V by the U3 voltage supply. Elimination of the
circuit compensation capacitor C
1
in the circuit is not suggested as a result of the change in the output
impedance Z
O
, according to
Equation 4
:
As shown in
Equation 4
, with matched resistors, Z
O
is infinite and the circuit is optimum for use as a current
source. However, if unmatched resistors are used, Z
O
is positive or negative with negative output impedance
being a potential cause of oscillation. Therefore, by incorporating C
1
into the circuit, possible oscillation problems
are eliminated. The value of C
1
can be determined for critical applications; for most applications, however, a
value of several pF is suggested.
Figure 30. Programmable Bidirectional Current Source Circuit
13
www.ti.com
Parallel Interface
Cross-Reference
DAC7821
SBAS365A OCTOBER 2005 REVISED FEBRUARY 2006
APPLICATION INFORMATION (continued)
Data is loaded to the DAC7821 as a 12-bit parallel word. The bi-directional bus is controlled with CS and R/W,
allowing data to be written to or read from the DAC register. To write to the device, CS and R/W are brought low,
and data available on the data lines fills the input register. The rising edge of CS latches the data and transfers
the latched data-word to the DAC register. The DAC latches are not transparent; therefore, a write sequence
must consist of a falling and rising edge on CS in order to ensure that data is loaded to the DAC register and its
analog equivalent is reflected on the DAC output.
To read data stored in the device, R/W is held high and CS is brought low. Data is loaded from the DAC register
back to the input register and out onto the data line, where it can be read back to the controller.
The DAC7821 has an industry-standard pinout.
Table 1
provides the cross-reference information.
Table 1. Cross-Reference
SPECIFIED
TEMPERATURE
PACKAGE
PACKAGE
CROSS-
PRODUCT
INL (LSB)
DNL (LSB)
RANGE
DESCRIPTION
OPTION
REFERENCE PART
DAC7821
1
1
40
C to +125
C
20-Lead TSSOP
TSSOP-20
AD5445
DAC7821
1
1
40
C to +125
C
20-Lead QFN
(1)
QFN-20
AD5445
(1)
Available 2Q 2006.
14
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
DAC7821IPW
ACTIVE
TSSOP
PW
20
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7821IPWG4
ACTIVE
TSSOP
PW
20
78
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7821IPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7821IPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7821IRGPR
PREVIEW
QFN
RGP
20
3000
TBD
Call TI
Call TI
DAC7821IRGPT
PREVIEW
QFN
RGP
20
250
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Apr-2006
Addendum-Page 1
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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