Quad Channel, Low Power, 16-Bit, Serial Input

DIGITAL-TO-ANALOG CONVERTER

APPLICATIONS

PORTABLE INSTRUMENTATION

CLOSED-LOOP SERVO-CONTROL

PROCESS CONTROL

DATA ACQUISITION SYSTEMS

PROGRAMMABLE ATTENUATION

PC PERIPHERALS

DESCRIPTION

The DAC8534 is a quad channel, 16-bit Digital-to-Analog
Converter (DAC) offering low-power operation and a flexible
serial host interface. Each on-chip precision output amplifier
allows rail-to-rail output swing to be achieved over the supply
range of 2.7V to 5.5V. The device supports a standard 3-wire
serial interface capable of operating with input data clock
frequencies up to 30MHz for IOV

= 5V.

The DAC8534 requires an external reference voltage to set
the output range of each DAC channel. Also incorporated
into the device is a power-on reset circuit which ensures that
the DAC outputs power up at zero-scale and remain there
until a valid write takes place. The DAC8534 provides a per
channel power-down feature, accessed over the serial inter-
face, that reduces the current consumption to 200nA per
channel at 5V.

The low-power consumption of this device in normal opera-
tion makes it ideally suited to portable battery-operated
equipment and other low-power applications. The power
consumption is 5mW at 5V, reducing to 4

W in power-down

mode.

The DAC8534 is available in a TSSOP-16 package with a
specified operating temperature range of 40

C to +105

FEATURES

POWER SUPPLY: +2.7V to +5.5V

microPOWER OPERATION: 950

A at 5V

16-BIT MONOTONIC OVER TEMPERATURE

SETTLING TIME: 10

s to

0.003% FSR

ULTRA-LOW AC CROSSTALK: 100dB typ

POWER-ON RESET TO ZERO-SCALE

ON-CHIP OUTPUT BUFFER AMPLIFIER WITH

RAIL-TO-RAIL OPERATION

DOUBLE BUFFERED INPUT ARCHITECTURE

SIMULTANEOUS OR SEQUENTIAL OUTPUT

UPDATE AND POWER-DOWN

16 CHANNEL BROADCAST CAPABILITY

SCHMITT-TRIGGERED INPUTS

TSSOP-16 PACKAGE

DAC8534

SBAS254D SEPTEMBER 2002 REVISED MARCH 2004

www.ti.com

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Buffer

Control

Data

Buffer D

DAC

DAC D

Power-Down

Control Logic

24-Bit

Serial-to-

Parallel

Shift

Resistor
Network

IOV

GND

OUT

Data

Buffer A

DAC

DAC A

REF

SYNC

SCLK

LDAC ENABLE

REF

DAC8

534

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

DAC8534

SBAS254D

www.ti.com

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

(1)

Resolution

Bits

Relative Accuracy

0.0987

% of FSR

Differential Nonlinearity

16-Bit Monotonic

0.25

LSB

Zero-Scale Error

+20

Zero-Scale Error Drift

Full-Scale Error

0.15

1.0

% of FSR

Gain Error

1.0

% of FSR

Gain Temperature Coefficient

ppm of FSR/

Channel-to-Channel Matching

= 2k

, C

= 200pF

PSRR

0.75

mV/V

OUTPUT CHARACTERISTICS

(2)

Output Voltage Range

REF

Output Voltage Settling Time

0.003% FSR

0200

to FD00

= 2k

; 0pF < C

< 200pF

= 2k

; C

= 500pF

Slew Rate

Capacitive Load Stability

470

= 2k

1000

Code Change Glitch Impulse

1LSB Change Around Major Carry

nV-s

Digital Feedthrough

0.5

nV-s

DC Crosstalk

0.25

LSB

AC Crosstalk

1kHz sine Wave

100

DC Output Impedance

Short-Circuit Current

= +5V

= +3V

Power-Up Time

Coming Out of Power-Down Mode

= +5V

2.5

Coming Out of Power-Down Mode

= +3V

AC PERFORMANCE

BW = 20kHz, AV

= 5V

SNR (1st 19 Harmonics Removed)

OUT

= 1kHz

THD

SFDR

SINAD

to GND ........................................................................ 0.3V to +6V

Digital Input Voltage to GND ............................... 0.3V to +AV

+ 0.3V

OUT

A to V

OUT

to GND .................................... 0.3V to + AV

+ 0.3V

Operating Temperature Range ...................................... 40

C to +105

Storage Temperature Range ......................................... 65

C to +150

Junction Temperature Range (T

max) ........................................ +150

Power Dissipation .......................................................... (T

max T

Thermal Impedance ......................................................... 118

C/W

Thermal Impedance ........................................................... 29

C/W

Lead Temperature, Soldering:

Vapor Phase (60s) ............................................................... +215

Infrared (15s) ........................................................................ +220

NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

ABSOLUTE MAXIMUM RATINGS

(1)

PACKAGE/ORDERING INFORMATION

SPECIFICATION

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

DESIGNATOR

(1)

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

DAC8534

TSSOP-16

C to +105

D8534I

DAC8534IPW

Tube, 90

DAC8534IPWR

Tape and Reel, 2000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

ELECTRICAL CHARACTERISTICS

= +2.7V to +5.5V, 40

C to +105

C, unless otherwise specified.

DAC8534

NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.

DAC8534

SBAS254D

www.ti.com

REFERENCE INPUT
Reference Current

REF

= AV

= +5V

135

180

REF

= AV

= +3V

120

Reference Input Range

Reference Input Impedance

LOGIC INPUTS

(2)

Input Current

L, Input LOW Voltage

IOV

= +5V

0.8

L, Input LOW Voltage

IOV

= +3V

0.6

H, Input HIGH Voltage

IOV

= +5V

2.4

H, Input HIGH Voltage

IOV

= +3V

2.1

Pin Capacitance

POWER REQUIREMENTS

2.7

5.5

IOV

2.7

5.5

(normal mode)

DAC Active and Excluding Load Current

IOI

= +3.6V to +5.5V

= IOV

and V

= GND

0.95

1.6

= +2.7V to +3.6V

= IOV

and V

= GND

0.9

1.5

(all power-down modes)

= +3.6V to +5.5V

= IOV

and V

= GND

0.8

= +2.7V to +3.6V

= IOV

and V

= GND

0.05

POWER EFFICIENCY
I

OUT

LOAD

= 2mA, AV

= +5V

TEMPERATURE RANGE
Specified Performance

+105

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ELECTRICAL CHARACTERISTICS

(Cont.)

= +2.7V to +5.5V, 40

C to +105

C, unless otherwise specified.

DAC8534

NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.

PIN

NAME

DESCRIPTION

OUT

Analog output voltage from DAC A.

OUT

Analog output voltage from DAC B.

REF

Positive reference voltage input.

Power supply input, +2.7V to +5.5V.

REF

Negative reference voltage input.

GND

Ground reference point for all circuitry on the part.

OUT

Analog output voltage from DAC C.

OUT

Analog output voltage from DAC D.

SYNC

Level-triggered control input (active LOW). This is
the frame synchronization signal for the input data.
When SYNC goes LOW, it enables the input shift
register and data is transferred in on the falling
edges of the following clocks. The DAC is updated
following the 24th clock (unless SYNC is taken
HIGH before this edge in which case the rising edge
of SYNC acts as an interrupt and the write sequence
is ignored by the DAC8534).

SCLK

Serial Clock Input. Data can be transferred at rates
up to 30MHz.

Serial Data Input. Data is clocked into the 24-bit
input shift register on each falling edge of the serial
clock input.

IOV

Digital Input-Output Power Supply

Address 0 -- sets device address, see Table II.

Address 1 -- sets device address, see Table II.

ENABLE

Active LOW, ENABLE LOW connects the SPI inter-
face to the serial port.

LDAC

Load DACs, rising edge triggered loads all DAC
registers.

PIN DESCRIPTIONS

PIN CONFIGURATION

Top View

TSSOP

OUT

REF

GND

OUT

LDAC

ENABLE

IOV

SCLK

SYNC

DAC8534

DAC8534

SBAS254D

www.ti.com

SERIAL WRITE OPERATION

SCLK

SYNC

DB23

DB0

DB23

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNITS

(3)

SCLK Cycle Time

IOV

= AV

= 2.7V to 3.6V

IOV

= AV

= 3.6V to 5.5V

SCLK HIGH Time

IOV

= AV

= 2.7V to 3.6V

IOV

= AV

= 3.6V to 5.5V

SCLK LOW Time

IOV

= AV

= 2.7V to 3.6V

22.5

IOV

= AV

= 3.6V to 5.5V

SYNC Falling Edge to SCLK

IOV

= AV

= 2.7V to 3.6V

Rising Edge Setup Time

IOV

= AV

= 3.6V to 5.5V

Data Setup Time

IOV

= AV

= 2.7V to 3.6V

IOV

= AV

= 3.6V to 5.5V

Data Hold Time

IOV

= AV

= 2.7V to 3.6V

4.5

IOV

= AV

= 3.6V to 5.5V

4.5

24th SCLK Falling Edge to

IOV

= AV

= 2.7V to 3.6V

SYNC Rising Edge

IOV

= AV

= 3.6V to 5.5V

Minimum SYNC HIGH Time

IOV

= AV

= 2.7V to 3.6V

IOV

= AV

= 3.6V to 5.5V

24th SCLK Falling Edge to

IOV

= AV

= 2.7V to 5.5V

130

SYNC Falling Edge

NOTES: (1) All input signals are specified with t

= t

= 3ns (10% to 90% of AV

) and timed from a voltage level of (V

+ V

)/2. (2) See Serial Write Operation

timing diagram, below. (3) Maximum SCLK frequency is 30MHz at IOV

= AV

= +3.6V to +5.5V and 20MHz at IOV

= AV

= +2.7V to +3.6V.

TIMING CHARACTERISTICS

(1, 2)

= +2.7V to +5.5V; all specifications 40

C to +105

C unless otherwise noted.

DAC8534

DAC8534

SBAS254D

www.ti.com

TYPICAL CHARACTERISTICS

At T

= +25

C, unless otherwise noted.

64
48
32
16

16
32
48
64

LE (LSB)

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

1.0

0.5

0.0

0.5

1.0

DLE (LSB)

CHANNEL A

= 5V

64
48
32
16

16
32
48
64

LE (LSB)

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

1.0

0.5

0.0

0.5

1.0

DLE (LSB)

CHANNEL B

= 5V

64
48
32
16

16
32
48
64

LE (LSB)

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

1.0

0.5

0.0

0.5

1.0

DLE (LSB)

CHANNEL C

= 5V

64
48
32
16

16
32
48
64

LE (LSB)

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

1.0

0.5

0.0

0.5

1.0

DLE (LSB)

CHANNEL D

= 5V

64
48
32
16

16
32
48
64

LE (LSB)

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

1.0

0.5

0.0

0.5

1.0

DLE (LSB)

CHANNEL A

= 2.7V

64
48
32
16

16
32
48
64

LE (LSB)

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

1.0

0.5

0.0

0.5

1.0

DLE (LSB)

CHANNEL B

= 2.7V

DAC8534

SBAS254D

www.ti.com

TYPICAL CHARACTERISTICS

(Cont.)

At T

= +25

C, unless otherwise noted.

64
48
32
16

16
32
48
64

LE (LSB)

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

1.0

0.5

0.0

0.5

1.0

DLE (LSB)

CHANNEL C

= 2.7V

64
48
32
16

16
32
48
64

LE (LSB)

LINEARITY ERROR AND DIFFERENTIAL

LINEARITY ERROR vs DIGITAL INPUT CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

1.0

0.5

0.0

0.5

1.0

DLE (LSB)

CHANNEL D

= 2.7V

ZERO-SCALE ERROR vs TEMPERATURE

Error (mV)

110

Temperature (

CH D

CH C

CH B

CH A

= V

REF

= 5V

ZERO-SCALE ERROR vs TEMPERATURE

Error (mV)

110

Temperature (

CH A

CH C

CH B

CH D

= V

REF

= 2.7V

FULL-SCALE ERROR vs TEMPERATURE

Error (mV)

110

Temperature (

To avoid clipping of the output signal
during the test, V

REF

= AV

10mV,

= 5V, V

REF

= 4.99V

CH C

CH D

CH B

CH A

FULL-SCALE ERROR vs TEMPERATURE

Error (mV)

110

Temperature (

To avoid clipping of the output signal
during the test, V

REF

= AV

10mV,

= 2.7V, V

REF

= 2.69V

CH C

CH D

CH A

CH B

DAC8534

SBAS254D

www.ti.com

TYPICAL CHARACTERISTICS

(Cont.)

At T

= +25

C, unless otherwise noted.

0.150

0.125

0.100

0.075

0.050

0.025

0.000

OUT

(V)

SINK CURRENT CAPABILITY (ALL CHANNELS)

SINK

(mA)

= 5V

REF

= AV

10mV

DAC loaded with 0000

= 2.7V

REF

= AV

10mV

DAC Loaded with FFFFH

= 5V

5.00

4.95

4.90

4.85

4.80

OUT

(V)

SOURCE CURRENT CAPABILITY (ALL CHANNELS)

SOURCE

(mA)

REF

= AV

10mV

DAC Loaded with FFFFH

= 2.7V

2.70

2.65

2.60

2.55

2.50

OUT

(V)

SOURCE CURRENT CAPABILITY (ALL CHANNELS)

SOURCE

(mA)

= V

REF

= 5V

SUPPLY CURRENT vs DIGITAL INPUT CODE

1200

1000

800

600

400

200

(

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

= V

REF

= 2.7V

= V

REF

= 5V

= V

REF

= 2.7V

Reference Current Included
All Channels Powered, No Load.

1200

1000

800

600

400

200

SUPPLY CURRENT vs TEMPERATURE

(

110

Temperature (

1000

950

900

850

800

750

700

650

600

(

2.7

3.05

3.4

3.75

4.1

4.45

4.8

5.15

5.5

(V)

SUPPLY CURRENT vs SUPPLY VOLTAGE

DAC8534

SBAS254D

www.ti.com

TYPICAL CHARACTERISTICS

(Cont.)

At T

= +25

C, unless otherwise noted.

= 25

C, SYNC Input (All others inputs = GND)

Reference Current Included

= V

REF

= 5V

= V

REF

= 2.7V

SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

1750

1650

1550

1450

1350

1250

1150

1050

950

850

750

+ IOI

(

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

LOGIC

(V)

= V

REF

= 5V

Reference Current Included

HISTOGRAM OF CURRENT CONSUMPTION

1500

1000

500

Frequency

820

790

850

880

910

940

970

1000

1030

1060

1090

120

150

(

= V

REF

= 2.7V

Reference Current Included

HISTOGRAM OF CURRENT CONSUMPTION

1500

1000

500

Frequency

820

790

760

730

850

880

910

940

970

1000

1030

1060

(

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0.5

OUT

(V)

EXITING POWER-DOWN MODE

Time (3

s/div)

= V

REF

= 5V

Power-Up Code = FFFF

2.53

2.52

2.51

2.50

2.49

2.48

2.47

2.46

2.45

2.44

2.43

OUT

, 10mV/div)

OUTPUT GLITCH

(Mid-Scale)

Time (1

s/div)

= V

REF

= 5V

Code 7FFF

to 8000

to 7FFF

(Glitch Occurs Every N · 4096
Code Boundary)

4.72

4.70

4.68

4.66

4.64

4.62

4.60

4.58

4.56

4.54

OUT

, 20mV/div)

OUTPUT GLITCH

(Worst Case)

Time (1

s/div)

= V

REF

= 5V

Code EFFF

to F000

to EFFF

(Glitch Occurs Every N · 4096
Code Boundary)

DAC8534

SBAS254D

www.ti.com

TYPICAL CHARACTERISTICS

(Cont.)

At T

= +25

C, unless otherwise noted.

Channel D Output

Channel B Output

Channel A Output

Channel C Output

ABSOLUTE ERROR

Output Error (mV)

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

= V

REF

= 5V

= 25

Channel B Output

Channel A Output

Channel C Output

Channel D Output

ABSOLUTE ERROR

Output Error (mV)

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

= V

REF

= 2.7V

= 25

FULL-SCALE SETTLING TIME

(Large Signal)

OUT

(V)

Time (12

s/div)

= V

REF

= 5.5V

Output Loaded with
2k

and 200pF

to GND

HALF-SCALE SETTLING TIME

(Large Signal)

3.0

2.5

2.0

1.5

1.0

0.5

OUT

(V)

Time (12

s/div)

= V

REF

= 5V

Output Loaded with
2k

and 200pF

to GND

FULL-SCALE SETTLING TIME

(Large Signal)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

OUT

(V)

Time (12

s/div)

= V

REF

= 2.7V

Output Loaded with
2k

and 200pF

to GND

HALF-SCALE SETTLING TIME

1.5

1.0

0.5

OUT

(V)

Time (12

s/div)

= V

REF

= 2.7V

Output Loaded with

and 200pF

to GND

DAC8534

SBAS254D

www.ti.com

TYPICAL CHARACTERISTICS

(Cont.)

At T

= +25

C, unless otherwise noted.

= 5V

= 2.7V

= V

REF

1dB FSR Digital Input, F

= 52ksps

Measurement Bandwidth = 20kHz

SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY

SNR (dB)

500

1.0k

1.5k

2.0k

2.5k

3.0k

3.5k

4.0k

4.5k

Output Frequency (Hz)

= V

REF

= 5V

= 52ksps, 1dB FSR Digital Input

Measurement Bandwidth = 20kHz

THD

2nd-Harmonic

3rd-Harmonic

TOTAL HARMONIC DISTORTION vs

OUTPUT FREQUENCY

100

THD (dB)

500

1.0k

1.5k

2.0k

2.5k

3.0k

3.5k

4.0k

Output Frequency (Hz)

= V

REF

= 2.7V

= 52ksps, 1dB FSR Digital Input

Measurement Bandwidth = 20kHz

THD

2nd-Harmonic

3rd-Harmonic

TOTAL HARMONIC DISTORTION vs

OUTPUT FREQUENCY

100

THD (dB)

500

1.0k

1.5k

2.0k

2.5k

3.0k

3.5k

4.0k

Output Frequency (Hz)

FULL-SCALE SETTLING TIME

(Small-Signal-Positive Going Step)

Output V

oltage

Time (2

s/div)

Small-Signal Settling Time
5mV/div

Trigger Pulse

FULL-SCALE SETTLING TIME

(Small-Signal-Negative Going Step)

Output V

oltage

Time (2

s/div)

Small-Signal Settling Time
5mV/div

Trigger Pulse

DAC8534

SBAS254D

www.ti.com

The write sequence begins by bringing the SYNC line LOW.
Data from the D

line is clocked into the 24-bit shift register on

each falling edge of SCLK. The serial clock frequency can be
as high as 30MHz, making the DAC8534 compatible with high-
speed DSPs. On the 24th falling edge of the serial clock, the
last data bit is clocked into the shift register and the shift
register gets locked. Further clocking does not change the shift
register data. Once 24 bits are locked into the shift register, the
8MSBs are used as control bits and the 16LSBs are used as
data. After receiving the 24th falling clock edge, DAC8534
decodes the 8 control bits and 16 data bits to perform the
required function, without waiting for a SYNC rising edge. A
new SPI sequence starts at the next falling edge of SYNC. A
rising edge of SYNC before the 24-bit sequence is complete
resets the SPI interface; no data transfer occurs.

At this point, the SYNC line may be kept LOW or brought HIGH.
In either case, the minimum delay time from the 24th falling
SCLK edge to the next falling SYNC edge must be met in order
to properly begin the next cycle. To assure the lowest power
consumption of the device, care should be taken that the digital
input levels are as close to each rail as possible. (Please refer
to the "Typical Characteristics" section for the "Supply Current
vs Logic Input Voltage" transfer characteristic curve.)

IOV

AND VOLTAGE TRANSLATORS

The IOV

pin powers the digital input structures of the

DAC8534. For single-supply operation, it could be tied to AV

For dual-supply operation, the IOV

pin provides interface

flexibility with various CMOS logic families and it should be
connected to the logic supply of the system. Analog circuits and
internal logic of the DAC8534 use AV

as the supply voltage.

The external logic high inputs get translated to AV

by level

shifters. These level shifters use the IOV

voltage as a

THEORY OF OPERATION

DAC SECTION

The architecture of each channel of the DAC8534 consists of
a resistor-string DAC followed by an output buffer amplifier.
Figure 1 shows a simplified block diagram of the DAC
architecture.

The input coding for each device is unipolar straight binary,
so the ideal output voltage is given by:

OUT

REF

65536

(

)

where D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 65535.
V

OUT

X refers to channel A or through D.

RESISTOR STRING

The resistor string section is shown in Figure 2. It is simply
a divide-by-2 resistor followed by a string of resistors. The
code loaded into the DAC register determines at which node
on the string the voltage is tapped off. This voltage is then
applied to the output amplifier by closing one of the switches
connecting the string to the amplifier.

OUTPUT AMPLIFIER

Each output buffer amplifier is capable of generating rail-to-
rail voltages on its output which approaches an output range
of 0V to AV

(gain and offset errors must be taken into

account). Each buffer is capable of driving a load of 2k

parallel with 1000pF to GND. The source and sink capabili-
ties of the output amplifier can be seen in the typical charac-
teristics.

SERIAL INTERFACE

The DAC8534 uses a 3-wire serial interface (SYNC, SCLK,
and D

), which is compatible with SPITM, QSPITM, and

MicrowireTM interface standards, as well as most DSPs. See
the Serial Write Operation timing diagram for an example of
a typical write sequence.

FIGURE 1. DAC8534 Architecture.

To Output

Amplifier

(2x Gain)

REF

DIVIDER

REF

FIGURE 2. Resistor String.

DAC Register

REF (+)

Resistor String

REF()

REF

OUT

50k

70k

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LD1

LD0

DAC Select 1 DAC Select 0

PD0

D15

D14

D13

D12

D11

D10

DB11

DB0

FIGURE 3. DAC8534 Data Input Register Format.

DB23

DB12

reference to shift the incoming logic HIGH levels to AV

IOV

is ensured to operate from 2.7V to 5.5V regardless of

the AV

voltage, which ensures compatibility with various

logic families. Although specified down to 2.7V, IOV

will

operate at as low as 1.8V with degraded timing and tempera-
ture performance. For lowest power consumption, logic V

levels should be as close as possible to IOV

, and logic V

levels should be as close as possible to GND voltages.

INPUT SHIFT REGISTER

The input shift register (SR) of the DAC8534 is 24 bits wide, as
shown in Figure 3, and is made up of 8 control bits (DB16-DB23)
and 16 data bits (DB0-DB15). The first two control bits (DB22
and DB23) are the address match bits. The DAC8534 offers
additional hardware-enabled addressing capability allowing a
single host to talk to up to four DAC8534s through a single SPI
bus without any glue logic, enabling up to 16-channel operation.
The state of DB23 should match the state of pin A1; similarly, the
state of DB22 should match the state of pin A0. If there is no
match, the control command and the data (DB21...DB0) are
ignored by the DAC8534. That is, if there is no match, the
DAC8534 is not addressed. Address matching can be overrid-
den by the broadcast update, as will be explained.

LD 1 (DB20) and LD 0 (DB21) control the updating of each
analog output with the specified 16-bit data value or power-
down command. Bit DB19 is a "Don't Care" bit which does not
affect the operation of the DAC8534 and can be 1 or 0. The
DAC Channel Select Bits (DB17, DB18) control the destination
of the data (or power-down command) from DAC A through
DAC D. The final control bit, PD0 (DB16), selects the power-
down mode of the DAC8534 channels.

The DAC8534 also supports a number of different load com-
mands. The load commands include broadcast commands to
address all the DAC8534s on an SPI bus. The load commands
can be summarized as follows:

DB21 = 0 and DB20 = 0: Single-channel store. The temporary
register (data buffer) corresponding to a DAC selected by
DB18 and DB17 is updated with the contents of SR data (or
power-down).

DB21 = 0 and DB20 = 1: Single-channel update. The tempo-
rary register and DAC register corresponding to a DAC se-
lected by DB18 and DB17 are updated with the contents of SR
data (or power-down).

DB21 = 1 and DB20 = 0: Simultaneous update. A channel
selected by DB18 and DB17 gets updated with the SR data,
and simultaneously, all the other channels get updated with
previous stored data (or power-down).

DB21 = 1 and DB20 = 1: Broadcast update. All the DAC8534s
on the SPI bus respond, regardless of address matching. If
DB18 = 0, then SR data gets ignored, all channels from all

DAC8534s get updated with previously stored data (or power-
down). If DB18 = 1, then SR data (or power-down) updates all
channels of all DAC8534s in the system. This broadcast update
feature allows the simultaneous update of up to 16 channels.

Power-down/data selection is as follows:

DB16 is a power-down flag. If this flag is set, then DB15 and
DB14 select one of the four power-down modes of the device
as described in Table I. If DB16 = 1, DB15 and DB14 no longer
represent the two MSBs of data, they represent a power-down
condition described in Table I. Similar to data, power-down
conditions can be stored at the temporary registers of each
DAC. It is possible to update DACs simultaneously either with
data, power-down, or a combination of both.

Please refer to Table II for more information.

PD0 (DB16) PD1 (DB15) PD2 (DB14)

OPERATING MODE

Output High Impedance

Output Typically 1k

to GND

Output Typically 100k

to GND

Output High Impedance

TABLE I. DAC8534 Power-Down Modes.

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept LOW for
at least 24 falling edges of SCLK and the addressed DAC
register is updated on the 24th falling edge. However, if

SYNC is brought HIGH before the 24th falling edge, it acts

as an interrupt to the write sequence; the shift register is
reset and the write sequence is discarded. Neither an update
of the data buffer contents, DAC register contents, nor a
change in the operating mode occurs (see Figure 4).

POWER-ON RESET

The DAC8534 contains a power-on reset circuit that con-
trols the output voltage during power-up. On power-up, the
DAC registers are filled with zeros and the output voltages
are set to zero-scale; they remain there until a valid write
sequence and load command is made to the respective
DAC channel. This is useful in applications where it is
important to know the state of the output of each DAC
output while the device is in the process of powering up. No
device pin should be brought high before power is applied
to the device.

POWER-DOWN MODES

The DAC8534 utilizes four modes of operation. These modes
are accessed by setting three bits (PD2, PD1, and PD0) in
the shift register and performing a "Load" action to the DACs.
The DAC8534 offers a very flexible power-down interface
based on channel register operation. A channel consists of a

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D23

D22

D21

D20

D19

D18

D17

D16

Load 1

Load 0

Don't Care

DAC Sel 1 DAC Sel 0

PD0

This address selects 1 of 4 possible devices on a single SPI
data bus based on each device's address pin(s) state.

Write To Buffer A w/Data

Write To Buffer B w/Data

Write To Buffer C w/Data

Write To Buffer D w/Data

Write To Buffer (selected by DB17 and DB18) w/Power-Down
Command

Write To Buffer w/Data and Load DAC (selected by DB17 and
DB18)

Write To Buffer w/Power-Down Command and Load DAC
(selected by DB17 and DB18)

Write To Buffer w/Data (selected by DB17 and DB18) and Load All
DACs

Write To Buffer w/Power-Down Command (selected by DB17 and
DB18) and Load All DACs

Load All DACs, All Device, and All Buffers with Stored Data

Write To All Devices and Load All Dacs, with SR Data

Write To All Devices w/Power-Down Command in SR

SCLK

SYNC

DIN

Invalid Write-Sync Interrupt:

SYNC HIGH Before 24th Falling Edge

Valid Write-Buffer/DAC Update:

SYNC HIGH After 24th Falling Edge

DB23 DB22

DB0

DB23 DB22

DB1

DB0

24th Falling

Edge

24th Falling

Edge

FIGURE 4. Interrupt and Valid SYNC Timing.

D15

D14

D13-D0

MSB

MSB-1

MSB-2...LSB

single 16-bit DAC with power-down circuitry, a temporary
storage register (TR), and a DAC register (DR). TR and DR
are both 18-bit wide. Two MSBs represent power-down
condition and 16LSBs represent data for TR and DR. By
adding bits 17 and 18 to TR and DR, a power-down condition
can be temporarily stored and used just like data. Internal
circuits ensure that DB15 and DB14 get transfered to TR17
and TR16 (DR17 and DR16), when DB16 = 1.

The DAC8534 treats the power-down condition like data and
all the operational modes are still valid for power-down. It is
possible to broadcast a power-down condition to all the
DAC8534s in a system, or it is possible to simultaneously
power-down a channel while updating data on other channels.

DB16, DB15, and DB14 = 100 represent a power-down
condition with Hi-Z output impedance for a selected channel.
Same is true for 111. 101 represents a power-down condition
with 1k output impedance and 110 represents a power-down
condition with 100k output impedance.

TABLE II. Control Matrix.

DESCRIPTION

(A0 and A1 should

correspond to the

package address set

via pins 13 and 14.)

See Below

0/1

(00, 01, 10, or 11)

Data

(see Table I)

When both bits are set to 0 or 1, the device enters a high-
impedance state with a typical power consumption of 3pA at
5V. For the two low impedance output modes, however, the
supply current falls to 100nA at 5V (50nA at 3V). Not only does
the supply current fall, but the output stage is also internally
switched from the output of the amplifier to a resistor network
of known values. This has the advantage that the output
impedance of the device is known while it is in power-down
mode. There are three different options for power-down: the
output is connected internally to GND through a 1k

resistor,

a 100k

resistor, or it is left open-circuited (High-Impedance).

The output stage is illustrated in Figure 5.

All analog circuitry is shut down when the power-down mode
is activated. Each DAC will exit power-down when PD0 is set
to 0, new data is written to the Data Buffer, and the DAC
channel receives a "Load" command. The time to exit power-
down is typically 2.5

s for AV

= 5V and 5

s for AV

= 3V

(see the Typical Characteristics).

Broadcast Modes

(Address Select)

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OPERATION EXAMPLES

Example 1: Write to Data Buffer A; Through Buffer D; Load DAC A Through DAC D Simultaneously
·

1st--Write to Data Buffer A:

2nd--Write to Data Buffer B:

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

......

DB1

DB0

D15

.....

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

......

DB1

DB0

D15

.....

2nd--Write to Data Buffer B and Load DAC B: DAC B output settles to specified value upon completion:

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

......

DB1

DB0

D15

.....

3rd--Write to Data Buffer C and Load DAC C: DAC C output settles to specified value upon completion:

4th--Write to Data Buffer D and Load DAC D: DAC D output settles to specified value upon completion:

After completion of each write cycle, DAC analog output settles to the voltage specified.

Example 3: Power-Down DAC A and DAC B to 1k

and Power-Down DAC C and DAC D to 100k

Simultaneously

Write power-down command to Data Buffer A: DAC A to 1k

The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon completion of the
4th write sequence. (The "Load" command moves the digital data from the data buffer to the DAC register at which time the
conversion takes place and the analog output is updated. "Completion" occurs on the 24th falling SCLK edge after SYNC LOW.)

Example 2: Load New Data to DAC A Through DAC D Sequentially
·

1st--Write to Data Buffer A and Load DAC A: DAC A output settles to specified value upon completion:

3rd--Write to Data Buffer C:

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

......

DB1

DB0

D15

.....

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

......

DB1

DB0

D15

.....

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

......

DB1

DB0

D15

.....

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

......

DB1

DB0

D15

.....

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

DB14

DB13

........

........

4th--Write to Data Buffer D and simultaneously update all DACs:

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

......

DB1

DB0

D15

.....

Resistor

String DAC

Amplifier

Power-down

Circuitry

Resistor
Network

OUT

FIGURE 5. Output Stage During Power-Down (High-Impedance).

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LDAC FUNCTIONALITY

The DAC8534 offers both a software and hardware simulta-
neous update function. The DAC8534 double-buffered architec-
ture has been designed so that new data can be entered for
each DAC without disturbing the analog outputs. The software
simultaneous update capability is controlled by the Load 1 (LD1)
and Load 0 (LD0) control bits. By setting Load 1 equal to "1" all
of the DAC registers will be updated on the falling edge of the
24th clock signal. When the new data has been entered into the
device, all of the DAC outputs can be updated simultaneously
and synchronously with the clock.

The internal DAC register is edge triggered and not level
triggered, therefore, when the LDAC pin signal is transitioned
from LOW to HIGH, the digital word currently in the DAC input
register is latched. Additionally, it allows the DAC input registers
to be written to at any point; then, the DAC output voltages can
be asynchronously changed via the LDAC pin. The LDAC trigger
should only be used after the buffers are properly updated
through software. If DAC outputs are desired to be updated
through software only, the LDAC pin must be tied low perma-
nently.

Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially:
·

Write power-down command to Data Buffer A and Load DAC A: DAC A output = High-Z:

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

DB14

DB13

........

........

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

DB14

DB13

........

........

Write power-down command to Data Buffer B and Load DAC B: DAC B output = High-Z:

Write power-down command to Data Buffer C and Load DAC C: DAC C output = High-Z:

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

DB14

DB13

........

........

Write power-down command to Data Buffer D and Load DAC D: DAC D output = High-Z:

MICROPROCESSOR
INTERFACING

DAC8534 to 8051 INTERFACE

See Figure 6 for a serial interface between the DAC8534 and
a typical 8051-type microcontroller. The setup for the inter-
face is as follows: TXD of the 8051 drives SCLK of the
DAC8534, while RXD drives the serial data line of the device.
The SYNC signal is derived from a bit-programmable pin on
the port of the 8051. In this case, port line P3.3 is used. When
data is to be transmitted to the DAC8534, P3.3 is taken LOW.
The 8051 transmits data in 8-bit bytes; thus only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left LOW after the first eight bits are transmitted,
then a second and third write cycle is initiated to transmit the
remaining data. P3.3 is taken HIGH following the completion
of the third write cycle. The 8051 outputs the serial data in a
format which presents the LSB first, while the DAC8534
requires its data with the MSB as the first bit received. The
8051 transmit routine must therefore take this into account,
and "mirror" the data as needed.

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

DB14

DB13

........

........

The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon completion of the
1st, 2nd, 3rd, and 4th write sequences, respectively.

Write power-down command to Data Buffer B: DAC B to 1k

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

DB14

DB13

........

........

Write power-down command to Data Buffer C: DAC C to 100k

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

DB14

DB13

........

........

Write power-down command to Data Buffer D: DAC D to 100k

and Simultaneously Update all DACs.

LD1

LD0

DAC Sel 1

DAC Sel 0

PD0

DB15

DB14

DB13

........

........

The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified mode upon
completion of the 4th write sequence.

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DAC8534 to Microwire INTERFACE

Figure 7 shows an interface between the DAC8534 and any
Microwire compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the
DAC8534 on the rising edge of the CK signal.

DAC8534 to 68HC11 INTERFACE

Figure 8 shows a serial interface between the DAC8534 and
the 68HC11 microcontroller. SCK of the 68HC11 drives the
SCLK of the DAC8534, while the MOSI output drives the
serial data line of the DAC. The SYNC signal is derived from
a port line (PC7), similar to the 8051 diagram.

FIGURE 6. DAC8534 to 80C51/80L51 Interface.

FIGURE 8. DAC8534 to 68HC11 Interface.

80C51/80L51

(1)

P3.3

TXD

RXD

DAC8534

(1)

SYNC

SCLK

NOTE: (1) Additional pins omitted for clarity.

SYNC

SCLK

Microwire

DAC8534

(1)

NOTE: (1) Additional pins omitted for clarity.

Microwire is a registered trademark of National Semiconductor.

68HC11

(1)

PC7

SCK

MOSI

SYNC

SCLK

DAC8534

(1)

NOTE: (1) Additional pins omitted for clarity.

DAC8534

TMS320 DSP

SYNC

SCLK

FSX

CLKX

OUT

Output A

Output D

Reference

Input

REF

GND

0.1

F to 10

Positive Supply

0.1

FIGURE 7. DAC8534 to Microwire Interface.

FIGURE 9. DAC8534 to TMS320 DSP.

APPLICATIONS

CURRENT CONSUMPTION

The DAC8534 typically consumes 250

A at AV

= 5V and

225

A at AV

= 3V for each active channel, including

reference current consumption. Additional current consump-
tion can occur at the digital inputs if V

<< IOV

. For most

efficient power operation, CMOS logic levels are recom-
mended at the digital inputs to the DAC.
In power-down mode, typical current consumption is 200nA
per channel. A delay time of 10ms to 20ms after a power-
down command is issued to the DAC is typically sufficient for
the power-down current to drop below 10

DRIVING RESISTIVE AND CAPACITIVE LOADS

The DAC8534 output stage is capable of driving loads of up
to 1000pF while remaining stable. Within the offset and gain
error margins, the DAC8534 can operate rail-to-rail when
driving a capacitive load. Resistive loads of 2k

can be

driven by the DAC8534 while achieving a typical load regu-
lation of 1%. As the load resistance drops below 2k

, the

load regulation error increases. When the outputs of the DAC
are driven to the positive rail under resistive loading, the
PMOS transistor of each Class-AB output stage can enter
into the linear region. When this occurs, the added IR voltage
drop deteriorates the linearity performance of the DAC. This
only occurs within approximately the top 20mV of the DAC's
output voltage characteristic. The reference voltage applied
to the DAC8534 may be reduced below the supply voltage
applied to AV

in order to eliminate this condition if good

linearity is a requirement at full-scale (under resistive loading
conditions).

CROSSTALK AND AC PERFORMANCE

The DAC8534 architecture uses separate resistor strings for
each DAC channel in order to achieve ultra-low crosstalk
performance. DC crosstalk seen at one channel during a full-

The 68HC11 should be configured so that its CPOL bit is 0
and its CPHA bit is 1. This configuration causes data appear-
ing on the MOSI output to be valid on the falling edge of
SCLK. When data is being transmitted to the DAC, the

SYNC line is held LOW (PC7). Serial data from the 68HC11

is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. (Data is transmitted MSB
first.) In order to load data to the DAC8534, PC7 is left LOW
after the first eight bits are transferred, then a second and
third serial write operation is performed to the DAC. PC7 is
taken HIGH at the end of this procedure.

DAC8534 to TMS320 DSP INTERFACE

Figure 9 shows the connections between the DAC8534 and
a TMS320 Digital Signal Processor (DSP). A Single DSP can
control up to four DAC8534s without any interface logic.

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FIGURE 11. Bipolar Operation with the DAC8534.

DAC8534

(Other pins omitted for clarity.)

, V

REF

OUT

10k

+5V

0.1

+5V

OPA703

FIGURE 10. REF02 as a Power Supply to the DAC8534.

REF02

DAC8534

3-Wire

Serial

Interface

+5V

, V

REF

OUT

= 0V to 5V

SYNC

SCLK

+15

+ I

REF

scale change on the neighboring channel is typically less than
0.5LSBs. The AC crosstalk measured (for a full-scale, 1kHz
sine wave output generated at one channel, and measured at
the remaining output channel) is typically under 100dB.
In addition, the DAC8534 can achieve typical AC perfor-
mance of 96dB SNR (Signal-to-Noise Ratio) and 65dB THD
(Total Harmonic Distortion), making the DAC8534 a solid
choice for applications requiring high SNR at output frequen-
cies at or below 4kHz.

OUTPUT VOLTAGE STABILITY

The DAC8534 exhibits excellent temperature stability of
5ppm/

C typical output voltage drift over the specified tem-

perature range of the device. This enables the output voltage
of each channel to stay within a

V window for a

ambient temperature change.
Good Power-Supply Rejection Ratio (PSRR) performance
reduces supply noise present on AV

from appearing at the

outputs to well below 10

V-s. Combined with good DC noise

performance and true 16-bit differential linearity, the DAC8534
becomes a perfect choice for closed-loop control applica-
tions.

SETTLING TIME AND OUTPUT
GLITCH PERFORMANCE

Settling time to within the 16-bit accurate range of the
DAC8534 is achievable within 10

s for a full-scale code

change at the input. Worst-case settling times between
consecutive code changes is typically less than 2

s, en-

abling update rates up to 500ksps for digital input signals
changing code-to-code. The high-speed serial interface of
the DAC8534 is designed in order to support these high
update rates.
For full-scale output swings, the output stage of each
DAC8534 channel typically exhibits less than 100mV of
overshoot and undershoot when driving a 200pF capacitive
load. Code-to-code change glitches are extremely low given
that the code-to-code transition does not cross an Nx4096
code boundary. Due to internal segmentation of the
DAC8534, code-to-code glitches occur at each crossing of
an Nx4096 code boundary. These glitches can approach
100nVs for N = 15, but settle out within ~2

USING THE REF02 AS A POWER SUPPLY FOR
THE DAC8534

Due to the extremely low supply current required by the
DAC8534, a possible configuration is to use a REF02 +5V
precision voltage reference to supply the required voltage to
the DAC8534's supply input as well as the reference input, as
shown in Figure 10. This is especially useful if the power
supply is quite noisy or if the system supply voltages are at
some value other than 5V. The REF02 will output a steady
supply voltage for the DAC8534. If the REF02 is used, the
current it needs to supply to the DAC8534 is 1.085mA typical
and 1.78mA max for AV

= 5V. When a DAC output is

loaded, the REF02 also needs to supply the current to the
load. The total typical current required (with a 5k

load on a

given DAC output) is:

1.085mA + (5V/ 5k

) = 2.085mA

BIPOLAR OPERATION USING THE DAC8534

The DAC8534 has been designed for single-supply opera-
tion, but a bipolar output range is also possible using the
circuit in Figure 11. The circuit shown will give an output
voltage range of

REF

. Rail-to-rail operation at the amplifier

output is achievable using an amplifier such as the OPA703,
as shown in Figure 11.

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The output voltage for any input code can be calculated as
follows:

OUT

REF

65536

where D represents the input code in decimal (065535).

With V

REF

= 5V, R

= R

= 10k

OUT

65536

This is an output voltage range of

5V with 0000

corre-

sponding to a 5V output and FFFF

corresponding to a +5V

output. Similarly, using V

REF

= 2.5V, a

2.5V output voltage

range can be achieved.

LAYOUT

A precision analog component requires careful layout, ad-
equate bypassing, and clean, well-regulated power supplies.

The DAC8534 offers single-supply operation, and it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch-
ing speed, the more difficult it will be to keep digital noise
from appearing at the output.

Due to the single ground pin of the DAC8534, all return
currents, including digital and analog return currents for the
DAC, must flow through a single point. Ideally, GND would
be connected directly to an analog ground plane. This plane
would be separate from the ground connection for the digital
components until they were connected at the power-entry
point of the system.

The power applied to AV

should be well regulated and low

noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high-frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between the power connec-
tions and analog output.

As with the GND connection, AV

should be connected to

a positive power-supply plane or trace that is separate from
the connection for digital logic until they are connected at the
power-entry point. In addition, a 1

F to 10

F capacitor in

parallel with a 0.1

F bypass capacitor is strongly recom-

mended. In some situations, additional bypassing may be
required, such as a 100

F electrolytic capacitor or even a

"Pi" filter made up of inductors and capacitors--all designed
to essentially low-pass filter the supply, removing the high-
frequency noise.

Up to four DAC8534 devices can be used on a single SPI bus
without any glue logic to create a high channel count solu-
tion. Special attention is required to avoid digital signal
integrity problems when using multiple DAC8534s on the
same SPI bus. Signal integrity of SYNC, SCLK, and D

lines

will not be an issue as long as the rise times of these digital
signals are longer than six times the propagation delay
between any two DAC8534 devices. Propagation speed is
approximately six inches/ns on standard PCBs. Therefore, if
the digital signal risetime is 1ns, the distance between any
two DAC8534 devices is recommended not to exceed 1 inch.
If the DAC8534s have to be further apart on the PCB, the
signal rise times should be reduced by placing series resis-
tors at the drivers for SYNC, SCLK, and D

lines. If the

largest distance between any two DAC8534s has to be six
inches, the risetime should be reduced to 6ns with an RC
network formed by the series resistor at the digital driver and
the total trace and input capacitance on the PCB.

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