DAC8541

SLAS353 DECEMBER 2001

16-BIT, SINGLE CHANNEL, PARALLEL INPUT DIGITAL-TO-ANALOG

CONVERTER WITH RAIL-TO-RAIL VOLTAGE OUTPUT

www.ti.com

FEATURES

Micropower Operation: 250

A at 5 V AV

Power-On Reset to Min-Scale

16-Bit Monotonic

Settling Time: 10

s to

0.003% FSR

16-Bit Parallel Interface

On-Chip Output Buffer Amplifier With
Rail-to-Rail Operation

Hardware Reset to Min-Scale or Mid-Scale

Double-Buffered Architecture

Asynchronous LDAC Control

Data Readback Support

1.8 V Compatible Digital Interface:

 DV

= 1.8 V5.5 V

Wide Analog Supply Range:

 AV

= 2.7 V5.5 V

32-Lead 5 mm

5 mm TQFP Package

APPLICATIONS

Process Control

Data Acquisition Systems

Closed-Loop Servo Control

PC Peripherals

Portable Instrumentation

DESCRIPTION

The DAC8541 is a low-power, single channel, 16-bit,
voltage output DAC. Its on-chip precision output
amplifier allows rail-to-rail voltage swing to be achieved
at the output. The DAC8541 utilizes a 16-bit parallel
interface and features additional powerdown function
pins as well as hardware-enabled, asynchronous DAC
updating and reset capability.

The DAC8541 requires an external reference voltage to
set the output range of the DAC. The device
incorporates a power-on-reset circuit that ensures that
the DAC output powers up at min-scale and remains
there until a valid write takes place to the device. In
addition, the DAC8541 contains a power-down feature,
accessed via two hardware pins, that when enabled
reduces the current consumption of the device to
200 nA at 5 V.

The low power consumption of this device in normal
operation makes it ideally suited for use in portable
battery operated equipment applications. The power
consumption is 1.2 mW at AV

= 5 V reducing to 1

in power-down mode.

The DAC8541 is available in a 32-lead TQFP package
with an operating temperature range of 40

C to 85

I/O

Buffer

Input

Register

DAC

Register

DAC

Resistor
Network

Power

Down

Control

Logic

Control

Logic

AVDD DVDD

VREFH

VOUTSense

VOUT

PD1

PD0

VREFL

LDAC

RST

RSTSEL

AGND

DGND

R/W

BTC/USB

Data I/O

DAC8541

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

2001, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

AVAILABLE OPTIONS

PRODUCT

PACKAGE

DRAWING NUMBER

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA

DAC8541

32 TQFP

PBS

C to 85

E41Y

DAC8541Y/250

Tape and Reel

DAC8541

32-TQFP

PBS

C to 85

E41Y

DAC8541Y/2K

Tape and Reel

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

to AGND

0.3 V to 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

to DGND

0.3 V to 6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage to DGND

0.3 V to DV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OUT

to AGND

0.3 V to AV

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating temperature range

C to 85

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Junction temperature, T

max

150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

electrical characteristics, DV

= 1.8 V to 5.5 V; AV

= 2.7 V to 5.5 V; R

= 2 k

to AGND; C

= 200

pF to AGND; all specifications 40

C to 85

C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STATIC PERFORMANCE (see Note 1)

Resolution

Bits

Relative accuracy

0.098

%FSR

Differential nonlinearity

16-Bit monotonic

LSB

Zero code error

All zeroes loaded to DAC register

Full-scale error

All ones loaded to DAC register

0.15

0.8

%FSR

Gain error

0.8

%FSR

Zero code error drift

Gain temperature coefficient

ppm of

FSR/

OUTPUT CHARACTERISTICS (see Note 2)

Output voltage range

VREFL

VREFH

Output voltage settling time

(

full scale)

RL = 2 k

; 0 pF < CL < 200 pF

Output voltage settling time

(

full scale)

RL = 2 k

; CL = 500 pF

Slew rate

Capacitive load stability

RL =

470

Capacitive load stability

RL = 2 k

1000

Digital-to-analog glitch impulse

1 LSB change around major carry (see Note 3)

nVs

Digital feedthrough

0.5

nVs

DC output impedance

Short circuit current

AVDD = 5 V

Short circuit current

AVDD = 3 V

Power up time

Coming out of power-down mode, AVDD = 5 V

2.5

Power-up time

Coming out of power-down mode, AVDD = 3 V

NOTES:

1. Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
2. Assured by design and characterization, not production tested.
3. Specification for code changes at each N x 4096 code boundary.

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

electrical characteristics, DV

= 1.8 V to 5.5 V; AV

= 2.7 V to 5.5 V; R

= 2 k

to AGND;

= 200 pF to AGND; all specifications 40

C to 85

C (unless otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE INPUT

Reference current

AVDD = VREFH = 5 V, VREFL = AGND

Reference current

AVDD = VREFH = 3.6 V, VREFL = AGND

VREFH input range

VREFH>VREFL

AVDD

VREFL input range

100

AGND

100

Reference input impedance

100

LOGIC INPUTS (see Note 2)

Input current

VINL, input low voltage

DVDD = 1.8 V to 5.5 V

0.3

DVDD

VINH, input high voltage

DVDD = 1.8 V to 5.5 V

0.7

DVDD

Pin input capacitance

POWER REQUIREMENTS

DVDD

1.8

5.5

DIDD

DAC active and excluding load current,
VIH = DVDD and VIL = DGND

0.2

1.0

AVDD

2.7

5.5

AIDD (normal operation)

DAC

l di

AVDD = 3.6 V to 5.5 V

DAC active and excluding load current,
VIH = DVDD and VIL = DGND

250

400

AVDD = 2.7 V to 3.6 V

VIH = DVDD and VIL = DGND

240

390

AIDD (all power-down modes)

AVDD = 3.6 V to 5.5 V

and V

DGND

0.2

AVDD = 2.7 V to 3.6 V

VIH = DVDD and VIL = DGND

0.05

POWER EFFICIENCY

IOUT/AIDD

I(LOAD) = 2 mA, AVDD = +5 V

89%

NOTE 2; Assured by design and characterization, not production tested.

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

PBS PACKAGE

(TOP VIEW)

31 30 29 28 27

9 10

OUT

Sense

AGND
V

REF

DGND

DB15
DB14
DB13
DB12

DB11

DB10

DB9
DB8

11 12 13 14 15

DB7

DB6

DB5

DB4

DB1

R/W

LDAC

RST

RSTSEL

BTC/USB

PD1

PD0

DB0

DB3

DB2

DAC8541

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

DB15DB0

116

I/O

Data input/output, (pin 1-MSB: pin 16-LSB)

DGND

Digital ground

DVDD

Digital supply input, 1.8 V to 5.5 V

AVDD

Analog power supply input, 2.7 V to 5.5 V

VREFH

Positive reference voltage input (referenced to AGND)

VREFL

Negative reference voltage input (referenced to AGND), nominally VREFL = AGND

AGND

Analog ground

VOUTSense

Analog output sense. The feedback terminal of the output amplifier.

VOUT

Analog output voltage from DAC. The output amplifier has rail-to-rail operation.

PD0

Powerdown control bit 0

PD1

Powerdown control bit 1

BTC/USB

Data input format: binary twos complement or unipolar straight binary

RSTSEL

Reset VOUT on active RST to min-scale (RSTSEL = 0) or mid-scale (RSTSEL = 1)

RST

VOUT reset to min-scale or mid-scale, rising edge (Does not reset input register data.)

LDAC

Asynchronous load command, rising edge

R/W

Read/Write control input

Chip select, active low

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

timing characteristics, DV

= 1.8 V to 5.5 V; AV

= 2.7 V to 5.5 V; R

= 2 k

to AGND;

= 200 pF to AGND; all specifications 40

C to 85

C (unless otherwise noted)

MIN

TYP

MAX

UNIT

tw1

Pulse width: CS low for valid write

tsu1

Setup time: R/W low before CS falling (see Note 4)

tsu2

Setup time: data in valid before CS falling

th1

Hold time: R/W low after CS rising (see Note 4)

th2

Hold time: data in valid after CS rising

tw2

Pulse width: CS low for valid read

tsu3

Setup time: R/W high before CS falling

td1

Delay time: data out valid after CS falling

th3

Hold time: R/W high after CS rising

th4

Hold time: data out valid after CS rising

tsu4

Setup time: LDAC rising after CS falling (see Note 4)

td2

Delay time: CS low after LDAC rising

tw3

Pulse width: LDAC low

tw4

Pulse width: LDAC high

tw5

Pulse width: CS high (see Note 4)

tsu5

Setup time: RSTSEL valid before RST rising

th5

Hold time: RSTSEL valid after RST rising

tw6

Pulse width: RST low

tw7

Pulse width: RST high

VOUT Settling time (settling time for a full scale code change)

NOTE 4: Simplified operation: CS and W/R can be tied low if the DAC8541 is the only device on the bus and Read operation is not needed. In

this case, LDAC is still required to update the output of the DAC and tsu(4) is from Data In Valid to LDAC Rising.

tw1

tw5

tw2

tsu1

th1

tsu3

th3

th4

tsu2

th2

td1

tsu4

td2

tw4

tw3

0.003% of FSR Error Bands

Data Out Valid

Data In Valid

R/W

Data I/O

DB0DB15

LDAC

VOUT

Figure 1. Data Read/Write Timing

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

tsu5

th5

tw6

tw7

VOUT

RST

RSTSEL

+FS

(RSTSEL = Low)

+FS

FS

(RSTSEL = High)

Min-Scale

Mid-Scale

Figure 2. Reset Timing

TYPICAL CHARACTERISTICS

This condition applies to all typical characteristics: V

REF

H = AV

, V

REF

L = AGND, T

= 25

C (unless

otherwise noted)

64

48

32

16

Linearity Error

LSB

Digital Input Code

LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR

DIGITAL INPUT CODE

1.5

0.5

1.5

8192

16384

24576

32768

40960

49152

57344

65535

Differential Linearity Error

LSB

AVDD = 2.7 V, TA = 85

Figure 3

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

TYPICAL CHARACTERISTICS

Figure 6

TA Free-Air Temperature 

Zero-Scale Error

ZERO-SCALE ERROR

FREE-AIR TEMPERATURE

AVDD = VREF = 5 V

AVDD = VREF = 2.7 V

Figure 7

TA Free-Air Temperature 

Full-Scale Error

FULL-SCALE ERROR

FREE-AIR TEMPERATURE

AVDD = 5 V

AVDD= 2.7 V

To Avoid Clipping of The Output Signal
During The Test, VREF = AVDD 10mV

Figure 8

0.5

1.5

2.5

DAC Loaded With 0000h

DAC Loaded With FFFFh

AVDD = VREF = 2.7 V

I(SOURCE/SINK) Drive Current Capability mA

Output V

oltage

OUTPUT VOLTAGE

DRIVE CURRENT CAPABILITY

OUT

Figure 9

DAC Loaded With 0000h

DAC Loaded With FFFFh

AVDD = VREF = 5 V

I(SOURCE/SINK) Drive Current Capability mA

Output V

oltage

OUTPUT VOLTAGE

DRIVE CURRENT CAPABILITY

OUT

Figure 10

200

220

240

260

280

300

2.7

3.1

3.5

3.9

4.3

4.7

5.1

5.5

AVDD Analog Supply Voltage V

Analog Supply Current

ANALOG SUPPLY CURRENT

ANALOG SUPPLY VOLTAGE

Figure 11

1000

500

100

150

200

250

Frequency

1500

2000

AIDD HISTOGRAM

2500

300

350

400

AIDD 

AVDD = 5 V
TA = 25

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

TYPICAL CHARACTERISTICS

Figure 12

1000

500

100

150

200

250

Frequency

1500

2000

AIDD HISTOGRAM

2500

300

350

400

AIDD 

AVDD = 2.7 V
TA = 25

Figure 13

100

150

200

250

300

350

400

16384

32768

49152

65535

Digital Input Code

Analog Supply Current

ANALOG SUPPLY CURRENT

DIGITAL INPUT CODE

AVDD = DVDD = 5 V

AVDD = DVDD = 2.7 V

Excluding Reference and Load Current.

Figure 14

100

150

200

250

300

350

AVDD = DVDD = 5 V

AVDD = DVDD = 2.7 V

Excluding Reference and Load Current.

TA Free-Air Temperature 

Analog Supply Current

ANALOG SUPPLY CURRENT

FREE-AIR TEMPERATURE

Figure 15

2.7

3.4

4.1

4.8

5.5

TA = 85

TA = 40

TA = 25

AVDD Supply Voltage V

Power-Down Current

POWER-DOWN CURRENT

SUPPLY VOLTAGE

Figure 16

DVDD = 2.7 V

100

200

300

400

500

DIDD Values are Shown for Logic

Level Change on one Digital Input.

DVDD = 5 V

VLOGIC Logic Input Voltage V

Digital Supply Current

DIGITAL SUPPLY CURRENT

LOGIC INPUT VOLTAGE

Figure 17

t Time 

100 200 300400 500 600

POWER-ON RESET TO 0 V

700 800 900 1000

Loaded With 2 k

to AGND

AVDD (2 V/div)

VOUT (1 V/div)

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

TYPICAL CHARACTERISTICS

Figure 18

12 14

18 20

Scope Trigger (5 V/div)

OUT

(2 V/div)

t Time 

EXITING POWER-DOWN

= V

REF

= 2.7 V

Digital Code = 8000h

Figure 19

MAJOR CARRY CODE CHANGE GLITCH

t Time 

0.5

1 1.5

2.5

Output V

oltage

20 mV/div

3.5

4.5

OUT

= DV

= V

REF

= 2.7 V

Code 8000

to 7FFF

Glitch Occurs Every N

4096 Code

Boundary.

Figure 20

Output V

oltage

50 mV/div

OUT

t Time 

0.5

1 1.5

2.5

3.5

4.5

MAJOR CARRY CODE CHANGE GLITCH

= DV

= V

REF

= 5 V

Code 8000

to 7FFF

Glitch Occurs Every N

4096 Code

Boundary.

Figure 21

t Time 

FULL-SCALE SETTLING TIME

18 20

= 2.7 V

Large-Signal Output (1 V/div)

Full-Scale Code Change:

0000

to FFFF

Output Loaded With

2 k

and 200 pF to AGND

Scope Trigger (5 V/div)

Small-Signal Error (1 mV/div)

Figure 22

t Time 

FULL-SCALE SETTLING TIME

18 20

= 2.7 V

Small-Signal Error (1 mV/div)

Full-Scale Code Change:

FFFF

to 0000

Output Loaded With

2 k

and 200 pF to AGND

Scope Trigger (5 V/div)

Large-Signal Output (1 V/div)

Figure 23

t Time 

HALF-SCALE SETTLING TIME

18 20

= 2.7 V

Large-Signal Output (1 V/div)

Small-Signal Error (1 mV/div)

Half-Scale Code Change:

4000

to C000

Output Loaded With

2 k

and 200 pF to AGND

Scope Trigger (5 V/div)

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

TYPICAL CHARACTERISTICS

Figure 24

t Time 

HALF-SCALE SETTLING TIME

14 16 18

Large-Signal Output (1 V/div)

Small-Signal Error (1 mV/div)

Half-Scale Code Change:

C000

to 4000

Output Loaded With

2 k

and 200 pF to AGND

Scope Trigger (5 V/div)

= 2.7 V

Figure 25

t Time 

FULL-SCALE SETTLING TIME

18 20

= 5 V

Large-Signal Output (2 V/div)

Small-Signal Error (1 mV/div)

Full-Scale Code Change:

0000

to FFFF

Output Loaded With

2 k

and 200 pF to AGND

Scope Trigger (5 V/div)

Figure 26

t Time 

FULL-SCALE SETTLING TIME

18 20

Full-Scale Code Change:

FFFF

to 0000

Output Loaded With

2 k

and 200 pF to AGND

Scope Trigger (5 V/div)

= 5 V

Large-Signal Output (2 V/div)

Small-Signal Error (1 mV/div)

Figure 27

t Time 

HALF-SCALE SETTLING TIME

14 16 18

Large-Signal Output (1 V/div)

Small-Signal Error (1 mV/div)

Half-Scale Code Change:

4000

to C000

Output Loaded With

2 k

and 200 pF to AGND

Scope Trigger (5 V/div)

= 5 V

Figure 28

t Time 

HALF-SCALE SETTLING TIME

14 16 18

Large-Signal Output (1 V/div)

Small-Signal Error (1 mV/div)

Half-Scale Code Change:

C000

to 4000

Output Loaded With

2 k

and 200 pF to AGND

Scope Trigger (5 V/div)

= 5 V

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

THEORY OF OPERATION

D/A section

The architecture of the DAC8541 consists of a string DAC followed by an output buffer amplifier. Figure 29
shows a generalized block diagram of the DAC architecture.

REF+

Resistor

String

REF

VREFL = AGND

DAC Register

VOUT

VOUTSense

VREFH = External Reference Voltage

Figure 29. Generalized DAC Architecture

The input coding to the DAC8541 is set by the BTC/USB input to the device. When this input is high, the input
code is binary 2s complement. If the input is low, the format is unipolar straight binary, in which case the ideal
output voltage is given by:

OUT

REF

65536

Where D = the decimal equivalent of the binary code that is loaded to the DAC register, which can range from
0 to 65535 and V

REF

L = AGND.

RDIVIDE

To Output Amplifier
(2x Gain)

VREFH

VREFL

VREFH

Figure 30. Typical Resistor String

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

THEORY OF OPERATION

resistor string

The resistor string section is shown in Figure 30. It is simply a string of resistors, each of which has a value of
R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This
voltage is then presented to the output amplifier by closing one of the switches connecting the string to the
amplifier. The negative tap of the resistor string, V

REF

L, can be tied to AGND or a small voltage can be applied

in order to make minor adjustments to the offset seen at the V

OUT

pin. (This is discussed in more detail in the

voltage reference inputs section.)

output amplifier

The output buffer amplifier is capable of generating near rail-to-rail voltages on its output, which gives an output
range of 0 V to AV

(offset and gain errors affect the absolute V

OUT

range). It is also capable of driving a load

of 2 k

in parallel with 1000 pF to AGND while remaining stable. The source and sink capabilities of the output

amplifier can be seen in the typical curves. The slew rate of the DAC8541 is typically 1 V/

s with a typical

full-scale settling time of 8

For additional functionality, the inverting input of the output amplifier is brought out via the V

OUT

Sense pin. This

allows for better accuracy in critical applications by tying the V

OUT

Sense and V

OUT

together directly at the load.

Other signal conditioning circuitry may also be connected between these points for specific applications.

parallel interface

The DAC8541 provides a 16-bit parallel interface and supports both writing to and reading from the DAC input
register. (See the timing characteristics section for detailed information for a typical write or read command.)

In addition to the data, CS, and R/W inputs, the DAC8541's interface also provides powerdown, LDAC, data
format, and reset/reset-select control. Tables 1 and 2 show the control signal actions and data format,
respectively. These features are discussed in more detail in the remaining sections.

Table 1. DAC8541 CONTROL SIGNAL SUMMARY

R/W

BTC/USB

LDAC

RST

RSTSEL

PD1

PD0

ACTION

Device data I/O is disabled on the bus.

H,L

Write initiated, present input data to the bus.

H,L

Read initiated, data from input register is presented to data bus.

H,L

Input data is latched when writing to the device.

H,L

Data from input register is transferred to DAC register and VOUT is
updated.

Input/output data format is unipolar straight binary.

Input/output data format is binary 2s complement.

DAC register and VOUT reset to min-scale. (If DAC is powered down
during reset, DAC register resets and VOUT will settle to min-scale
upon power up.)

DAC register and VOUT reset to mid-scale. (If DAC is powered down
during reset, DAC register resets and VOUT will settle to mid-scale
upon power up.)

Powerdown device, VOUT impedance equals 1 k

to AGND

Powerdown device, VOUT impedance equals 100 k

to AGND

Powerdown device, VOUT impedance equals high impedance

Only disables 16-bit data I/O interface. Other control lines remain active.

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

THEORY OF OPERATION

data format

Table 2 details the input data format of the DAC8541. Two data I/O formats are available to the host interface.
These two formats are binary 2s complement (BTC) and unipolar straight binary (USB). The BTC/USB input
pin controls the format used by the DAC. The data format selected by the BTC/USB input is used for data written
into the device as well as data that is read back from the DAC8541. (Refer to Table 1 and Figure 1 for additional
information for performing read and write operations.)

Table 2. DAC8541 Data Format

BTC/USB = 0

BTC/USB = 1

UNIPOLAR STRAIGHT BINARY

BINARY 2s COMPLEMENT

DIGITAL INPUT

ANALOG OUTPUT

DIGITAL INPUT

ANALOG OUTPUT

0x0000h

Min-scale

0x8000h

Min-scale

0x0001h

Min-scale + 1 LSB

0x8001h

Min-scale + 1 LSB

0x8000h

Mid-scale

0x0000h

Mid-scale

0x8001h

Mid-scale + 1 LSB

0x0001h

Mid-scale + 1 LSB

0xFFFFh

Full Scale

0x7FFFh

Full Scale

LDAC function

The DAC8541 is designed using a double-buffered architecture. A write command transfers data from the data
input pins into the input register. The data is held in the input register until a rising edge is detected on the LDAC
input. This rising edge signal transfers the data from the input register to the DAC register. Upon issuance of
the rising LDAC edge, the output of the DAC8541 begins settling to the newly written data value presented to
the DAC register.(Data in the input register is not changed when an LDAC command is given.)

RST and RSTSEL

The RST and RSTSEL inputs control the reset of the DAC register and consequently, the DAC output. The reset
command is edge triggered by a low-to-high transition on the RST pin. Once a rising edge on RST is detected,
the DAC output may settle to the mid-scale or min-scale code depending on the state of the RSTSEL input. A
logic high value on RSTSEL causes the DAC output to reset to mid-scale and a logic low value resets the DAC
to min-scale. Application of a valid reset signal to the DAC does not overwrite existing data in the input register.

power-on reset

The DAC8541 contains a power-on reset circuit that controls the output voltage during power up. On power up,
the DAC register (and DAC output) is set to min-scale (plus a small offset error produced by the output buffer).
It remains at min-scale until a valid write sequence is made to the DAC changing the DAC register data. This
is useful in applications where it is important to know the state of the output of the DAC while the system is in
the process of powering up. DGND must be applied to all digital inputs until the digital and analog supplies are
applied to the DAC8541. Logic voltages applied to the input pins when power is not applied to DV

and AV

may power the device through the ESD input structures causing undesired operation.

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

THEORY OF OPERATION

power-down modes

The DAC8541 utilizes four modes of operation. These modes are programmable via two inputs (PD1 and PD0)
to the device. Table 3 shows how the state of these pins correspond to the mode of operation of the DAC8541.

Table 3. Modes of Operation for the DAC8541

PD1

PD0

OPERATING MODE

Normal operation

POWER-DOWN MODES

1 k

to AGND

100 k

to AGND

High impedance

When both pins are set to 0, the device works normally with its typical power consumption of 250

A at

= 5 V. However, for the three power-down modes, the supply current falls to 200 nA at AV

= 5 V (50 nA

at AV

= 3 V). Not only does the supply current fall, but the V

OUT

terminal is internally switched from the output

of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the
device is known while in power-down mode. There are three different options: The output is connected internally
to AGND through a 1-k

resistor, it is connected to AGND through a 100-k

resistor, or it is left open-circuited

(high impedance). The output stage is illustrated in Figure 31.

DAC

Powerdown

Circuitry

Amplifier

Resistor
Network

VOUT

VOUTSense

Figure 31. Output Stage During Power Down (High-Impedance)

All analog circuitry is shut down when a power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. This allows the DAC's output voltage to return to the previous level
when power-up resumes. The delay time required to exit power-down is typically 2.5

s for AV

= 5 V and 5

s for AV

= 3 V. (See the typical curves section for additional information.)

voltage reference inputs

Two voltage inputs provide the reference set points for the DAC architecture. These are V

REF

and V

REF

L. For

typical rail-to-rail operation, V

REF

should be equivalent to AV

and V

REF

L tied to AGND. The output voltage

is given by:

OUT

REF

The use of the V

REF

L input allows minor adjustments to be made to the offset of the DAC output by applying

a small voltage to the V

REF

L input. The acceptable range is between 100 mV and 100 mV with respect to

AGND. A low output impedance source is needed, so that the accuracy of the DAC over its operating range is
not affected.

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

THEORY OF OPERATION

analog and digital supplies

The DAC8541 utilizes two separate supplies for operation. The analog supply (AV

) powers the output buffer

and DAC while the digital supply (DV

) sets the I/O voltage thresholds. Refer to the device specification table

for additional information. AV

can operate from 2.7 V to 5.5 V while DV

can independently function from

1.8 V to 5.5 V. The control and data I/O thresholds are determined by DV

and are given in the electrical

characteristics section.

APPLICATION INFORMATION

host processor interfacing

DAC8541 to MSP430 microcontroller

Figure 32 shows a typical parallel interface connection between the DAC8541 and a MSP430 microcontroller.
The setup for the interface shown uses ports 4 and 5 of the MSP430 to send or receive the 16-bit data while
bits 07 of port 2 provides the control signals for the DAC. When data is to be transmitted to the DAC8541, the
data is made available to the DAC via P4 and P5 and P2.1 is taken low. The MSP430 then toggles P2.0 from
high-to-low and back to high, transferring the 16-bit data to the DAC. This data is loaded into the DAC register
by applying a rising edge to P2.4. The remaining five I/O signals of P2 shown in the figure control the reset,
power-down, and data format functions of the DAC. Depending on the specific requirements of a given
application, these pins may be tied to DGND or DV

, enabling the desired mode of operation.

8 Bits

16 Bits

D[15:0]

R/W

RST

RSTSEL

LDAC

PD0

PD1

BTC/USB

VREFL

DGND

AVDD

DVDD

VOUTSENSE

VOUT

VREFH

AGND

(Other Connections Omitted for Clarity)

0.1

1 to 10

0.1

AVDD

DVDD

VOUT

VREF

P4[0:7]

P5[0:7]

P2:0

P2:1

P2:2

P2:3

P2:4

P2:5

P2:6

P2:7

MSP430F149

DAC8541

Figure 32. DAC8541 to MSP430 Microcontroller

DAC8541 to TMS320C5402 DSP

Figure 33 shows the connections between the DAC8541 and the TMS320C5402 digital signal processor. Data
is provided via the parallel data bus of the DSP while the DAC's CS control input is derived from the decoded
I/O strobe signal. The IOSTRB in addition to the R/W and XF(I/O) signals control the data transmission to and
from the DAC as well as the LDAC control. With additional decoding, multiple DAC8541's can be connected
to the same parallel data bus of the DSP.

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

APPLICATION INFORMATION

16 Bits

D[15:0]

R/W

LDAC

VREFL

DGND

AVDD

DVDD

VOUTSENSE

VOUT

VREFH

AGND

(Other Connections Omitted for Clarity)

0.1

1 to 10

0.1

AVDD

DVDD

VOUT

VREF

D[15:0]

A[23:0]

IOSTRB

R/W

XF(I/O)

TMS320C5402

DAC8541

Address
Decoder

Figure 33. DAC8541 to TMS320 DSP

bipolar operation using the DAC8541

The DAC8541 has been designed for single-supply operation but a bipolar output range is also possible using
the circuit shown in Figure 34. The circuit allows the DAC8541 to achieve an analog output range of

5 V.

Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier.

Setting BTC/USB = 1, sets the DAC into binary 2s complement I/O format for the bipolar V

OUT

configuration.

When operated with BTC/USB set high, the output voltage for any input code can be calculated as follows:

OUT

REF

65536

)

REF

R2
R1

where D represents the input code in decimal, unipolar straight binary (065535) and V

REF

L = AGND.

With V

REF

H = 5 V, R

= R

= 10 k

OUT

65536

5 V

This is an output voltage range of

5 V with 8000h corresponding to a 5 V output and 7FFFh corresponding

to a 5 V output. Bipolar zero is given by 0000h applied to the DAC.

VOUT

VOUTSense

VREFH

VREFL

R1 = 10 k

5 V

R2 = 10 k

5 V

DAC8541

0.1

5 V

(Other Pins Omitted for Clarity)

OPA703

Figure 34. Bipolar Operation With the DAC8541

DAC8541

SLAS353 DECEMBER 2001

www.ti.com

APPLICATION INFORMATION

layout

A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies. The following measures should be taken to assure optimum performance of the DAC8541.

The DAC8541 offers dual-supply operation, as it can often be used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design
and the higher the switching speed, the more important it becomes to separate the analog and digital ground
and supply planes at the DAC.

Because the DAC8541 has both analog and digital ground pins, return currents can be better controlled and
have less effect on the DAC's output error. Ideally, AGND would be connected directly to an analog ground plane
and DGND to the digital ground plane. The analog ground plane would be separate from the ground connection
for the digital components until they were connected at the power entry point of the system.

The power applied to AV

and V

REF

H (this also applies to V

REF

L if not tied to AGND) should be well-regulated

and low-noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes
riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their
internal logic switches states. This noise can easily couple into the DAC output voltage through various paths
between the power connections and analog output.

As with the AGND connection, AV

should be connected to a 5-V power supply plane or trace that is separate

from the connection for digital logic until they are connected at the power entry point. In addition, the 1-

F to

10-

F and 0.1-

F bypass capacitors are strongly recommended. In some situations, additional bypassing may

be required, such as a 100-

F electrolytic capacitor or even a Pi filter made up of inductors and capacitors--all

designed to essentially lowpass filter the AV

supply, removing the high frequency noise.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding thirdparty products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

2002, Texas Instruments Incorporated

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC8541Y/250

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC8541Y/250