DAC

858

Burr Brown Products
from Texas Instruments

FEATURES

DESCRIPTION

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM OF DAC8580

DAC8580

Serial Interface

Shift Register

Control

Logic

DIN

SCLK

FSYNC

DAC

Latch

DAC

OSR2

OSR1

Digital Filter

)

(

)

(

AGND

DGND

REF

MUTEB

OUT

BPB

RSTB

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

16-BIT, HIGH-SPEED, LOW-NOISE, VOLTAGE OUTPUT,

DIGITAL-TO-ANALOG CONVERTER

16-Bit Monotonic

The DAC8580 is a 16-bit, high-speed, low-noise,
voltage-output

DAC

designed

for

waveform

±5-V Rail-to-Rail Output

generation applications. It operates from dual ±5-V

Fast Settling: 0.65 µs

power supplies and requires only a single external

Fast Slew Rate: 35 V/µs

reference. The DAC8580 is capable of generating

Low Noise: 20 nV/

output signal frequencies up to 1 MHz. The DAC8580
significantly relaxes, or removes, the

need

for

Low Glitch Energy: 0.5 nV-s

external de-glitchers, analog filters and high-swing

Low Power-On Transient

output buffers. It incorporates a programmable digital

On-Chip Digital Low-Pass Filter

interpolation filter capable of oversampling the input
word rate by 2, 4, 8, or 16. The digital filter can be

Programmable Oversampling

bypassed on-the-fly, or can be permanently turned

16-MSPS Update Rate (Filter On)

off. The fast 30-MHz serial interface is compatible

30-MHz Serial Interface

with right-justified digital audio format. The DAC8580
is specified from 40°C to 85°C.

1.8-V to 5.5-V Logic Compatible

TSSOP-16 Package

Waveform Generation

CRT Projection TV Digital Convergence

Automated Test Equipment

Industrial Process Control

Music Synthesis

Ultrasound

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS

(1)

ELECTRICAL CHARACTERISTICS

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications. This device is rated at 1500 V HBM and 1000
V CDM.

PACKAGE/ORDERING INFORMATION

(1)

PRODUCT

PACKAGE

SPECIFICATION

PACKAGE

ORDERING

TRANSPORT MEDIA

DRAWING

TEMPERATURE

MARKING

NUMBER

RANGE

DAC8580IPW

90-Piece Tube

DAC8580

16-TSSOP

40°C TO +85°C

D8580I

DAC8580IPWR

2000-Piece Tape and Reel

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at

www.ti.com

or DV

to AV

0.3 V to 12 V

Digital input voltage to AV

0.3 V to 12 V

OUT

or V

REF

to AV

0.3 V to 12 V

DGND and AGND to AV

0.3 V to 6 V

Operating temperature range

40°C to +85°C

Storage temperature range

65°C to +150°C

Junction temperature range (T

max)

+150°C

Power dissipation:

Thermal impedance (

)

118°C/W

Thermal impedance (

)

29°C/W

Lead temperature, soldering:

Vapor phase (60 s)

215°C

Infrared (15 s)

220°C

(1)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.

All specifications at T

= T

MIN

to T

MAX

, +AV

= +5 V, AV

= 5 V, DV

= +5 V, V

REF

= 4.096 V, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

STATIC PERFORMANCE

Resolution

Bits

Linearity error

±0.05

% FSR

Differential linearity error

±0.25

±1

LSB

Gain error

% FSR

Gain drift

±3

ppm/°C

Bipolar zero error

REF

= 4.096 V

Bipolar zero drift

From 40°C to +85°C

±20

µV/°C

Total drift

From 40°C to +85°C

±8

ppm/°C

OUTPUT CHARACTERISTICS

Voltage output range

= 6 V, AV

= 6 V, V

REF

= 5.5 V

5.5

Maximum current drive capability

At full speed, driving resistive load

(1)

±25

Output Impedance

(1)

Sourcing and sinking dc currents larger than 25 mA is not recommended.

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DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T

= T

MIN

to T

MAX

, +AV

= +5 V, AV

= 5 V, DV

= +5 V, V

REF

= 4.096 V, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

<200 pF, R

= 2 k

, to 0.1% FS, 8-V step

0.35

0.65

Settling time (large signal)

µs

To 0.003% FS, 8-V step

1.0

Settling time (small signal)

To 0.003% FS, 100-mV step

0.15

µs

Slew rate

From 10% to 90% of % FSR

V/µs

Code-to-code glitch impulse

1 LSB change around major carry

Code-to-code glitch energy

1 LSB change around major carry

0.5

nV-s

Limited by slew-boost circuit operation during

100

Overshoot

large-signal swings.

Digital feedthrough

(2)

SCLK toggling

0.5

nV-s

Voltage output noise

Frequency = 100 kHz

nV/

Frequency = 10 kHz

nV/

F = 0.1 Hz to 10 Hz

µVp-p

Power supply rejection

varies ±10%

0.3

mV/V

REFERENCE INPUT CHARACTERISTICS

Reference input voltage range

3.0

Reference input impedance

Reference input capacitance

Reference multiplying bandwidth

Large signal (1 V peak-to-peak)

MHz

Reference multiplying bandwidth

Small signal

MHz

AC CHARACTERISTICS

DAC output signal (sine wave) frequency = 1 kHz,
DAC input update rate = 192 KSPS,

Digital filter is OFF

DAC output signal (sine wave) frequency = 40 kHz,
DAC input update rate = 1 MSPS,

Harmonic distortion

Digital filter oversampling rate = 16

(3)

DAC output signal (sine wave) frequency = 1 kHz,
DAC input update rate = 192 KSPS

100

Software calibrated, digital filter is OFF

(4)

DAC output signal (sine wave) frequency = 1 kHz,
DAC input update rate = 192 KSPS,

Digital filter is OFF

DAC output signal (sine wave) frequency = 40 kHz,
DAC input update rate= 1 MSPS,

Harmonic distortion

Digital filter oversampling rate = 16

(3)

DAC output signal (sine wave) frequency = 1 kHz,
DAC input update rate = 192 KSPS,

100

Software calibrated, digital filter is OFF

(4)

DAC output signal (sine wave) frequency = 1 kHz,
DAC input update rate = 192 KSPS,

Digital filter is OFF

DAC output signal (sine wave) frequency = 40 kHz,

Spurious free dynamic range (SFDR)

DAC input update rate= 1 MSPS,

Digital filter oversampling rate =16

(3)

DAC output signal (sine wave) frequency = 1 kHz,
DAC input update rate = 192 KSPS,

100

Software calibrated, digital filter is OFF

(4)

(2)

Digital feedthrough error is defined as the area of the impulse injected into the analog output from the digital input, during the toggling of
the digital input.

(3)

No analog filter is used. On-chip digital filter is set at oversampling ratio of 16. High-speed digitizer has 10-MHz input bandwidth. This
specification is 100% tested during production.

(4)

Software calibration requires the user to calibrate the linearity error using a precision digitizer and provide the DAC inputs from a lookup
table.

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TIMING CHARACTERISTICS

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T

= T

MIN

to T

MAX

, +AV

= +5 V, AV

= 5 V, DV

= +5 V, V

REF

= 4.096 V, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DAC output signal (sine wave) frequency = 1 kHz,
DAC input update rate = 192 KSPS,

Digital filter is OFF

DAC output signal (sine wave) frequency = 40 kHz,

Total harmonic distortion (THD)

DAC input update rate =1 MSPS,

Digital filter oversampling rate =16

(3)

DAC output signal (sine wave) frequency = 1 kHz,
DAC input update rate = 192 KSPS,

Software calibrated, digital filter is OFF

(4)

DAC output signal is 1-kHz sine wave, 1 dBFS.

Signal to noise ratio (SNR)

110

dBFS

Noise bandwidth is from 0 to 10 kHz.

(5)

Serial clock = 16 MHz,

Maximum output frequency (without external

Digital filter oversampling rate =16

0.2

MHz

analog filter)

THD > 50 dBs, without analog filter

Serial clock = 32 MHz,

Maximum output frequency (with external

Digital filter oversampling rate = 8

(6)

MHz

analog filter)

THD > 50 dBs, with analog filter

Maximum output update rate

MHz

DIGITAL INPUT CHARACTERISTICS

0.7 x DV

GND

0.3 x DV

Input leakage current

±0.05

±1

µA

Input capacitance

Power-on delay

From V

high to CS low

130

µs

POWER SUPPLY CHARACTERISTICS

+AV

4.0

6.0

4.0

1.8

= 5.0 V, AV

= 5.0 V,

REF

= 4.096 V, I

REF

included

TEMPERATURE RANGE

Specified performance

°C

(5)

A precision delta-sigma digitizer is used to make the measurement.

(6)

An oversampling ratio of 16X cannot be supported at 32 MHz clock frequency. 8X oversampling can be used instead to generate a
1-MHz output. To generate output frequencies over 200 kHz, use of analog anti-imaging filters are highly recommended. The DAC8580
digital filter still relaxes the analog filter requirements. At F

OUT

>200 kHz, large-signal waveforms have overshoot/undershoot due to the

settling characteristics of the output amplifiers. Small-signal waveforms don't show this behavior.

At 40°C to 85°C, DV

= +5 V, +AV

= +5 V, AV

= 5 V, unless otherwise noted

(1) (2)

PARAMETER

MIN

MAX

UNIT

sck

SCLK period

wsck

SCLK high or low time

Data setup time (input)

Data hold time (input)

SWF

FSYNC setup time

HWF

FSYNC hold time

Rise time

Fall time

WFUPDAC

Delay from falling edge of FSYNC to loading DAC latch

(3)

1.5

sck

(1)

Specified by design. Not production tested.

(2)

Sample tested during the initial release and after any redesign or process changes that may affect this parameter.

(3)

OUTPUT of pin V

OUT

changes to new level immediately (within settling time) after DAC register is loaded.

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REF

OUT

AGND

BPB

OSR2
OSR1

DGND
RSTB
MUTEB
DV

DGND
FSYNC
SCLK
SDIN

(TOP VIEW)

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

TSSOP PACKAGE

TERMINAL FUNCTIONS

NO.

NAME

DESCRIPTION

REF

Reference input voltage; 3 V to AV

OUT

DAC output voltage; output swing is ±V

REF

Negative analog supply voltage; tie to 5 V

Positive analog supply voltage; tie to +5 V

AGND

Ground reference for analog circuitry of the device

BPB

Active-low, asynchronous digital input for filter bypass

OSR2

Digital input for selecting the oversampling ratio

OSR1

Digital input for selecting the oversampling ratio

DIN

Digital input, serial data

SCLK

Digital input, serial bit clock

FSYNC

Digital input. FSYNC is word clock.

DGND

Ground reference for digital circuitry

Positive digital supply, 1.8-V to 5.5-V compatible

MUTEB

Digital input, actime low, for forcing the output to mid-scale.

RSTB

Filter reset. Active-low, asynchronous digital input for disabling all digital filter activity.

DGND

Must connect to digital ground reference to ensure correct operation.

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RIGHT-JUSTIFIED AUDIO TIMING DIAGRAM

VALUE of WORD-1

DAC

Updated

t HWF

t SWF

New Word

Starts

t WFUPDAC

t SCK

BIT-14,...., 1

BIT-15 (MSB)

BIT-0

SCLK

DIN

t wsck

t hi

t su

t r

t f

BIT-0

BIT-15 (MSB)

BIT-1

BIT-14, ...., 1

WORD-0

WORD-1

WORD-2

New Word

Starts

t WFUPDAC

Temporary

VALUE of WORD-0

PREVIOUS VALUE

changes immediately to new value

FSYNC

changes immediately to new value

** -- New data is transferred to DAC Latch if filter is off;

transferred to filter if filter is on.

DAC Latch or Digital filter input **

TYPICAL CHARACTERISTICS (AVDD = 5 V, AVSS = 5 V, VREF = 4.096 V, unless otherwise

-20

-15

-10

-5

8192

16384

24576

32768

40960

49152

57344

65536

Input Code

LE - LSBs

-0.5

-0.25

0.25

0.5

8192

16384

24576

32768

40960

49152

57344

65536

Input Code

DLE - LSBs

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

The DAC8580 serial interface timing uses a single channel (mono) version of right-justified audio format. The
input data is latched into the device input shift register on the rising edge of SCLK, MSB first. The falling edge of
FSYNC latches the last 16 bits of received data (right-justified) from the shift register into a temporary register,
which connects to either the digital filter or the DAC latch. Data in the temporary register is transferred to the
DAC latch (when digital filter is off), or to the digital filter (when the filter is on) on the second rising SCLK edge
after the falling edge of FSYNC. For operating the digital filter, a continuous SCLK is required.

Figure 1. Timing Diagram

noted)

LINEARITY ERROR

DIFFERENTIAL LINEARITY ERROR

INPUT CODE

Figure 2.

Figure 3.

www.ti.com

-30

-20

-10

3.5

4.5

5.5

INL - LSBs

REF

- Reference Voltage - V

INL max

INL min

= 6 V,

= -6 V

-30

-20

-10

3.5

4.5

5.5

INL - LSBs

INL max

INL min

= -AV

REF

= AV

-0.3 V

- Supply Voltage - V

185

187

189

191

193

-40

-20

- Free-Air Temperature -

Gain Error - mV

= 5 V,

REF

= 4.096 V

-4

-2

-40

-20

- Free-Air Temperature -

Offset Error - mV

= 5 V,

REF

= 4.096 V

-40

-20

- Free-Air Temperature -

I DD

- Supply Current - mA

-25

-23

-21

-19

-17

-15

-13

-11

-40

-20

- Free-Air Temperature -

I SS

- Supply Current - mA

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (AVDD = 5 V, AVSS = 5 V, VREF = 4.096 V, unless otherwise
noted) (continued)

INTEGRAL NONLINEARITY ERROR

VREF

SUPPLY VOLTAGE

Figure 4.

Figure 5.

OFFSET ERROR

GAIN ERROR

TEMPERATURE

Figure 6.

Figure 7.

POSITIVE SUPPLY CURRENT - I

NEGATIVE SUPPLY CURRENT - I

TEMPERATURE

Figure 8.

Figure 9.

www.ti.com

-21

-20.5

-20

-19.5

-32768

-16384

16384

32768

Code

I SS

- Supply Current - mA

13.5

14.5

-32768

-16384

16384

32768

Code

I DD

- Supply Current - mA

t - Time - 50 ns/div

mV - 50 mV/div

t - Time - 1

s/ div

V - 2 V/div

t - Time - 1

s/div

Feedthrough

FSYNC

Glitch

mV - 10 mV/div

100

1 k

100 k

100

1 k

10 k

100 k

10 k

- Output Noise V

oltage -

nV/

f - Frequency - Hz

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (AVDD = 5 V, AVSS = 5 V, VREF = 4.096 V, unless otherwise
noted) (continued)

POSITIVE SUPPLY CURRENT - I

NEGATIVE SUPPLY CURRENT - I

CODE

Figure 10.

Figure 11.

LARGE-SIGNAL SETTLING

SMALL-SIGNAL SETTLING

Figure 12.

Figure 13.

DIGITAL FEEDTHROUGH AND MID-CODE GLITCH

OUTPUT VOLTAGE NOISE

Figure 14.

Figure 15.

www.ti.com

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

2000000

4000000

Gain - dB

f - Frequency - Hz

OSR = 16,
Fclk = 16 MHz,
No Analog Filter Used,
AV

= 6 V,

= -6 V,

REF

= 5 V,

Digitizer F

= 8 MHz

-5

-2.5

2.5

0.00001

0.00002

0.00003

0.00004

0.00005

t - Time - s

- Output V

oltage - V

OSR = 16,
Fclk = 16 MHz,
No Analog Filter Used,
AV

= 6 V,

= -6 V,

REF

= 5 V,

Digitizer F

= 8 MHz

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

2000000

4000000

Gain - dB

f - Frequency - Hz

OSR = 16,
Fclk = 16 MHz,
No Analog Filter Used,
AV

= 6 V,

= -6 V,

REF

= 5 V,

Digitizer F

= 8 MHz

-5

-2.5

2.5

0.00001

0.00002

0.00003

0.00004

0.00005

t - Time - s

- Output V

oltage - V

OSR = 16,
Fclk = 16 MHz,
No Analog Filter Used,
AV

= 6 V,

= -6 V,

REF

= 5 V,

Digitizer F

= 8 MHz

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

2000000

4000000

Gain - dB

f - Frequency - Hz

OSR = 16
Fclk = 16 MHz
No Analog Filter Used
AVDD = 6 V
AVSS = -6 V
VREF = 5 V
Digitizer Fs = 8 MHz

-5

-2.5

2.5

0.00001

0.00002

0.00003

0.00004

0.00005

t - Time - s

- Output V

oltage - V

OSR = 16,
Fclk = 16 MHz,
No Analog Filter Used,
AV

= 6 V,

= -6 V,

REF

= 5 V,

Digitizer F

= 8 MHz

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (AVDD = 5 V, AVSS = 5 V, VREF = 4.096 V, unless otherwise
noted) (continued)

SINE WAVE OUTPUT

POWER SPECTRAL DENSITY

Fo = 30 kHZ

Fo = 30 kHz

Figure 16.

Figure 17.

SINE WAVE OUTPUT

POWER SPECTRAL DENSITY

Fo = 50 kHz

Figure 18.

Figure 19.

SINE WAVE OUTPUT

POWER SPECTRAL DENSITY

Fo = 100 kHz

Figure 20.

Figure 21.

www.ti.com

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

2000000

4000000

Gain - dB

f - Frequency - Hz

OSR = 16,
Fclk = 16 MHz,
No Analog Filter Used,
AV

= 6 V,

= -6 V,

REF

= 5 V,

Digitizer F

= 8 MHz

-5

-2.5

2.5

0.00001

0.00002

0.00003

0.00004

0.00005

t - Time - s

- Output V

oltage - V

OSR = 16,
Fclk = 16 MHz,
No Analog Filter Used,
AV

= 6 V,

= -6 V,

REF

= 5 V,

Digitizer F

= 8 MHz

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

2000000

4000000

Gain - dB

f - Frequency - Hz

OSR = 16,
Fclk = 16 MHz,
No Analog Filter Used,
AV

= 6 V,

= -6 V,

REF

= 5 V,

Digitizer F

= 8 MHz

-5

-2.5

2.5

0.00001

0.00002

0.00003

0.00004

0.00005

t - Time - s

- Output V

oltage - V

OSR = 16,
Fclk = 16 MHz,
No Analog Filter Used,
AV

= 6 V,

= -6 V,

REF

= 5 V,

Digitizer F

= 8 MHz

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

2000

4000

6000

Gain - dB

f - Frequency - Hz

Fo = 1 kHz,
Fclk = 192 KSPS,
OSR = 1,
THD = -71 dB,
SNR = 113 dBFS,
Digitizer = Delta-Sigma

-80

-60

-40

-20

5000000

10000000

15000000

20000000

THD

THD and SFDR - dB

Clock Frequency - Hz

SFDR, Dominated by Images or 3rd Harmonic

OSR = 16,
Fo = 20 kHz,
No Analog Filter Used

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (AVDD = 5 V, AVSS = 5 V, VREF = 4.096 V, unless otherwise
noted) (continued)

SINE WAVE OUTPUT

POWER SPECTRAL DENSITY

Fo = 150 kHz

Figure 22.

Figure 23.

SINE WAVE OUTPUT

POWER SPECTRAL DENSITY

Fo = 200 kHz

Figure 24.

Figure 25.

POWER SPECTRAL DENSITY

TOTAL HARMONIC DISTORTION

FROM DC TO 6 kHz

AND SPURIOUS FREE DYNAMIC RANGE

CLOCK FREQUENCY

Figure 26.

Figure 27.

www.ti.com

-80

-60

-40

-20

3.5

4.5

5.5

THD

SFDR, Dominated by Images

OSR = 16,
Fo = 20 kHz,
Fclk = 8 MHz,
No Analog Filter Used,
V

ref

= AVDD = -AVSS

THD and SFDR - dB

- Supply Voltage - V

-80

-60

-40

-20

50000

100000

150000

200000

250000

THD

SFDR

THD and SFDR - dB

Output Frequency - Hz

OSR = 16,
No Analog Filter Used

REF

- Reference Voltage - V

-80

-60

-40

-20

3.5

4.5

5.5

THD

SFDR

OSR = 16,
Fo = 100 kHz,
Fclk = 16 MHz,
No Analog Filter Used,
AVDD = 6 V,
AV

= -6 V

THD and SFDR - dB

-4

-3

-2

-1

16384

32768

49152

65536

Input Code

LE - LSBs

After piece-wise linear external calibration

-140

-120

-100

-80

-60

-40

-20

1000

2000

3000

4000

5000

6000

f - Frequency - Hz

Code - dB

Fo = 1 kHz,
Fs = 192 KSPS

After piece-wise linear external calibration.
Filter Off

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

TYPICAL CHARACTERISTICS (AVDD = 5 V, AVSS = 5 V, VREF = 4.096 V, unless otherwise
noted) (continued)

TOTAL HARMONIC DISTORTION

AND SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY

SUPPLY VOLTAGE

Figure 28.

Figure 29.

TOTAL HARMONIC DISTORTION

SOFTWARE-TRIMMED UNIT

AND SPURIOUS FREE DYNAMIC RANGE

LINEARITY ERROR

REFERENCE VOLTAGE

INPUT CODE

Figure 30.

Figure 31.

SOFTWARE-TRIMMED UNIT

POWER SPECTRAL DENSITY

Figure 32.

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THEORY OF OPERATION

LPF

DAC8580

Output

Driver

De-glitcher

I-to-V

Converter

out

DAC

Output Voltage (V

OUT

)

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

The traditional high-speed, voltage-output D/A conversion employs a current-output DAC followed by an I-to-V
conversion amplifier. For voltage waveform generation applications, these components are typically followed by a
sample-and-hold de-glitcher circuit, an analog low-pass filter, and an external buffer to drive low-impedance
loads (see

Figure 33

). Monolithic applications of such traditional architectures suffer from the imperfections of

on-chip sample-and-hold circuits, and the analog filters. Multi-chip applications of this traditional architecture
suffer from voltage drift problems due to the temperature coefficient mismatches between external passive
components and the D/A converter, as well as large circuit size and high cost. DAC8580 is designed to address
the problems of traditional high-speed, high-resolution, voltage-output D/A converters.

Figure 33. Traditional Voltage Output Waveform Generation Circuitry Replaced by a Single DAC8580

The DAC8580 uses a proprietary, inherently monotonic, high-speed, low-glitch, resistor-string architecture,
followed by an on-chip low-noise output amplifier. 16-bit input data is coded in twos-complement format and
transmitted using a 3-wire serial interface (MSB first). The input data is sent to an on-chip digital interpolation
filter. The filter can be programmed to different oversampling rates, it can be bypassed, or it can be totally
disabled. The digital data is then decoded to select a tap voltage of the resistor string. The resistor-string output
is sent to a high-speed, low-noise output amplifier. The output buffer has quasi-rail-to-rail swing capability (within
250-mV range of each rail) on a 600-

, 200-pF load. Loads of 50

or 75

can also be continuously driven as

long as the output current remains within ±25 mA. The DAC8580 reduces the components that are used for
implementing sample-and-hold circuits, analog filters, and output driver amplifiers.

The resistor-string DAC architecture provides low glitch, exceptional differential linearity, and temperature stability
while the output buffer provides fast settling and exceptionally low noise (20 nV/

Hz). The DAC8580 settles well

under 1 µs for large signals. The small-signal settling time is less than 150 ns, which enables (oversampled)
update rates exceeding 6.7 MSPS. If some small-signal settling error can be tolerated, the DAC8580 can update
as fast as 16 MSPS.

Due to the remarkably low glitch energy, the DAC8580 has low harmonic distortion ( 70 dB THD for 1-kHz sine
wave output). When the linearity error of the DAC8580 is calibrated using a lookup table, the THD performance
typically exceeds 98 dBs, without an external S/H circuit.

The DAC8580 needs a low-noise external reference voltage to set its output voltage range. The DAC8580 does
not introduce glitches to the external voltage source. This significantly reduces the crosstalk when a single
external reference is used to supply the reference voltage for multiple devices.

The DAC8580 has a 3-wire serial interface to communicate with a microprocessor or a DSP. The host is not
overloaded by the DAC8580: When the digital filter is on, the host needs only to send 1-out-of-16 data points (for
oversampling rate 16). The digital filter of the DAC8580 can generate the remaining data points digitally, on-chip.
When the digital filter is disabled (bypassed), the DAC8580 operates as a standard, 16-bit, 2-MSPS,
voltage-output DAC. The 1.8-V to 5.5-V digital interface of the DAC8580 enables compatibility with various logic
families.

The DAC8580 uses a high-performance rail-to-rail output buffer capable of driving a 600-

, 200-pF load with fast

1-µs large-signal settling. The buffer has exceptional noise performance (20 nV/

Hz) and fast slew-rate

(35 V/µs). The small-signal settling time is under 150 ns, supporting DAC update rates exceeding 6.7 MSPS.

www.ti.com

Reference Input Voltage (V

REF

)

Power Supply (AV

, AV

, DV

)

SERIAL INTERFACE

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

THEORY OF OPERATION (continued)

On power up, a switching circuitry is used to lower power-on transients. Before power up, the DAC output is
connected to AGND voltage using a 100-k

resistor. During power up, transient output voltages are typically less

than 200 mV. Approximately 30 µs after power up, the output gets set to mid-scale value (power-on reset). This
mid-scale value is around AGND potential within offset error limits.

Table 1. Two's-Complement Data Format

DAC OUTPUT

DIGITAL CODE

BINARY

HEX

+Vref

0111111111111111

7FFF

+Vref/2

0100000000000000

4FFF

0000000000000000

0000

Vref/2

1011111111111111

BFFF

Vref

1000000000000000

8000

The reference input pin VREF is typically tied to a standard 3-V, 4.096-V, or 5-V external reference. Minimum
external reference voltage that can be used is 3 V. A 0.1-µF (or less) bypass capacitor is recommended,
depending on the load-driving capability of the external voltage reference. To reduce crosstalk and improve
settling time, V

REF

pin is internally buffered by a high-performance amplifier. Pin V

REF

has a constant 5-k

impedance to AGND; therefore, a reference driver should be chosen with care. Because the V

REF

pin does not

induce glitches, multiple DAC8580 devices can share a single external reference without crosstalk concerns. In
addition, because the reference pin does not require fast current spikes, the reference voltage generator can be
heavily filtered to improve noise performance without hurting settling or distortion. The output range of the
DAC8580 is equal to ±V

REF

. Pin V

REF

should not be powered before the supply pins. REF3133 and REF3140 are

recommended to set the DAC8580 output range to ±3.3 V and ±4.096 V, respectively. The reference bandwidth
is 10 MHz (small signal) and 3 MHz (large signal).

The DAC8580 uses ±5-V analog power supplies (AV

, AV

) and a 1.8-V to 5.5-V digital supply (DV

). Analog

and digital ground pins (AGND and DGND) are also provided. For low-noise operation, analog and digital power,
and ground pins should be separated. Sufficient bypass capacitors, at least 1 µF, should be placed between
AV

and AV

, AV

and DGND, and DV

and DGND pins. Series inductors are not recommended on the

supply paths. AV

, DV

, AV

, and V

REF

should be applied together. V

REF

must not be applied before AV

and AV

. During power up, all digital inputs and the reference input should be kept at zero volts. If any pin is

brought high before the power supplies, overvoltage protection circuitry turns on.

The DAC8580 serial interface consists of serial data input pin SDIN, bit clock pin SCLK, and word clock pin
FSYNC. The serial interface is designed to support the right-justified (mono) audio format. The serial inputs are
1.8-V to 5.5-V logic compatible.

Data from SDIN pin is continuously clocked into a 16-bit shift register, at each rising edge of SCLK. Falling edge
of the FSYNC latches the shift register data into a 16-bit temporary register. The second rising edge of SCLK
following the falling edge of FSYNC transfers the data stored in the temporary register to the DAC latch when the
digital filter is turned off; when the digital filter is on, data is transferred to the digital filter. That is, DAC data is
updated 1.5 clock cycles after the falling edge of FSYNC when the digital filter is off. The shift register
continuously performs a shift operation; therefore, on the falling edge of the word clock FSYNC, the last 16 bits
received determines the data update (right-justified). Data is received MSB-first. This operation provides a
simplified timing for the digital filter, and enables clock rates exceeding 30 MHz. See the timing diagram for
details.

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DIGITAL FILTER

Data vs time. Third-order comb filtering, quadratic interpolation. Over-sampling ratio = 4.

H(z)

(1)

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

The digital filter removes, or simplifies, the component tolerance and temperature drift requirements of the analog
filter that follows the DAC8580. Thus, the digital filter reduces the system cost, and improves system reliability.
The filter does so at the expense of a 2-input-word delay and some rolloff of the input spectrum, which also is
present for the case of an analog filter. The DAC8580 is not a delta-sigma DAC. No noise shaping is performed,
and there is no out-of-band noise other than the significantly reduced image frequencies. Driving a 600-

load,

the DAC8580 idle channel noise typically exceeds 115 dBs over the audio bandwidth.

For output signals exceeding 200 kHz, an analog anti-imaging filter is recommended.

The digital filter is a third-order comb filter with programmable oversampling ratio, which performs a second-order
interpolation on the input data.

Figure 34

shows the third-order comb filter effect, which is quadratic interpolation (two-frame delay is not shown).

Figure 34. Data vs Time Third-Order Comb Filtering

The digital filter has a two-frame delay, independent of the oversampling rate. It does not exactly preserve the
input samples. However, it has the nice property of outputting the input sample, if two repetitive input frames are
used in a row. It is a finite impulse response (FIR) filter with linear phase, and it does not distort audio phase
relationships. The hardware implementation uses feedback; therefore, it is implemented similar to an infinite
impulse response (IIR) filter. The number of equivalent FIR coefficients depends on the oversampling rate and is
not described in detail. The filter has the following Z-transform and its low-pass frequency response has sinx/x
envelope to the third power.

The filter serves three major purposes:

The first purpose of the filter is to relax the analog filtering requirement by pushing the image frequencies
higher in the spectrum. A single analog RC filter, or no analog filter at all, could work fine. Image frequencies
are a fundamental property of an ideal D/A converter, and they can easily dominate the spurious free
dynamic range (SFDR) for high-frequency output signals. The digital filter helps remove these image
frequencies. Image frequencies appear at the integer multiples of the output data update rate (±) input signal
rate. For example, a 1-MSPS DAC generating a 225-kHz sine wave has image frequencies pop up at 775
kHz, 1.225 MHz, 1.775 MHz, 2.25 MHz, etc. The images for the fifth-harmonic are at 112.5 kHz, 887.5 kHz,
1.125 MHz, 1.887 MHz, etc. This 112.5-kHz image for the fifth harmonic pops up even below the 225 kHz
fundamental. With an oversampling rate of 16, at 16 MSPS, the image frequency for that same fifth harmonic
is pushed back to 16 MHz 5 × 225 kHz = 14.875 MHz, which can be filtered easily with an RC circuit.
The second purpose of the digital filter is to relax the computational burden on the microcontroller unit driving
the DAC8580. At an oversampling rate of 16, the MCU needs to generate only 1-out-of-16 samples; 15
samples out of 16 are computed and generated by the DAC8580 digital filter. Even the input sample itself
gets recomputed into a slightly different value by the filter. This way a high-MIPS (million instructions per
second) MCU or DSP is not required to drive the DAC8580 for continuous waveform generation applications.
A simple microcontroller is sufficient.

www.ti.com

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

The third purpose of the filter is to relax the burden on the DAC8580 output buffer by band limiting the digital
input signal. Analog overshoot is not generated during smooth digital signals (filter on). Moreover, when the
filter is on, the 150-ns small-signal settling time becomes a dominant factor, as opposed to the 1-µs
large-signal settling time. This enables 6.7-MSPS operation with full settling; 16 MSPS is possible if full
settling is not necessary. At output update rates above 6.7 MSPS, the user can trade off image frequencies
with distortion caused by insufficient settling.

When the filter is bypassed (pin BPB connects to DGND), the DAC latch is loaded directly with the value from
the input temporary register. The DAC output changes immediately when the input temporary register is loaded
with the new value. If high-speed signals are needed within smooth signals, the filter bypass feature is useful to
temporarily switch back to 35 V/µs fast slew rate, while the filter is still in operation.

The DAC8580 uses an infinite impulse response (IIR) implementation of the third-order comb filter. This
implementation is stable when there is exactly 16 SCLK rising edges per frame. SCLK should be equally spaced,
continuous, and uninterrupted for proper filtered operation. The particular frame during which the RSTB pulse
makes a low-to-high transition can contain any number of clock cycles, but after that frame, there must be 16
clocks per frame.

For oversampling ratios of 1, 2, 4, 8, and 16, the DAC8580 analog outputs change every 16, 8, 4, 2, and 1 SCLK
rising edges, respectively. For all oversampling ratios, DAC8580 always receives one input data every 16 SCLK
cycles. To perform the low-pass function, the digital filter uses the current input, as well as two previous inputs.
During power up, when three consecutive inputs are not yet available, the current input and two previous inputs
are taken at mid-scale code. The intermediate points between consecutive digital input samples are computed
(interpolated) by the digital filter and sent to the output at a higher update rate determined by the oversampling
ratio.

The digital filter itself can support update rates up to 16 MSPS due to inherent logic delay limitations. Therefore,
the oversampled output update rate of the DAC8580 should not exceed 16 MSPS. For example:

Case 1:

Fsclk = 32 MHz
Din = 32 MHz/16 = 2 MSPS
Vout (OSR = 2) = 4 MSPS
Vout (OSR = 4) = 8 MSPS
Vout (OSR = 8) = 16 MSPS
Vout (OSR =16) = Not allowed, limited by the filter update-rate.

Case 2:

Fsclk = 16 MHz
Din = 16 MHz/16 = 1 MSPS.
Vout (OSR = 2) = 2 MSPS
Vout (OSR = 4) = 4 MSPS
Vout (OSR = 8) = 8 MSPS
Vout (OSR =16) = 16 MSPS

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CONFIGURATION of DIGITAL FILTER

Mute Function (Pin MUTEB)

Oversampling Rate (Pin OSR2, OSR1)

Digital Filter Bypass (Pin BPB)

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

The digital filter is configured through hardware as shown in

Table 2

Table 2. Configuration of Digital Filter

BPB

RSTB

OSR2

OSR1

MUTEB

DESCRIPTION

Don't

OUTPUT CLEAR. The output goes to mid-scale, 1.5 SCLK cycles after falling FSYNC

care

Don't

STANDARD DAC OPERATION (FILTER OFF)

care

DAC output updates with serial data, 1.5 SCLK after falling FSYNC

Don't

FILTER INITIALIZATION

care

Digital filter gets reset. DAC output goes to mid-scale after receiving SCLK rising edge.

Don't

STANDARD DAC OPERATION (FILTER COMPUTES IN THE BACKGROUND)

care

DAC output updates with serial data, 1.5 SCLK after falling FSYNC

2X oversampled OPERATION WITH FILTER ON
DAC output updates with filtered data, 1.5 SCLK after falling FSYNC and every 8

SCLK

thereafter.

4X oversampled OPERATION WITH FILTER ON
DAC output updates with filtered data, 1.5 SCLK after falling FSYNC and every 4

SCLK

thereafter.

8X oversampled OPERATION WITH FILTER ON
DAC output updates with filter data, 1.5 SCLK after falling FSYNC and every 2

SCLK

thereafter.

16X oversampled OPERATION WITH FILTER ON
DAC output updates with filter data, 1.5 SCLK after falling FSYNC and every SCLK thereafter.

Mute function is implemented by setting the DAC output voltage to mid-scale (~0 V). The MUTEB pin is active
low, and is synchronized with the frame. That is, the DAC latch and DAC output are immediately set to mid-scale
during the first update while the MUTEB pin is low. The MUTEB pin works independent of the serial data
transfer, or the digital filter. Neither the serial input, nor the digital filter data get interrupted or get lost while the
output is set at mid-scale with MUTEB. The first DAC update occurring after the MUTEB pin goes high sets the
DAC latch and DAC output to the next desired value. MUTEB pin must be kept at logic low level before power
up.

oversampling rate of the digital filter is set via pins OSR2 and OSR1.

OSR2 OSR1

OVERSAMPLING RATE

The DAC8580 can support these oversampling ratios as long as the oversampled update rate does not exceed
16 MSPS. The oversampling ratio should be set at power up. OSR1 and OSR2 pins must be kept at logic-low
level before power up.

The digital filter can be asynchronously bypassed via pin BPB. When pin BPB is active low, the digital filter is
bypassed. In this case, the DAC latch receives the data from the temporary register, not from the digital filter.
When the series input data is latched into the temporary register from the input shift register, the DAC latch and
DAC output are updated immediately with the new value of the temporary register. When pin BPB is high, digital
filter is not bypassed. The DAC latch is loaded with the output of the digital filter, not with the content of the
temporary register. The digital filter generates the data and transfers it to the DAC latch.

When the digital filter is bypassed, the filter keeps running. A bypass does not disrupt the internal computations
of the digital filter. When the BPB pin goes high, the oversampled operation resumes without any discontinuity of

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Digital Filter Asynchronous Reset (Pin RSTB)

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

the filtered output. The BPB pin multiplexes the DAC input between the filter output and the output of the
temporary register. Certain applications require generation of smooth waveforms, combined with fast edges. A
good example is the CRT positioning signal, where a smooth ramp is followed by a fast blanking pulse. The
digital low-pass filter offers the capability to generate smooth ramp waveforms (with filter on) and fast blanking
pulse (with filter bypassed). The bypass feature offers on-the-fly capability to switch between smooth filtered
operation and high-speed unfiltered operation. The BPB pin must be kept at logic low before power up.

The digital filter equation is invalidated if other than 16 clocks per frame are received. This condition causes
numerical instability; the RSTB pin is used for recovering from such errors without forcing the user to issue a
power-on reset. The RSTB digital input is an active-low, asynchronous filter reset. The RSTB does not reset the
serial interface. Immediately after RSTB becomes low, all filter registers were cleared, all filter clocks are
stopped, all digital filter switching activities are stopped in order to lower switching noise and digital power
consumption. If the digital filter is not needed, the RSTB and BPB pins should both be tied to a logic zero. The
filter reset operation always occurs asynchronously when RSTB = 0. However, the effect of RSTB = 0 at the
DAC output (Vout ~ 0 V) cannot be observed if the SCLK is stopped, or if BPB = 0. Pin RSTB must be kept at
logic low before power up.

The DAC8580 monitors for receipt of 16 clocks per frame and issues an automatic filter reset if other than 16
clocks per frame is received. This auto-reset is synchronized with the FSYNC line.

RSTB

BPB

OPERATION

Conventional DAC operation: Shutdown and disconnect
the digital filter

Filter reset. DAC output becomes ~0 V only if SCLK is
continuously running.

Filter bypass. Conventional DAC operation resumes,
while filter is on.

Filtered operation. DAC outputs filtered data at the
oversampling rate.

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APPLICATION INFORMATION

CRT Projection TV Digital Convergence

WCLK

BVOUT

MUTEB

GHOUT

BHOUT

RVOUT

GVOUT

REF3025

Ref (+5V)

BCLK

RHOUT

Ref (+5V)

V REF

AVSS

DVDD

AGND

DAC8580

V OUT

Serial

Interface Shift

Control

Logic

DIN

FSYNC

Digital

Filter

DAC

Latch

DAC

OSR2

OSR1

DGND

MODE

DAC-1

-5V

DVDD

+5V

V REF

AV SS

AV DD

AGND

DAC8580

V OUT

Serial

Interface Shift

Control

Logic

DIN

SCLK

FSYNC

Digital

Filter

DAC

Latch

DAC

OSR2

OSR1

DGND

MODE

DAC-6

-5V

DVDD

+5V

Ref (+5V)

Digital

Convergence

Controller

0.1

MUTEB

0.1

RSTB

BPB

RSTB

DAC8580

SLAS458B JUNE 2005 REVISED AUGUST 2005

The DAC8580 is an ideal component for the digital convergence units of the three-tube projection TV sets. Digital
convergence applications require the generation of precision voltage waveforms with approximately 150-kHz
bandwidth. Six DAC8580s are needed for one TV set to generate convergence waveforms for horizontal and
vertical red, green, and blue, as seen in

Figure 35

. A single external reference, REF3025, can support all six

DACs. The low temperature drift, low glitch, and low noise of the DAC8580 improve the picture quality and color
drift.

Figure 35. DAC8580 for Projection TV Digital Convergence

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

DAC8580IPW

ACTIVE

TSSOP

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

DAC8580IPWG4

ACTIVE

TSSOP

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

DAC8580IPWR

ACTIVE

TSSOP

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

DAC8580IPWRG4

ACTIVE

TSSOP

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

27-Sep-2005

Addendum-Page 1

IMPORTANT NOTICE

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