www.ti.com

PRODUCT PREVIEW

FEATURES

DESCRIPTION

APPLICATIONS

DAC

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

D10

D11

D12
D13

A0
A1

A
B
C
D

2:4

Decode

SDO

SDI

CLK

DGND

MSB

LDAC

GND

OUT

GND

OUT

GND

OUT

GND

OUT

A B C D

REF

Input

Power-on

Reset

DAC A

DAC B

DAC C

DAC D

DAC A

DAC B

DAC C

DAC D

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

Quad, Current Output, Serial Input 14-Bit Multiplying Digital-to-Analog Converter

Relative Accuracy: 1 LSB Max

The DAC8803 is a quad, 14-bit, current-output digi-
tal-to-analog converter (DAC) designed to operate

Differential Nonlinearity: 1 LSB Max

from a single 2.7 V to 5-V supply.

2-mA Full-Scale Current ±20%,
With V

REF

= ±10 V

The applied external reference input voltage V

REF

0.5-µs Settling Time

determines the full-scale output current. An internal
feedback resistor (R

) provides temperature tracking

Midscale or Zero-Scale Reset

for the full-scale output when combined with an

Four Separate 4-Quadrant Multiplying

external I-to-V precision amplifier.

Reference Inputs

A doubled buffered serial data interface offers

Reference Bandwidth: 10 MHz

high-speed, 3-wire, SPI and microcontroller compat-

Reference Dynamics: -105 dB THD

ible inputs using serial data in (SDI), clock (CLK), and

50-MHz SPITM-Compatible 3-Wire Interface

a chip select (CS). In addition, a serial data out pin

Double Buffered Registers Enable

(SDO) allows for daisy chaining when multiple pack-
ages are used. A common level-sensitive load DAC

Simultaneous Multichannel Update

strobe (LDAC) input allows simultaneous update of all

Internal Power On Reset

DAC outputs from previously loaded input registers.

Compact SSOP-28 Package

Additionally, an internal power on reset forces the
output voltage to zero at system turn on. An MSB pin

Industry-Standard Pin Configuration

allows system reset assertion (RS) to force all regis-
ters to zero code when MSB = 0, or to half-scale
code when MSB = 1.

Automatic Test Equipment

The DAC8803 is packaged in a SSOP package.

Instrumentation

Digitally Controlled Calibration

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the forma-

tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.

www.ti.com

PRODUCT PREVIEW

ABSOLUTE MAXIMUM RATINGS

(1)

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

(1)

MINIMUM

DIFFERENTIAL

SPECIFIED

TRANSPORT

RELATIVE

PACKAGE-

PACKAGE

ORDERING

PRODUCT

NONLINEARITY

TEMPERATURE

MEDIA

ACCURACY

LEAD

DESIGNATOR

NUMBER

(LSB)

RANGE

QUANTITY

(LSB)

DAC8803IDBT

Tape and Reel, 250

DAC8803

±1

-40°C to +85°C

SSOP-28

DAC8803IDBR

Tape and Reel, 2500

(1)

For the most current specifications and package information, see the Package Option Addendum at the end of this document, or see the
TI website at www.ti.com

DAC8803

UNIT

to GND

-0.3 to +8

to GND

-0.3 to -7

REF

to GND

-18 to +18

Logic inputs and output to GND

-0.3 to +8

V(I

OUT

) to GND

-0.3 to V

+ 0.3

GND

X to DGND

-0.3 to +0.3

Input current to any pin except supplies

±50

Package power dissipation

max - T

Thermal resistance,

28-Lead shrink surface-mount (RS-28)

100

°C/W

Maximum junction temperature (T

max)

150

°C

Operating temperature range, Model A

-40 to +85

°C

Storage temperature range

-65 to +150

°C

Lead temperature

RS-28 (Vapor phase 60s)

215

°C

Lead temperature

RS-28 (Infrared 15s)

220

°C

(1)

Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.

www.ti.com

PRODUCT PREVIEW

ELECTRICAL CHARACTERISTICS

(1)

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

= 5 V ± 10%; V

= 0 V, I

OUT

X = Virtual GND, A

GND

X = 0 V, V

REF

A, B, C, D = 10 V, T

= full operating temperature range,

unless otherwise noted.

DAC8803

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

STATIC PERFORMANCE

(2)

Resolution

Bits

Relative accuracy

±1

LSB

Differential nonlinearity

DNL

±1

LSB

Output leakage current

OUT

Data = 0000h, T

= 25°C

OUT

Data = 0000h, T

= T

max

Full-scale gain error

FSE

Data = FFFFh

±0.75

±3

Full-scale tempco

(3)

TCV

ppm/°C

Feedback resistor

= 5 V

REFERENCE INPUT

REF

X Range

REF

-15

Input resistance

REF

Input resistance match

REF

Channel-to-channel

Input capacitance

(3)

REF

ANALOG OUTPUT

Output current

OUT

Data = FFFFh

1.25

2.5

Output capacitance

(3)

OUT

Code-dependent

LOGIC INPUTS AND OUTPUT

Input low voltage

= +2.7 V

0.6

= +5 V

0.8

Input high voltage

= +2.7 V

2.1

= +5 V

2.4

Input leakage current

µA

Input capacitance

(3)

Logic output low voltage

= 1.6 mA

0.4

Logic output high voltage

= 100 µA

INTERFACE TIMING

(3)

(4)

Clock width high

Clock width low

CS to Clock setup

CSS

Clock to CS hold

CSH

Clock to SDO prop delay

Load DAC pulsewidth

LDAC

Data setup

Data hold

Load setup

LDS

Load hold

LDH

SUPPLY CHARACTERISTICS

Power supply range

DD RANGE

2.7

5.5

Positive supply current

Logic inputs = 0 V

µA

(1)

Specifications subject to change without notice.

(2)

All static performance tests (except I

OUT

) are performed in a closed-loop system using an external precision OPA277 I-to-V converter

amplifier. The DAC8803 R

terminal is tied to the amplifier output. Typical values represent average readings measured at 25°C.

(3)

These parameters are specified by design and not subject to production testing.

(4)

All input control signals are specified with t

= t

= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

www.ti.com

PRODUCT PREVIEW

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

ELECTRICAL CHARACTERISTICS (continued)

= 5 V ± 10%; V

= 0 V, I

OUT

X = Virtual GND, A

GND

X = 0 V, V

REF

A, B, C, D = 10 V, T

= full operating temperature range,

unless otherwise noted.

DAC8803

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

= +4.5 V to +5.5 V

µA

= +2.7 V to +3.6 V

2.5

µA

Negative supply current

Logic inputs = 0 V, V

= -5 V

0.001

µA

Power dissipation

DISS

Logic inputs = 0 V

0.025

Power supply sensitivity

= ±5%

0.006

AC CHARACTERISTICS

(5)

Output voltage settling time

To ±0.1% of full-scale,

µs

0.5

Data = 0000h to FFFFh to 0000h

To ±0.006% of full-scale,

µs

Data = 0000h to FFFFh to 0000h

Reference multiplying BW

BW -3 dB V

REF

X = 100 mV

RMS

, Data = FFFF

, C

= 15 pF

MHz

DAC glitch impulse

REF

X = 10 V, Data = 0000h to 8000h to 0000h

nV/s

Feedthrough error

OUT

X/V

REF

Data = 0000h, V

REF

X = 100 mV

RMS

, f = 100 kHz

-70

Crosstalk error

OUT

A/V

REF

Data = 0000h, V

REF

B = 100 mV

RMS

-90

Adjacent channel, f = 100 kHz

Digital feedthrough

CS = 1 and f

CLK

= 1 MHz

nV/s

Total harmonic distortion

THD

REF

= 5 V

, Data = FFFFh, f = 1 kHz

-105

Output spot noise voltage

f = 1 kHz, BW = 1 Hz

nV/

(5)

All ac characteristic tests are performed in a closed-loop system using an OPA627 I-to-V converter amplifier.

www.ti.com

PRODUCT PREVIEW

PIN CONFIGURATIONS

GND

OUT

REF

MSB

CLK

SDI

REF

OUT

GND

OUT

REF

DGND
V

GND

LDAC
SDO
NC
R

REF

OUT

GND

DAC8803

(TOP VIEW)

NC - No internal connection

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

PIN DESCRIPTION

PIN

NAME

DESCRIPTION

1, 14, 15, 28

GND

A, A

GND

B, A

GND

C, A

GND

DAC A, B, C, D Analog ground

2, 13, 16, 27

OUT

A, I

OUT

B, I

OUT

C, I

OUT

DAC A, B, C, D Current output

DAC A, B, C, D Reference voltage input terminal. Establishes DAC A, B, C, D full-scale

3, 12, 17, 26

REF

A, V

REF

B, V

REF

C, V

REF

output voltage. Can be tied to V

4, 11, 18, 25

A, R

B, R

C, R

Establish voltage output for DAC A, B, C, D by connecting to external amplifier output.

MSB

MSB Bit set during a reset pulse (RS) or at system power on if tied to ground or V

Reset pin, active low. Input register and DAC registers are set to all zeros or half scale

code (8000h) determined by the voltage on the MSB pin. Register data = 8000h when
MSB = 1.

Positive power-supply input. Specified range of operation 5 V ±10%.

Chip-select; active low input. Disables shift register loading when high. Transfers shift

CLK

Clock input; positive edge triggered clocks data into shift register

SDI

Serial data input; data loads directly into the shift register.

Not connected; leave floating

Serial data output; input data load directly into shift register. Data appears at SDO, 19

SDO

clock pulses after input at the SDI pin.

Load DAC register strobe; level sensitive active low. Tranfers all input register data to

LDAC

the DAC registers. Asynchronous active low input. See

Table 1

for operation.

GND

High current analog force ground.

Negative bias power-supply input. Specified range of operation -0.3 V to -5.5 V.

DGND

Digital ground.

www.ti.com

PRODUCT PREVIEW

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Logic Input Voltage (V)

= +5.0V

= +2.7V

Supply Current, I

(mA)

102

108

114

100

10k

100k

10M

100M

t
t
e

t
i
o

(
d

)

Bandwidth (Hz)

Time (0.1

s/div)

t
p

l
t
a

(
5

/
d

i
v

)

Trigger Pulse

Voltage Output Settling

Time (0.2

s/div)

t
p

l
t
a

(
5

/
d

i
v

)

Trigger Pulse

Code: 7FFFh to 8000h

Channel A

Graphic

Forthcoming

Graphic

Forthcoming

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V

= +2.7 V (continued)

At T

= +25°C, +V

= +2.7 V, unless otherwise noted.

SUPPLY CURRENT

vs LOGIC INPUT VOLTAGE

REFERENCE MULTIPLYING BANDWIDTH

Figure 25.

Figure 26.

DAC GLITCH

DAC SETTLING TIME

Figure 27.

Figure 28.

LINEARITY ERROR

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Figure 29.

Figure 30.

www.ti.com

PRODUCT PREVIEW

Graphic

Forthcoming

Graphic

Forthcoming

PARAMETER MEASUREMENT INFORMATION

SDI

CLK

LDAC

SDO

CSS

csh

Input REG. LD

lds

LDAC

LDH

D13

D13 D12

D11 D10

CIRCUIT OPERATION

D/A Converter

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

TYPICAL CHARACTERISTICS: V

= +2.7 V (continued)

At T

= +25°C, +V

= +2.7 V, unless otherwise noted.

LINEARITY ERROR

DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE

Figure 51.

Figure 52.

Figure 53. DAC8803 Timing Diagram

The DAC8803 contains four 14-bit, current-output, digital-to-analog converters respectively. Each DAC has its
own independent multiplying reference input. The DAC8803 uses a 3-wire SPI compatible serial data interface,
with a configurable asynchronous RS pin for half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition, an
LDAC strobe enables four channel simultaneous updates for hardware synchronized output voltage changes.

The DAC8803 contains four current-steering R-2R ladder DACs.

Figure 54

shows a typical equivalent DAC.

Each DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The R

X pin

is connected to the output of the external amplifier. The I

OUT

X terminal is connected to the inverting input of the

external amplifier. The A

GND

X pin should be Kelvin-connected to the load point in the circuit requiring the full

14-bit accuracy.

www.ti.com

PRODUCT PREVIEW

OUT

+ *

REF

16384

(1)

RRR

5 k

From Other DACS A

GND

DGND

REF

OUT

GND

Digital interface connections omitted for clarity.
Switches S1 and S2 are closed, V

must be powered.

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

The DAC is designed to operate with both negative or positive reference voltages. The V

power pin is only

used by the logic to drive the DAC switches on and off. Note that a matching switch is used in series with the
internal 5 k

feedback resistor. If users are attempting to measure the value of R

, power must be applied to

in order to achieve continuity. An additional V

bias pin is used to guard the substrate during high

temperature applications to minimize zero-scale leakage currents that double every 10°C. The DAC output
voltage is determined by V

REF

and the digital data (D) according to

Equation 1

Note that the output polarity is opposite to the V

REF

polarity for dc reference voltages.

Figure 54. Typical Equivalent DAC Channel

The DAC is also designed to accommodate ac reference input signals. The DAC8803 accommodates input
reference voltages in the range of -12 V to +12 V. The reference voltage inputs exhibit a constant nominal input
resistance of 5 k

, ± 20%. On the other hand, the DAC outputs I

OUT

A, B, C, D are code-dependent and produce

various output resistances and capacitances.

The choice of external amplifier should take into account the variation in impedance generatedby the DAC8803
on the amplifiers' inverting input node. The feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. For multiplying mode applications, an external feedback compensation capacitor
(C

) may be needed to provide a critically damped output response for step changes in reference input

voltages.

Figure 5 and Figure 6 show the gain vs frequency performance at various attenuation settings using a 23 pF
external feedback capacitor connected across the I

OUT

X and R

X terminals. In order to maintain good analog

performance, power supply bypassing of 0.01 µF, in parallel with 1 µF, is recommended. Under these conditions,
clean power supply with low ripple voltage capability should be used. Switching power supplies is usually not
suitable for this application due to the higher ripple voltage and PSS frequency-dependent characteristics. It is
best to derive the DAC8803 5-V supply from the system analog supply voltages. (Do not use the digital 5-V
supply.) See

Figure 55

www.ti.com

PRODUCT PREVIEW

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

D10

D11

D12
D13

A0
A1

A
B
C
D

ADC

2:4

Decode

Input

Register R

Input

Register R

Input

Register R

Input

Register R

DAC A

Register R

DAC B

Register R

DAC C

Register R

DAC D

Register R

DAC A

DAC B

DAC C

DAC D

Set MSB

Set

MSB

Power-

Reset

DGND

MSB

LDAC

GND

OUT

GND

OUT

GND

OUT

GND

OUT

A B C D

REF

CLK

SDI

SDO

SERIAL DATA INTERFACE

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

Figure 56. System Level Digital Interfacing

The DAC8803 uses a 3-wire (CS, SDI, CLK) SPI compatible serial data interface. Serial data of the DAC8803 is
clocked into the serial input register in an 14-bit data-word format. MSB bits are loaded first. Table 3 defines the
16 data-word bits for the DAC8803.

Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data
setup and data hold time requirements specified in the Interface Timing Specifications. Data can only be clocked
in while the CS chip select pin is active low. For the DAC8803, only the last 16 bits clocked into the serial register
are interrogated when the CS pin returns to the logic high state.

Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the
DAC8803. Keeping the CS line low between the first, second, and third byte transfers results in a successful
serial register update. Similarly, two right-justified data bytes can be written to the DAC8803. Keeping the CS line
low between the first and second byte transfer will result in a successful serial register update.

www.ti.com

PRODUCT PREVIEW

A
B
C
D

Address
Decoder

Shift Register

To Input Register

CLK

SDI

SDO

/17

CLOCK

POWER ON RESET

ESD Protection Circuits

DIGITAL

INPUTS

DGND

5 k

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new
data to the target DAC register, determined by the decoding of address bits A1and A0. For DAC8803,

Table 1

Table 3

and

Figure 57

define the characteristics of the software serial interface. Figures 8 and 9 show the

equivalent logic interface for the key digital control pins for DAC8803.

Figure 57. DAC8803 Equivalent Logic Interface

Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If
these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all
input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).

When the V

power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the

zero-code state or half-scale, depending on the MSB pin voltage. The V

power supply should have a smooth

positive ramp without drooping in order to have consistent results, especially in the region of V

= 1.5 V to 2.3

V. The V

supply has no effect on the power-on reset performance. The DAC register data stays at zero or

half-scale setting until a valid serial register data load takes place.

All logic-input pins contain back-biased ESD protection Zener diodes connected to ground (DGND) and V

shown in

Figure 58

Figure 58. Equivalent ESD Protection Circuits

www.ti.com

PRODUCT PREVIEW

PCB LAYOUT

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

In printed circuit board (PCB) layout, all analog ground, A

GND

X, should be tied together. Amplifiers suitable for:

Table 1. Control Logic Truth Table

(1)

CLK

LDAC

MSB

SERIAL SHIFT REGISTER

INPUT REGISTER

DAC REGISTER

No effect

Latched

No effect

Latched

Shift register data advanced one bit

Latched

No effect

Latched

No effect

Selected DAC updated with current SR

Latched

contents

No effect

Latched

Transparent

No effect

Latched

No effect

Latched

No effect

Latched data = 0000h

No effect

Latched data = 8000h

(1)

+ Positive logic transition; X = Do not care

Table 2. Serial Input Register Data Format, Data Loaded MSB First

(1)

Bit

B17

B16

B15

B14

B13

B12

B11

B10

(MSB)

(LSB)

Data

D13

D12

D11

D10

(1)

Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line's positive edge returns to
logic high. At this point an internally generated load strobe transfers the serial register data contents (bits D13-D0) to the decoded
DAC-input-register address determined by bits A1 and A0. Any extra bits clocked into the DAC8803 shift register are ignored, only the
last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.

Table 3. Address Decode

DAC DECODE

DAC A

DAC B

DAC C

DAC D

www.ti.com

PRODUCT PREVIEW

APPLICATION INFORMATION

OUT

(D 32, 768

REF

(2)

10 V

REF

10 k

5 k

REF

OUT

GND

One Channel

DAC8803

OUT

-10 V < V

OUT

< +10 V

Digital interface connections omitted for clarity.

Cross-Reference

DAC8803

SBAS340A JANUARY 2005 REVISED APRIL 2005

The DAC8803, a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output I

OUT

is the inverse of the input reference voltage at V

REF

Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. An additional external
op amp A2 is added as a summing amp. In this circuit the first and second amps (A1 and A2) provide a gain of
2X that widens the output span to 20 V. A 4-quadrant multiplying circuit is implemented by using a 10-V offset of
the reference voltage to bias A2. According to the following circuit transfer equation (

Equation 2

), input data (D)

from code 0 to full scale produces output voltages of V

OUT

= -10 V to V

OUT

= 10 V.

Figure 59. Four-Quadrant Multiplying Application Circuit

The DAC8803 has an industry-standard pinout.

Table 4

provides the cross-reference information.

Table 4. Cross-Reference

SPECIFIED

TEMPERATURE

PACKAGE

CROSS-

PRODUCT

INL (LSB)

DNL (LSB)

RANGE

DESCRIPTION

OPTION

REFERENCE PART

DAC8803IDB

±1

-40°C to +85°C

28-Lead MicroSOIC

SSOP-28

AD5554BRS

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

DAC8803IDBR

PREVIEW

SSOP

2500

TBD

Call TI

DAC8803IDBT

PREVIEW

SSOP

250

TBD

Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

13-Apr-2005

Addendum-Page 1

MECHANICAL DATA

MSSO002E JANUARY 1995 REVISED DECEMBER 2001

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20
7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,90

7,90

10,50

9,90

0,38

5,60
5,00

0,22

6,50

0,05 MIN

5,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65

0,15

 8

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products

Applications

Amplifiers

amplifier.ti.com

Audio

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

www.ti.com/broadband

Interface

interface.ti.com

Digital Control

www.ti.com/digitalcontrol

Logic

logic.ti.com

Military

www.ti.com/military

Power Mgmt

power.ti.com

Optical Networking

www.ti.com/opticalnetwork

Microcontrollers

microcontroller.ti.com

Security

www.ti.com/security

Telephony

www.ti.com/telephony

Video & Imaging

www.ti.com/video

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

2005, Texas Instruments Incorporated

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC8803IDBR

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC8803IDBR