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FEATURES
DESCRIPTION
DBB03
Baseband ASIC for Dolphin Chipset
SWRS027B DECEMBER 2004 REVISED MARCH 2005
Five Power-Saving Modes
Low Supply Voltage Range: 1.8 V to 3.6 V
Wake-Up From Standby Mode in less than 6
s
Ultralow-Power Consumption:
16-Bit RISC Architecture, 125-ns Instruction
Active Mode: 160 A at 1 MHz, 2.2 V
Cycle Time
Standby Mode: 0.9 A
Serial Communication Interface (USART),
Off Mode (RAM Retention) : 0.1 A
Software Selects Asynchronous UART or
Contains Frequency-Hopping Firmware for
Synchronous SPI
Dolphin Reference Design
Available in 64-Pin Quad Flat Pack (QFP)
Firmware Resides in ROM-Based Program
For Complete Dolphin Product Description,
Memory and is Fixed
See the Dolphin Frequency Hopping Spread
Simple UART Interface to an External
Spectrum Evaluation Kit Hardware and
Host/System Microcontroller
Software User's Guide (SLLU090)
Pre-Defined Protocol for Communication with
an External Host/System Microcontroller
The DBB03 is a baseband ASIC for the "Dolphin" reference design. The firmware for the Dolphin reference
design resides in the ROM-based program memory of the DBB03, and thus can be readily interfaced with a
TRF6903 single-chip RF Transceiver to generate a frequency hopping wireless UART "Dolphin" reference design
chipset. This is illustrated in Figure 1.
The DBB03 baseband ASIC in addition to being a RF baseband processor is also responsible for
communications with an external host/system micrcontroller. In a typical end user application, the Dolphin chipset
will be connected up to an external host/system microcontroller that will send configuration messages, RF
transmission messages into the Dolphin chipset, or receive status, RF messages received from the Dolphin
chipset.
Any catalog low-cost host/system microcontroller can be interfaced to the Dolphin chipset as long as the Dolphin
host interface protocol for communication is adhered to. (See Application Note Dolphin - Frequency Hopping
Spread Spectrum Chipset Host Interface Protocol TI Literature SWRA043) Texas Instruments recommends its
ultra-low power MSP430 series of microcontrollers to interface with Dolphin.
The interface between the DBB03 baseband ASIC and an external host/system microcontroller is a simple UART
consisting of RX and TX data lines. (See Application Note Interfacing Dolphin to an External System
Microcontroller, TI Literature SWRA045).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20042005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
DBB03 Base-
band ASIC
RF
TRF6903
System Micro
Application Layer
Data Link Layer
MAC Layer
PHY Layer
Wireless UART Dolphin
Host Interface
Protocol via UART
DBB03
Baseband ASIC for Dolphin Chipset
SWRS027B DECEMBER 2004 REVISED MARCH 2005
Figure 1. DBB03 - Baseband ASIC for the Dolphin Chipset
The Wireless UART Dolphin chipset is a true Data-In/RF-out and RF-in/Data-out solution with all aspects of data
management and frequency hopping implemented in firmware residing on the DBB03. As illustrated in Figure 1,
the DBB03 baseband ASIC contains the complete firmware for Dolphin (PHYsical, MAC and the Data Link layer),
while the application layer protocol is handled by the external Host/System Microcontroller.
AVAILABLE OPTIONS
T
A
PACKAGE
ORDER NUMBER
-40
C to 85
C
Plastic 64-pin QFP (PM)
DBB03 IPM
2
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PIN DESIGNATION, DBB03 Baseband ASIC
17 18 19
P5.4/MCLK
P5.3
P5.2
P5.1
P5.0
P4.7/TBCLK
P4.6
P4.5
P4.4
P4.3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7
P3.6
P3.5/URXD0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DV
CC
P6.3
P6.4
P6.5
P6.6
P6.7
NC
XIN
XOUT
NC
NC
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
21 22 23 24
P5.6/ACLK
TDO/TDI
63 62 61 60 59
64
58
A
V
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
P2.6
P2.7/T
A0
P3.0/STE0
P3.1/SIMO0
P1.7/T
A2
P2.1/T
AINCLK
P2.2/CAOUT/T
A0
P2.3/CA0/T
A1
P2.4/CA1/T
A2
P2.5/Rosc
56 55 54
57
25 26 27 28 29
53 52
P1.5/T
A0
XT2IN
XT2OUT
51 50 49
30 31 32
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
P5.7/TBOUTH
TDI/TCLK
P5.5/SMCLK
A
V
DV
PM PACKAGE
(TOP VIEW)
P1.6/T
A1
P2.0/ACLK
CC
SS
SS
NC - No internal connection
DBB03
Baseband ASIC for Dolphin Chipset
SWRS027B DECEMBER 2004 REVISED MARCH 2005
3
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FUNCTIONAL BLOCK DIAGRAMS: DBB03
Oscillator
ACLK
SMCLK
CPU
Incl. 16 Reg.
Bus
Conv
MCB
XIN XOUT/TCLK
P3
P4
P2
XT2IN
XT2OUT
TMS
TCK
MDB, 16 Bit
MAB, 16 Bit
MCLK
4
TDI
TDO/TDI
P5
P6
MAB,
4 Bit
DV
CC
DV
SS
AV
CC
AV
SS
RST/NMI
System
Clock
R
OSC
P1
16KB ROM
8KB ROM
512B RAM
256B RAM
Watchdog
Timer
15/16-Bit
Timer_B3
3 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Test
JTAG
Emulation
Module
I/O Port
1/2
16 I/Os,
with
Interrupt
Capability
I/O Port 3/4
16 I/Os
POR
Comparator
A
USART0
UART Mode
SPI Mode
I/O Port 5/6
16 I/Os
MDB, 8 Bit
MDB, 16-Bit
MAB, 16-Bit
8
8
8
8
8
8
DEVICE INFORMATION
DBB03
Baseband ASIC for Dolphin Chipset
SWRS027B DECEMBER 2004 REVISED MARCH 2005
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AV
CC
64
Supply voltage, positive terminal. AV
CC
and DV
CC
are internally connected together.
AV
SS
64
Supply voltage, negative terminal. AV
SS
and DV
SS
are internally connected together.
DV
CC
1
Supply voltage, positive terminal. AV
CC
and DV
CC
are internally connected together.
DV
SS
63
Supply voltage, negative terminal. AV
SS
and DV
SS
are internally connected together.
P1.0/TACLK
12
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
13
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output
P1.2/TA1
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK
16
I/O
General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0
17
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK
20
I/O
General-purpose digital I/O pin/ACLK output
P2.1/TAINCL
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
K
P2.2/CAOUT/
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output
TA0
P2.3/CA0/TA
23
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
1
P2.4/CA1/TA
24
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
2
General-purpose digital I/O pin/input for external resistor defining the DCO nominal
P2.5/R
OSC
25
I/O
frequency
P2.6
26
I/O
General-purpose digital I/O pin
4
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DBB03
Baseband ASIC for Dolphin Chipset
SWRS027B DECEMBER 2004 REVISED MARCH 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
P2.7/TA0
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P3.0/STE0
28
I/O
General-purpose digital I/O pin/slave transmit enable - USART0/SPI mode
P3.1/SIMO0
29
I/O
General-purpose digital I/O pin/slave in/master out of USART0/SPI mode
P3.2/SOMI0
30
I/O
General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
General-purpose digital I/O pin/external clock input - USART0/UART or SPI mode, clock
P3.3/UCLK0
31
I/O
output - USART0/SPI mode
P3.4/UTXD0
32
I/O
General-purpose digital I/O pin/transmit data out - USART0/UART mode
P3.5/URXD0
33
I/O
General-purpose digital I/O pin/receive data in - USART0/UART mode
P3.6
34
I/O
General-purpose digital I/O pin
P3.7
35
I/O
General-purpose digital I/O pin
P4.0/TB0
36
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1
37
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output
P4.2/TB2
38
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output
P4.3
39
I/O
General-purpose digital I/O pin
P4.4
40
I/O
General-purpose digital I/O pin
P4.5
41
I/O
General-purpose digital I/O pin
P4.6
42
I/O
General-purpose digital I/O pin
P4.7/TBCLK
43
I/O
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0
44
I/O
General-purpose digital I/O pin
P5.1
45
I/O
General-purpose digital I/O pin
P5.2
46
I/O
General-purpose digital I/O pin
P5.3
47
I/O
General-purpose digital I/O pin
P5.4/MCLK
48
I/O
General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK
49
I/O
General-purpose digital I/O pin/submain system clock SMCLK output
P5.6/ACLK
50
I/O
General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUT
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance -
51
I/O
H
Timer_B7 TB0 to TB2
P6.0
59
I/O
General-purpose digital I/O pin
P6.1
60
I/O
General-purpose digital I/O pin
P6.2
61
I/O
General-purpose digital I/O pin
P6.3
2
I/O
General-purpose digital I/O pin
P6.4
3
I/O
General-purpose digital I/O pin
P6.5
4
I/O
General-purpose digital I/O pin
P6.6
5
I/O
General-purpose digital I/O pin
P6.7
6
I/O
General-purpose digital I/O pin
RST/NMI
58
I
Reset input, nonmaskable interrupt input port
TCK
57
I
Test clock. TCK is the clock input port for device programming test.
Test data input or test clock input. TDI is used as a data input port. The device protection
TDI/TCLK
55
I
fuse is connected to TDI.
TDO/TDI
54
I/O
Test data output port. TDO/TDI data output
TMS
56
I
Test mode select. TMS is used as an input port for device test.
NC
7, 10, 11
No internal connection
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
O
Output terminal of crystal oscillator XT1
XT2IN
53
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT
52
O
Output terminal of crystal oscillator XT2
5
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DBB03
Baseband ASIC for Dolphin Chipset
SWRS027B DECEMBER 2004 REVISED MARCH 2005
6
MECHANICAL DATA
MTQF008A JANUARY 1995 REVISED DECEMBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
4040152 / C 11/96
32
17
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50
M
0,08
0
7
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
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2005, Texas Instruments Incorporated
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