SN74HC165 Q1
8 BIT PARALLEL LOAD SHIFT REGISTER
SCLS518 - AUGUST 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Qualification in Accordance With
AEC-Q100
D
Qualified for Automotive Applications
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
D
ESD Protection Exceeds 1500 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Wide Operating Voltage Range of 2 V to 6 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 13 ns
D
4-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
Complementary Outputs
D
Direct Overriding Load (Data) Inputs
D
Gated Clock Inputs
D
Parallel-to-Serial Data Conversion
Contact factory for details. Q100 qualification data available on
request.
description/ordering information
The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (Q
H
)
output. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled
by a low level at the shift/load (SH/LD) input. The SN74HC165 also features a clock-inhibit (CLK INH) function
and a complementary serial (Q
H
) output.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
-40
C to 125
C
SOIC - D
Tape and reel
SN74HC165QDRQ1
HC165Q1
-40
C to 125
C
TSSOP - PW
Tape and reel
SN74HC165QPWRQ1
HC165Q1
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
F
G
H
Q
H
GND
V
CC
CLK INH
D
C
B
A
SER
Q
H
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74HC165 Q1
8 BIT PARALLEL LOAD SHIFT REGISTER
SCLS518 - AUGUST 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
FUNCTION
SH/LD
CLK
CLK INH
FUNCTION
L
X
X
Parallel load
H
H
X
No change
H
X
H
No change
H
L
Shift
H
L
Shift
Shift = content of each internal register shifts
toward serial output QH. Data at SER is
shifted into the first register.
logic diagram (positive logic)
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7
QH
QH
11
12
13
14
3
4
5
6
A
B
C
D
E
F
G
H
SN74HC165 Q1
8 BIT PARALLEL LOAD SHIFT REGISTER
SCLS518 - AUGUST 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
typical shift, load, and inhibit sequence
Load
E
QH
H
G
C
F
Data
Inputs
D
SH/LD
SER
CLK INH
CLK
B
A
QH
L
L
H
L
H
L
H
H
H
H
L
H
L
H
L
H
L
H
L
L
H
L
H
L
H
Inhibit
Serial Shift
SN74HC165 Q1
8 BIT PARALLEL LOAD SHIFT REGISTER
SCLS518 - AUGUST 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
108
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
V
VCC = 2 V
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VIH
High-level input voltage
VCC = 6 V
4.2
V
VCC = 2 V
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VIL
Low-level input voltage
VCC = 6 V
1.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2 V
1000
t/
v
Input transition rise/fall time
VCC = 4.5 V
500
ns
t/
v
Input transition rise/fall time
VCC = 6 V
400
ns
TA
Operating free-air temperature
-40
125
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
SN74HC165 Q1
8 BIT PARALLEL LOAD SHIFT REGISTER
SCLS518 - AUGUST 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
2 V
1.9
1.998
1.9
IOH = -20
A
4.5 V
4.4
4.499
4.4
VOH
VI = VIH or VIL
IOH = -20
A
6 V
5.9
5.999
5.9
V
VOH
VI = VIH or VIL
IOH = -4 mA
4.5 V
3.98
4.3
3.7
V
IOH = -5.2 mA
6 V
5.48
5.8
5.2
2 V
0.002
0.1
0.1
IOL = 20
A
4.5 V
0.001
0.1
0.1
VOL
VI = VIH or VIL
IOL = 20
A
6 V
0.001
0.1
0.1
V
VOL
VI = VIH or VIL
IOL = 4 mA
4.5 V
0.17
0.26
0.4
V
IOL = 5.2 mA
6 V
0.15
0.26
0.4
II
VI = VCC or 0
6 V
0.1
100
1000
nA
ICC
VI = VCC or 0,
IO = 0
6 V
8
160
A
Ci
2 V to 6 V
3
10
10
pF
SN74HC165 Q1
8 BIT PARALLEL LOAD SHIFT REGISTER
SCLS518 - AUGUST 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25
C
MIN
MAX
UNIT
VCC
MIN
MAX
MIN
MAX
UNIT
2 V
6
4.2
fclock
Clock frequency
4.5 V
31
21
MHz
fclock
Clock frequency
6 V
36
25
MHz
2 V
80
120
SH/LD low
4.5 V
16
24
tw
Pulse duration
SH/LD low
6 V
14
20
ns
tw
Pulse duration
2 V
80
120
ns
CLK high or low
4.5 V
16
24
CLK high or low
6 V
14
20
2 V
80
120
SH/LD high before CLK
4.5 V
16
24
SH/LD high before CLK
6 V
14
20
2 V
40
60
SER before CLK
4.5 V
8
12
SER before CLK
6 V
7
10
2 V
100
150
tsu
Setup time
CLK INH low before CLK
4.5 V
20
30
ns
tsu
Setup time
CLK INH low before CLK
6 V
17
25
ns
2 V
40
60
CLK INH high before CLK
4.5 V
8
12
CLK INH high before CLK
6 V
7
10
2 V
100
150
Data before SH/LD
4.5 V
20
30
Data before SH/LD
6 V
17
26
2 V
5
5
SER data after CLK
4.5 V
5
5
th
Hold time
SER data after CLK
6 V
5
5
ns
th
Hold time
2 V
5
5
ns
PAR data after SH/LD
4.5 V
5
5
PAR data after SH/LD
6 V
5
5
SN74HC165 Q1
8 BIT PARALLEL LOAD SHIFT REGISTER
SCLS518 - AUGUST 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
2 V
6
13
4.2
fmax
4.5 V
31
50
21
MHz
fmax
6 V
36
62
25
MHz
2 V
80
150
225
SH/LD
QH or QH
4.5 V
20
30
45
SH/LD
QH or QH
6 V
16
26
38
2 V
75
150
225
tpd
CLK
QH or QH
4.5 V
15
30
45
ns
tpd
CLK
QH or QH
6 V
13
26
38
ns
2 V
75
150
225
H
QH or QH
4.5 V
15
30
45
H
QH or QH
6 V
13
26
38
2 V
38
75
110
tt
Any
4.5 V
8
15
22
ns
tt
Any
6 V
6
13
19
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load
75
pF
SN74HC165 Q1
8 BIT PARALLEL LOAD SHIFT REGISTER
SCLS518 - AUGUST 2003
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%
50%
10%
10%
90%
90%
VCC
VCC
0 V
0 V
tr
tf
Reference
Input
Data
Input
50%
High-Level
Pulse
50%
VCC
0 V
50%
50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%
50%
10%
10%
90%
90%
VCC
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
50%
tPLH
tPHL
50%
50%
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Figure 1. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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2004, Texas Instruments Incorporated
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