Document Outline

features
description
AVAILABLE OPTIONS
pin designation, MSP430x11x2
pin designation, MSP430x12x2
functional block diagram, MSP430x11x2
functional block diagram, MSP430x12x2
Terminal Functions, MSP430x11x2
Terminal Functions, MSP430x12x2
short-form description
- CPU
- instruction set
- operating modes
- interrupt vector addresses
special function registers
- interrupt enable 1 and 2
- interrupt flag register 1 and 2
- module enable registers 1 and 2
memory organization
bootstrap loader (BSL)
flash memory
peripherals
oscillator and system clock
digital I/O
brownout
watchdog timer
USART0 (MSP430x12x2 Only)
ADC10
timer_A3
peripheral file map
absolute maximum ratings
recommended operating conditions
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
- supply current (into VCC) excluding external current
- current consumption of active mode versus system frequency
- current consumption of active mode versus supply voltage
- Schmitt-trigger inputs Port P1 to Port P3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
- standard inputs - RST\ /NMI; TEST
- inputs Px.x, TAx
- leakage current
- outputs Port 1 to Port 3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7
- outputs P1.x, P2.x, P3.x, TAx
- outputs - Ports P1, P2, and P3
- USART
- RAM
- POR brownout, reset
- crystal oscillator,LFXT1
- DCO
- principle characteristics of the DCO
- wake-up from lower power modes (LPMx)
- 10-bit ADC, power supply and input range conditions
- 10-bit ADC, external reference
- 10-bit ADC, built-in reference
- 10-bit ADC, timing parameters
- 10-bit ADC, linearity parameters
- 10-bit ADC, temperature sensor and built-in VMID
- Flash Memory
- JTAG Interface
- JTAG Fuse
APPLICATION INFORMATION
input/output schematic
- Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
- Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
- Port P2, P2.0 to P2.2, input/output with Schmitt-trigger
- Port P2, P2.3 to P2.4, input/output with Schmitt-trigger
- Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock Module
- Port P2, unbonded bits P2.6 and P2.7
- port P3, P3.0, P3.6 and P3.7 input/output with Schmitt-trigger
- port P3, P3.1 input/output with Schmitt-trigger
- port P3, P3.2, input/output with Schmitt-trigger
- port P3, P3.3, input/output with Schmitt-trigger
- port P3, P3.4, and P3.5 input/output with Schmitt-trigger
- JTAG fuse check mode
MECHANICAL DATA
- DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
- PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
- RHB (S-PQFP-N32) PLASTIC QUAD FLATPACK

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Low Supply Voltage Range 1.8 V - 3.6 V

Ultralow-Power Consumption:
- Active Mode: 200

A at 1 MHz, 2.2 V

- Standby Mode: 0.7

- Off Mode (RAM Retention): 0.1

Five Power Saving Modes

Wake-Up From Standby Mode in less
than 6

16-Bit RISC Architecture, 125 ns
Instruction Cycle Time

Basic Clock Module Configurations:
- Various Internal Resistors
- Single External Resistor
- 32-kHz Crystal
- High Frequency Crystal
- Resonator
- External Clock Source

16-Bit Timer_A With Three
Capture/Compare Registers

10-Bit, 200-ksps A/D Converter With
Internal Reference, Sample-and-Hold,
Autoscan, and Data Transfer Controller

Serial Communication Interface (USART0)
With Software-Selectable Asynchronous
UART or Synchronous SPI
(MSP430x12x2 Only)

Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse

Supply Voltage Brownout Protection

MSP430x11x2 Family Members Include:
MSP430F1122: 4KB + 256B Flash Memory

256B RAM

MSP430F1132: 8KB + 256B Flash Memory

256B RAM

Available in 20-Pin Plastic SOWB, 20-Pin
Plastic TSSOP and 32-Pin QFN Packages

MSP430x12x2 Family Members Include:
MSP430F1222: 4KB + 256B Flash Memory

256B RAM

MSP430F1232: 8KB + 256B Flash Memory

256B RAM

Available in 28-Pin Plastic SOWB, 28-Pin
Plastic TSSOP, and 32-Pin QFN Packages

For Complete Module Descriptions, See the
MSP430x1xx Family User's Guide,
Literature Number SLAU049

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6

The MSP430x11x2 and MSP430x12x2 series are ultralow-power mixed signal microcontrollers with a built-in
16-bit timer, 10-bit A/D converter with integrated reference and data transfer controller (DTC) and fourteen or
twenty-two I/O pins. In addition, the MSP430x12x2 series microcontrollers have built-in communication
capability using asynchronous (UART) and synchronous (SPI) protocols.

Digital signal processing with the 16-bit RISC performance enables effective system solutions such as glass
breakage detection with signal analysis (including wave digital filter algorithm). Another area of application is
in stand-alone RF sensors.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2002 - 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC 20-PIN

SOWB (DW)

PLASTIC 20-PIN

TSSOP (PW)

PLASTIC 28-PIN

SOWB (DW)

PLASTIC 28-PIN

TSSOP (PW)

PLASTIC 32-PIN

QFN (RHB)

- 40

C to 85

MSP430F1122IDW

MSP430F1122IPW

MSP430F1222IDW

MSP430F1222IPW

MSP430F1122IRHB
MSP430F1132IRHB

- 40

C to 85

MSP430F1122IDW
MSP430F1132IDW

MSP430F1122IPW
MSP430F1132IPW

MSP430F1222IDW
MSP430F1232IDW

MSP430F1222IPW
MSP430F1232IPW

MSP430F1132IRHB

MSP430F1222IRHB
MSP430F1232IRHB

pin designation, MSP430x11x2 (see Note)

TEST

P2.5/R

OSC

XOUT

XIN

RST/NMI

P2.0/ACLK/A0

P2.1/INCLK/A1

P2.2/TA0/A2

P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK/ADC10CLK
P2.4/TA2/A4/V

REF+

eREF+

P2.3/TA1/A3/V

REF-

eREF-

DW or PW PACKAGE

(TOP VIEW)

RHB PACKAGE

(TOP VIEW)

XIN

P2.5/R

OSC

RST/NMI

P2.0/ACLK/A0

TEST

P2.1/INCLK/A1

P1.7/T

A2/TDO/TDI

XOUT

P1.6/T

A1/TDI/TCLK

P1.1/TA0
P1.0/TACLK/ADC10CLK
NC
P2.4/TA2/A4/V

REF+

eREF+

P2.3/TA1/A3/V

REF-

eREF-

P1.2/TA1

Note: It is recommended that all NC pins be connected to VSS to avoid floating nodes,

otherwise increased current consumption may occur. Power pad not internally connected.

10 11 12 13

P1.5/T

A0/TMS

P1.3/TA2

P2.2/TA0/A2

P1.4/SMCLK/TCK

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

pin designation, MSP430x12x2 (see Note)

DW or PW PACKAGE

(TOP VIEW)

TEST

P2.5/R

OSC

XOUT

XIN

RST/NMI

P2.0/ACLK/A0

P2.1/INCLK/A1

P2.2/TA0/A2

P3.0/STE0/A5

P3.1/SIMO0
P3.2/SOMI0

P3.3/UCLK0

P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK/ADC10CLK
P2.4/TA2/A4/V

REF+

eREF+

P2.3/TA1/A3/V

REF-

eREF-

P3.7/A7
P3.6/A6
P3.5/URXD0
P3.4/UTXD0

RHB PACKAGE

(TOP VIEW)

XIN

P2.5/R

OSC

RST/NMI

P2.0/ACLK/A0

TEST

P2.1/INCLK/A1

P1.7/T

A2/TDO/TDI

XOUT

P1.6/T

A1/TDI/TCLK

P1.1/TA0
P1.0/TACLK/ADC10CLK
NC
P2.4/TA2/A4/V

REF+

eREF+

P2.3/TA1/A3/V

REF-

eREF-

P1.2/TA1

Note: It is recommended that all NC pins be connected to VSS to avoid floating nodes,

otherwise increased current consumption may occur. Power pad not internally connected.

10 11 12 13

P3.0/STE0/A5

P3.1/SIMO0

P3.2/SOMI0

P3.3/UCLK0

P3.4/UTXD0

P3.5/URXD0

P3.6/A6

P1.5/T

A0/TMS

P1.3/TA2

P2.2/TA0/A2

P3.7/A7

P1.4/SMCLK/TCK

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional block diagram, MSP430x11x2

Oscillator

ACLK

SMCLK

CPU

Incl. 16 Reg.

Bus

Conv

MCB

XIN

XOUT

MDB, 16 Bit

MAB, 16 Bit

MCLK

MAB,

4 Bit

VCC

VSS

RST/NMI

System

Clock

ROSC

8KB Flash

4KB Flash

256B RAM

ADC10

10-Bit

Autoscan

DTC

Watchdog

Timer

15/16-Bit

Timer_A3

3 CC Reg

I/O Port 1

8 I/Os, with

Interrupt

Capability

I/O Port 2

6 I/Os, with

Interrupt

Capability

POR/

Brownout

MDB, 8 Bit

MDB, 16-Bit

MAB, 16-Bit

JTAG

TEST

Test

JTAG

Emulation

Module

functional block diagram, MSP430x12x2

Oscillator

ACLK

SMCLK

CPU

Incl. 16 Reg.

Bus

Conv

MCB

XIN

XOUT

MDB, 16 Bit

MAB, 16 Bit

MCLK

MAB,

4 Bit

VCC

VSS

RST/NMI

System

Clock

ROSC

8KB Flash

4KB Flash

256B RAM

ADC10

10-Bit

Autoscan

DTC

Watchdog

Timer

15/16-Bit

Timer_A3

3 CC Reg

I/O Port 1

8 I/Os, with

Interrupt

Capability

I/O Port 2

6 I/Os, with

Interrupt

Capability

POR/

Brownout

USART0

UART Mode

SPI Mode

I/O Port 3

8 I/Os

MDB, 8 Bit

MDB, 16-Bit

MAB, 16-Bit

JTAG

TEST

Test

JTAG

Emulation

Module

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions, MSP430x11x2

TERMINAL

I/O

DESCRIPTION

NAME

DW & PW

RHB

I/O

DESCRIPTION

NAME

DW & PW

RHB

I/O

DESCRIPTION

P1.0/TACLK/
ADC10CLK

I/O

General-purpose digital I/O pin/Timer_A, clock signal TACLK input/conversion
clock--10-bit ADC

P1.1/TA0

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0
output/BSL transmit

P1.2/TA1

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output

P1.3/TA2

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output

P1.4/SMCLK/TCK

I/O

General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for
device programming and test

P1.5/TA0/TMS

I/O

General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input
terminal for device programming and test

P1.6/TA1/TDI/TCLK

I/O

General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal
or test clock input

P1.7/TA2/TDO/TDI

I/O

General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output
terminal or data input during programming

P2.0/ACLK/A0

I/O

General-purpose digital I/O pin/ACLK output/analog input to 10-bit ADC input A0

P2.1/INCLK/A1

I/O

General-purpose digital I/O pin/Timer_A, clock signal at INCLK/analog input to 10-bit
ADC input A1

P2.2/TA0/A2

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0
output/analog input to 10-bit ADC input A2/BSL receive

P2.3/TA1/A3/VREF-/
VeREF-

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1
output/analog input to 10-bit ADC input A3/negative reference voltage terminal.

P2.4/TA2/A4/VREF+/
VeREF+

I/O

General-purpose digital I/O pin/Timer_A, compare: Out2 output/analog input to 10-bit
ADC input A4/I/O of positive reference voltage terminal

P2.5/ROSC

I/O

General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal
frequency

RST/NMI

Reset or nonmaskable interrupt input

TEST

Selects test mode for JTAG pins on P1.x

VCC

Supply voltage

VSS

Ground reference

XIN

Input terminal of crystal oscillator

XOUT

Output terminal of crystal oscillator

4,9-16,

17,20,31

No connect. Recommended connection to VSS to avoid floating nodes, otherwise
increased current consumption may occur.

TDO or TDI is selected via JTAG instruction.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

Terminal Functions, MSP430x12x2

TERMINAL

I/O

DESCRIPTION

NAME

DW & PW

RHB

I/O

DESCRIPTION

NAME

DW & PW

RHB

I/O

DESCRIPTION

P1.0/TACLK/
ADC10CLK

I/O

General-purpose digital I/O pin/Timer_A, clock signal TACLK input/conversion
clock--10-bit ADC

P1.1/TA0

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0
output/BSL transmit

P1.2/TA1

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output

P1.3/TA2

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output

P1.4/SMCLK/TCK

I/O

General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for
device programming and test

P1.5/TA0/TMS

I/O

General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input
terminal for device programming and test

P1.6/TA1/TDI/TCLK

I/O

General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal
or test clock input

P1.7/TA2/TDO/TDI

I/O

General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output
terminal or data input during programming

P2.0/ACLK/A0

I/O

General-purpose digital I/O pin/ACLK output/analog input to 10-bit ADC input A0

P2.1/INCLK/A1

I/O

General-purpose digital I/O pin/Timer_A, clock signal at INCLK/analog input to 10-bit
ADC input A1

P2.2/TA0/A2

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0
output/analog input to 10-bit ADC input A2/BSL receive

P2.3/TA1/A3/VREF-/
VeREF-

I/O

General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1
output/analog input to 10-bit ADC input A3/negative reference voltage terminal.

P2.4/TA2/A4/VREF+/
VeREF+

I/O

General-purpose digital I/O pin/Timer_A, compare: Out2 output/analog input to 10-bit
ADC input A4/I/O of positive reference voltage terminal

P2.5/ROSC

I/O

General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal
frequency

P3.0/STE0/A5

I/O

General-purpose digital I/O pin/slave transmit enable--USART0/SPI mode/analog
input to 10-bit ADC input A5

P3.1/SIMO0

I/O

General-purpose digital I/O pin/slave in/master out of USART0/SPI mode

P3.2/SOMI0

I/O

General-purpose digital I/O pin/slave out/master in of USART0/SPI mode

P3.3/UCLK0

I/O

General-purpose digital I/O pin/external clock input--USART0/UART or SPI mode,
clock output--USART0/SPI mode clock input

P3.4/UTXD0

I/O

General-purpose digital I/O pin/transmit data out--USART0/UART mode

P3.5/URXD0

I/O

General-purpose digital I/O pin/receive data in--USART0/UART mode

P3.6/A6

I/O

General-purpose digital I/O pin/analog input to 10-bit ADC input A6

P3.7/A7

I/O

General-purpose digital I/O pin/analog input to 10-bit ADC input A7

RST/NMI

Reset or nonmaskable interrupt input

TEST

Selects test mode for JTAG pins on P1.x

VCC

Supply voltage

VSS

Ground reference

XIN

Input terminal of crystal oscillator

XOUT

Output terminal of crystal oscillator

4,17,

20,31

No connect. Recommended connection to VSS to avoid floating nodes, otherwise
increased current consumption may occur.

TDO or TDI is selected via JTAG instruction.

General-Purpose Register

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-Purpose Register

R10

R11

General-Purpose Register

R14

R15

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.

The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.

Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.

instruction set

The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination

e.g. ADD R4,R5

R4 + R5 ---> R5

Single operands, destination only

e.g. CALL R8

PC -->(TOS), R8--> PC

Relative jump, un/conditional

e.g. JNE

Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE

SYNTAX

EXAMPLE

OPERATION

D D

MOV Rs,Rd

MOV R10,R11

R10 --> R11

Indexed

D D

MOV X(Rn),Y(Rm)

MOV 2(R5),6(R6)

M(2+R5)--> M(6+R6)

Symbolic (PC relative)

D D

MOV EDE,TONI

M(EDE) --> M(TONI)

Absolute

D D

MOV &MEM,&TCDAT

M(MEM) --> M(TCDAT)

Indirect

MOV @Rn,Y(Rm)

MOV @R10,Tab(R6)

M(R10) --> M(Tab+R6)

Indirect

autoincrement

MOV @Rn+,Rm

MOV @R10+,R11

M(R10) --> R11
R10 + 2--> R10

Immediate

MOV #X,TONI

MOV #45,TONI

#45 --> M(TONI)

NOTE: S = source D = destination

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

Active mode AM;

All clocks are active

Low-power mode 0 (LPM0);

CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled

Low-power mode 1 (LPM1);

CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO's dc-generator is disabled if DCO not used in active mode

Low-power mode 2 (LPM2);

CPU is disabled
MCLK and SMCLK are disabled
DCO's dc-generator remains enabled
ACLK remains active

Low-power mode 3 (LPM3);

CPU is disabled
MCLK and SMCLK are disabled
DCO's dc-generator is disabled
ACLK remains active

Low-power mode 4 (LPM4);

CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO's dc-generator is disabled
Crystal oscillator is stopped

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the memory with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up, external reset, watchdog

WDTIFG (see Note1)
KEYV (see Note 1)

Reset

0FFFEh

15, highest

NMI, oscillator fault, flash memory
access violation

NMIIFG (see Notes 1 and 4)
OFIFG (see Notes 1 and 4)
ACCVIFG (see Notes 1 and 4)

(Non)-maskable,
(Non)-maskable,

(Non)-maskable

0FFFCh

0FFFAh

0FFF8h

0FFF6h

Watchdog timer

WDTIFG

Maskable

0FFF4h

Timer_A

TACCR0 CCIFG (see Note 2)

Maskable

0FFF2h

Timer_A

TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 and 2)

Maskable

0FFF0h

USART0 receive (see Note 5)

URXIFG0

Maskable

0FFEEh

USART0 transmit (see Note 5)

UTXIFG0

Maskable

0FFECh

ADC10

ADC10IFG

Maskable

0FFEAh

0FFE8h

I/O Port P2 (eight flags - see Note 3)

P2IFG.0 to P2IFG.7
(see Notes 1 and 2)

Maskable

0FFE6h

I/O Port P1 (eight flags)

P1IFG.0 to P1IFG.7
(see Notes 1 and 2)

Maskable

0FFE4h

0FFE2h

0FFE0h

0, lowest

NOTES:

1. Multiple source flags
2. Interrupt flags are located in the module
3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0-5) are implemented on the '11x2 and '12x2 devices.
4. (Non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
5. USART0 is implemented in MSP430x12x2 only.

MSP430x11x2, MSP430x12x2

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special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.

interrupt enable 1 and 2

OFIE

WDTIE

rw-0

Address

NMIIE

ACCVIE

rw-0

WDTIE: Watchdog

Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer

is configured in interval timer mode.

OFIE:

Oscillator fault enable

NMIIE:

(Non)maskable interrupt enable

ACCVIE:

Flash access violation interrupt enable

Address

01h

UTXIE0

URXIE0

rw-0

URXIE0: USART0, UART, and SPI receive-interrupt enable (MSP430x12x2 devices only)
UTXIE0: USART0, UART, and SPI transmit-interrupt enable (MSP430x12x2 devices only)

interrupt flag register 1 and 2

OFIFG

WDTIFG

rw-0

rw-1

rw-0

Address

02h

NMIIFG

WDTIFG:

Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V

power-up or a reset condition at RST/NMI pin in reset mode.

OFIFG:

Flag set on oscillator fault

NMIIFG:

Set via RST/NMI-pin

Address

03h

UTXIFG0

URXIFG0

rw-0

rw-1

URXIFG0: USART0, UART, and SPI receive flag (MSP430x12x2 devices only)
UTXIFG0: USART0, UART, and SPI transmit flag (MSP430x12x2 devices only)

MSP430x11x2, MSP430x12x2

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module enable registers 1 and 2

Address

04h

Address

05h

UTXE0

URXE0

USPIE0

rw-0

URXE0:

USART0, UART mode receive enable (MSP430x12x2 devices only)

UTXE0:

USART0, UART mode transmit enable (MSP430x12x2 devices only)

USPIE0:

USART0, SPI mode transmit and receive enable (MSP430x12x2 devices only)

Legend

rw:
rw-0:

Bit can be read and written.
Bit can be read and written. It is reset by PUC
SFR bit is not present in device.

memory organization

Int. Vector

8 KB

Flash

Segment0-15

256B RAM

16b Per.

8b Per.

SFR

FFFFh
FFE0h

FFDFh

02FFh

0200h

01FFh

0100h

00FFh

0010h

000Fh

0000h

MSP430F1132
MSP430F1232

E000h

Main
Memory

10FFh

128B

Flash

SegmentA,B

Information
Memory

1000h

1 KB

Boot ROM

0C00h

Int. Vector

4 KB Flash

Segment0-7

256B RAM

16b Per.

8b Per.

SFR

FFDFh

F000h

02FFh

0200h

0100h

00FFh

0010h

000Fh

0000h

MSP430F1122
MSP430F1222

1 KB

Boot ROM

128B

Flash

SegmentA,B

10FFh

1000h

01FFh

0C00h

0FFFh

FFFFh
FFE0h

0FFFh

MSP430x11x2, MSP430x12x2

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bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.

BSL Function

MSP430x11x2

DW & PW Package

(20 Pins)

MSP430x12x2

DW & PW Package

(28 Pins)

MSP430x11x2/12x2

RHB Package

(32 Pins)

Data Transmit

14 - P1.1

22 - P1.1

Data Receive

10 - P2.2

8 - P2.2

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A and B can be erased individually, or as a group with segments 0-n.
Segments A and B are also called information memory.

New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.

Segment0 w/

Interrupt Vectors

0FFFFh

0FE00h

Information

Memory

Flash Main Memory

Segment1

Segment2

Segment3

Segment4

Segment14

Segment15

SegmentA

SegmentB

0FDFFh

0FC00h

0FBFFh

0FA00h

0F9FFh

0F800h

0F7FFh

0F600h

0E3FFh

0E200h

0E1FFh

0E000h

010FFh

01080h

0107Fh

01000h

NOTE: All segments not implemented on all devices.

MSP430x11x2, MSP430x12x2

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peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family User's Guide, literature number
SLAU049.

oscillator and system clock

The clock system in the MSP430x11x2 and MSP430x12x2 devices is supported by the basic clock module that
includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a
high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes
in less than 6

s. The basic clock module provides the following clock signals:

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.

Main clock (MCLK), the system clock used by the CPU.

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

digital I/O

There are 3 8-bit I/O ports implemented--ports P1, P2, and P3 (only six port P2 I/O signals are available on
external pins; port P3 is implemented only on 'x12x2 devices):

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Edge-selectable interrupt input capability for all the eight bits of ports P1 and six bits of port P2.

Read/write access to port-control registers is supported by all instructions.

NOTE:

Six bits of port P2, P2.0 to P2.5, are available on external pins, but all control and data bits for port
P2 are implemented. Port P3 has no interrupt capability. Port P3 is implemented in MSP430x12x2
only.

brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.

watchdog timer

The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.

USART0 (MSP430x12x2 Only)

The MSP430x12x2 devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.

ADC10

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

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timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.

Timer_A3 Signal Connections

Input Pin Number

Output Pin Number

DW and PW

RHB

Device Input

Signal

Module

Input Name

Module

Block

Module Output

Signal

DW and PW

RHB

'11x2

20-Pin

'12x2

28-Pin

'11x2/12x2

32-Pin

Device Input

Signal

Module

Input Name

Module

Block

Module Output

Signal

'11x2

20-Pin

'12x2

28-Pin

'11x2/12x2

32-Pin

13 - P1.0

21 - P1.0

TACLK

ACLK

Timer

SMCLK

Timer

9 - P2.1

7 - P2.1

INCLK

14 - P1.1

22 - P1.1

TA0

CCI0A

14 - P1.1

22 - P1.1

10 - P2.2

8 - P2.2

TA0

CCI0B

CCR0

TA0

18 - P1.5

26 - P1.5

DVSS

GND

CCR0

TA0

10 - P2.2

8 - P2.2

DVCC

VCC

ADC10 Internal

15 - P1.2

23 - P1.2

TA1

CCI1A

15 - P1.2

23 - P1.2

11 - P2.3

19 - P2.3

18 - P2.3

TA1

CCI1B

CCR1

TA1

19 - P1.6

27 - P1.6

DVSS

GND

CCR1

TA1

11 - P2.3

19 - P2.3

18 - P2.3

DVCC

VCC

ADC10 Internal

16 - P1.3

24 - P1.3

TA2

CCI2A

16 - P1.3

24 - P1.3

ACLK (internal)

CCI2B

CCR2

TA2

20 - P1.7

28 - P1.7

DVSS

GND

CCR2

TA2

12 - P2.4

20 - P2.4

19 - P2.4

DVCC

VCC

ADC10 Internal

MSP430x11x2, MSP430x12x2

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peripheral file map

PERIPHERALS WITH WORD ACCESS

ADC10

ADC data transfer start address
ADC memory
ADC control register 1
ADC control register 0

ADC10SA
ADC10MEM
ADC10CTL1
ADC10CTL0

1BCh
1B4h
1B2h
1B0h

ADC control register 0
ADC analog enable
ADC data transfer control register 1
ADC data transfer control register 0

ADC10CTL0
ADC10AE
ADC10DTC1
ADC10DTC0

1B0h
04Ah
049h
048h

Timer_A

Reserved
Reserved
Reserved
Reserved
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Reserved
Reserved
Reserved
Reserved
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector

TACCR2
TACCR1
TACCR0
TAR

TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV

017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
0166h
0164h
0162h
0160h
012Eh

Flash Memory

Flash control 3
Flash control 2
Flash control 1

FCTL3
FCTL2
FCTL1

012Ch
012Ah
0128h

Watchdog

Watchdog/timer control

WDTCTL

0120h

PERIPHERALS WITH BYTE ACCESS

USART0
(in MSP430x12x2 only)

Transmit buffer
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control

U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL

077h
076h
075h
074h
073h
072h
071h
070h

Basic Clock

Basic clock sys. control2
Basic clock sys. control1
DCO clock freq. control

BCSCTL2
BCSCTL1
DCOCTL

058h
057h
056h

Port P2

Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input

P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN

02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h

Port P1

Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input

P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN

026h
025h
024h
023h
022h
021h
020h

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

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peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Port P3
(in MSP430x12x2 only)

Port P3 selection
Port P3 direction
Port P3 output
Port P3 input

P3SEL
P3DIR
P3OUT
P3IN

01Bh
01Ah
019h
018h

Special Function

Module enable2
Module enable1
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1

ME2
ME1
IFG2
IFG1
IE2
IE1

005h
004h
003h
002h
001h
000h

absolute maximum ratings

Voltage applied at V

to V

-0.3 V to 4.1 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any pin (see Note)

-0.3 V to V

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode current at any device terminal

2 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, T

stg

(unprogrammed device)

-55

C to 150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, T

stg

(programmed device)

-40

C to 85

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied

to the TEST pin when blowing the JTAG fuse.

recommended operating conditions

MIN

NOM

MAX

UNITS

Supply voltage during program execution, VCC (see Note 1)

MSP430F11x2

1.8

3.6

Supply voltage during program execution, VCC (see Note 1)

MSP430F11x2
MSP430F12x2

1.8

3.6

Supply voltage during program/erase flash memory, VCC

MSP430F11x2
MSP430F12x2

2.7

3.6

Supply voltage, VSS

Operating free-air temperature range, TA

MSP430F11x2
MSP430F12x2

-40

LFXT1 crystal frequency, f(LFXT1)

LF mode selected, XTS=0

Watch crystal

32 768

LFXT1 crystal frequency, f(LFXT1)
(see Note 2)

XT1 selected mode, XTS=1

Ceramic resonator

450

8000

kHz

(see Note 2)

XT1 selected mode, XTS=1

Crystal

1000

8000

kHz

Processor frequency f(system) (MCLK signal)

VCC = 1.8 V,
MSP430F11x2
MSP430F12x2

4.15

MHz

Processor frequency f(system) (MCLK signal)

VCC = 3.6 V,
MSP430F11x2
MSP430F12x2

MHz

NOTES:

1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 M

from XOUT to VSS when VCC <2.5 V.

The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC

2.2 V.

The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC

2.8 V.

2. The LFXT1 oscillator in LF-mode requires a watch crystal.

The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal.

MSP430x11x2, MSP430x12x2

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

4.15 MHz

at 1.8 V

MSP430F11x2 and MSP430F12x2 Devices

NOTE: Minimum processor frequency is defined by system clock. Flash

program or erase operations require a minimum VCC of 2.7 V.

VCC - Supply Voltage - V

8 MHz at 3.6 V

- Maximum Processor Frequency - MHz

f (system)

Figure 1. Frequency vs Supply Voltage

supply current (into V

) excluding external current

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TA = -40

C +85

fMCLK = f(SMCLK) = 1 MHz,

VCC = 2.2 V

200

250

I(AM)

Active mode

fMCLK = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz,
Program executes in Flash

VCC = 3 V

300

350

I(AM)

Active mode

TA = -40

C +85

f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz,

VCC = 2.2 V

f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz,
Program executes in Flash

VCC = 3 V

I(CPUOff) Low-power mode, (LPM0)

TA = -40

C +85

f(MCLK) = 0, f(SMCLK) = 1 MHz,

VCC = 2.2 V

I(CPUOff) Low-power mode, (LPM0)

f(MCLK) = 0, f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz

VCC = 3 V

I(LPM2)

Low-power mode, (LPM2)

TA = -40

C +85

f(MCLK) = f(SMCLK) = 0 MHz,

VCC = 2.2 V

I(LPM2)

Low-power mode, (LPM2)

f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0

VCC = 3 V

TA = -40

0.8

1.2

TA = 25

VCC = 2.2 V

0.7

I(LPM3)

Low-power mode, (LPM3)

TA = 85

VCC = 2.2 V

1.6

2.3

I(LPM3)

Low-power mode, (LPM3)

TA = -40

1.8

2.2

TA = 25

VCC = 3 V

1.6

1.9

TA = 85

VCC = 3 V

2.3

3.4

TA = -40

0.1

0.5

I(LPM4)

Low-power mode, (LPM4)

TA = 25

VCC = 2.2 V/3 V

0.1

0.5

I(LPM4)

Low-power mode, (LPM4)

TA = 85

VCC = 2.2 V/3 V

0.8

1.9

NOTES:

1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)

current consumption of active mode versus system frequency

= I

AM[1 MHz]

system

[MHz]

current consumption of active mode versus supply voltage

= I

AM[3 V]

+ 120

A/V

-3 V)

Schmitt-trigger inputs Port P1 to Port P3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIT+

Positive-going input threshold voltage

VCC = 2.2 V

1.1

1.5

VIT+

Positive-going input threshold voltage

VCC = 3 V

1.5

1.9

VIT-

Negative-going input threshold voltage

VCC = 2.2 V

0.4

0.9

VIT-

Negative-going input threshold voltage

VCC = 3 V

0.9

1.3

Vhys

Input voltage hysteresis, (VIT+ - VIT-)

VCC = 2.2 V

0.3

1.1

Vhys

Input voltage hysteresis, (VIT+ - VIT-)

VCC = 3 V

0.5

standard inputs - RST/NMI; TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIL

Low-level input voltage

VCC = 2.2 V / 3 V

VSS

VSS+0.6

VIH

High-level input voltage

VCC = 2.2 V / 3 V

0.8

VCC

inputs Px.x, TAx

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Port P1, P2: P1.x to P2.x, External trigger signal

2.2 V/3 V

1.5

cycle

t(int)

External interrupt timing

Port P1, P2: P1.x to P2.x, External trigger signal
for the interrupt flag, (see Note 1)

2.2 V

t(int)

External interrupt timing

for the interrupt flag, (see Note 1)

3 V

t(cap)

Timer_A, capture timing

TA0, TA1, TA2

2.2 V

t(cap)

Timer_A, capture timing

TA0, TA1, TA2

3 V

f(TAext)

Timer_A clock frequency

TACLK, INCLK t(H) = t(L)

2.2 V

MHz

f(TAext)

Timer_A clock frequency
externally applied to pin

TACLK, INCLK t(H) = t(L)

3 V

MHz

f(TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

2.2 V

MHz

f(TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

3 V

MHz

NOTES:

1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with

trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.

leakage current

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Ilkg(Px.x)

High-impedance leakage current

Port P1: P1.x, 0

(see Notes 1 and 2)

2.2 V/3 V

Ilkg(Px.x)

High-impedance leakage current

Port P2: P2.x, 0

(see Notes 1 and 2)

2.2 V/3 V

NOTES:

1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional

pullup or pulldown resistor.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)

outputs Port 1 to Port 3; P1.0 to P1.7, P2.0 to P2.5, P3.0 to P3.7

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I(OHmax) = -1.5 mA

VCC = 2.2 V

See Note 1

VCC-0.25

VCC

VOH

High-level output voltage

I(OHmax) = -6 mA

VCC = 2.2 V

See Note 2

VCC-0.6

VCC

VOH

High-level output voltage

I(OHmax) = -1.5 mA

VCC = 3 V

See Note 1

VCC-0.25

VCC

I(OHmax) = -6 mA

VCC = 3 V

See Note 2

VCC-0.6

VCC

I(OLmax) = 1.5 mA

VCC = 2.2 V

See Note 1

VSS

VSS+0.25

VOL

Low-level output voltage

I(OLmax) = 6 mA

VCC = 2.2 V

See Note 2

VSS

VSS+0.6

VOL

Low-level output voltage

I(OLmax) = 1.5 mA

VCC = 3 V

See Note 1

VSS

VSS+0.25

I(OLmax) = 6 mA

VCC = 3 V

See Note 2

VSS

VSS+0.6

NOTES:

1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed

12 mA to hold the maximum voltage

drop specified.

2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed

48 mA to hold the maximum voltage

drop specified.

outputs P1.x, P2.x, P3.x, TAx

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

f(P20)

P2.0/ACLK, CL = 20 pF

2.2 V/3 V

fSystem

f(TAx)

Output frequency

TA0, TA1, TA2, CL = 20 pF,
Internal clock source, SMCLK signal applied (see Note 1)

2.2 V/3 V

fSystem

MHz

fSMCLK = fLFXT1 = fXT1

40%

60%

P1.4/SMCLK,

fSMCLK = fLFXT1 = fLF

2.2 V/3 V

35%

65%

P1.4/SMCLK,
CL = 20 pF

fSMCLK = fLFXT1/n

2.2 V/3 V

50%-

15 ns

50%

50%+

15 ns

t(Xdc)

Duty cycle of O/P
frequency

fSMCLK = fDCOCLK

2.2 V/3 V

50%-

15 ns

50%

50%+

15 ns

frequency

P2.0/ACLK,

fP20 = fLFXT1 = fXT1

40%

60%

P2.0/ACLK,
CL = 20 pF

fP20 = fLFXT1 = fLF

2.2 V/3 V

30%

70%

CL = 20 pF

fP20 = fLFXT1/n

2.2 V/3 V

50%

t(TAdc)

TA0, TA1, TA2,

CL = 20 pF, Duty cycle = 50%

2.2 V/3 V

NOTES:

1. The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)

outputs - Ports P1, P2, and P3 (see Note)

Figure 2

VOL - Low-Level Output Voltage - V

0.0

0.5

1.0

1.5

2.0

2.5

VCC = 2.2 V
P1.0

TA = 25

TA = 85

OLI

ypical Low-Level Output Current - mA

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

Figure 3

VOL - Low-Level Output Voltage - V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VCC = 3 V
P1.0

TA = 25

TA = 85

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

OLI

ypical Low-Level Output Current - mA

Figure 4

VOH - High-Level Output Voltage - V

-28

-24

-20

-16

-12

-8

-4

0.0

0.5

1.0

1.5

2.0

2.5

VCC = 2.2 V
P1.0

TA = 25

TA = 85

OHI

ypical High-Level Output Current - mA

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

Figure 5

VOH - High-Level Output Voltage - V

-60

-50

-40

-30

-20

-10

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VCC = 3 V
P1.0

TA = 25

TA = 85

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

OHI

ypical High-Level Output Current - mA

NOTE:

Only one output is loaded at a time.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)

USART (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t( )

USART: deglitch time

VCC = 2.2 V

200

430

800

)

USART: deglitch time

VCC = 3 V

150

280

500

NOTES:

1. The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(

) to ensure that the URXS

flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(

). The operating conditions

to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on
the URXD line.

RAM

PARAMETER

MIN

NOM

MAX

UNIT

V(RAMh)

CPU halted (see Note 1)

1.6

NOTES:

1. This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No

program execution should happen during this supply voltage condition.

POR brownout, reset (see Notes 1 and 2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(BOR)

2000

VCC(start)

dVCC/dt

3 V/s

0.7

V(B_IT-)

Brownout

dVCC/dt

3 V/s

1.71

Vhys(B_IT-)

Brownout

dVCC/dt

3 V/s

130

180

t(reset)

Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 2.2 V/3 V

NOTES:

1. The current consumption of the brown-out module is already included in the ICC current consumption data.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-).

The default DCO settings must not be changed until VCC

VCC(min). See the MSP430x1xx Family User's Guide for more

information on the brownout circuit.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)

td(BOR)

VCC

V(B_IT-)

Vhys(B_IT-)

VCC(start)

Set signal for
POR circuitry

Figure 6. POR/Brownout Reset (BOR) vs Supply Voltage

VCC(min)

VCC
3 V

t pw

0.50

1.50

0.001

1000

V = 3.0 V

Typical Conditions

1ns

tpw - Pulse Width -

CC(min)

- V

tpw - Pulse Width -

Figure 7. V

CC(min)

Level With a Square Voltage Drop to Generate a POR/Brownout Signal

VCC

0.50

1.50

VCC(min)

t pw

tpw - Pulse Width -

CC(min)

- V

3 V

0.001

1000

tfall

trise

tpw - Pulse Width -

tfall = trise

V = 3.0 V

Typical Conditions

Figure 8. V

CC(min)

Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)

crystal oscillator,LFXT1

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

CXIN

Pin load

XTS=0; LF mode selected

2.2 V / 3 V

CXIN

Pin load
capacitance

XTS=1; XT1 mode selected (see Note 1)

2.2 V / 3 V

CXOUT

Pin load
capacitance

XTS=0; LF mode selected

2.2 V / 3 V

CXOUT

Pin load
capacitance

XTS=1; XT1 mode selected (see Note 1)

2.2 V / 3 V

VIL

Input levels at XIN

see Note 2

2.2 V / 3 V

VSS

0.2

VCC

VIH

Input levels at XIN

see Note 2

2.2 V / 3 V

0.8

VCC

NOTES:

1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

DCO

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

f(DCO03)

Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25

2.2 V

0.08

0.12

0.15

MHz

f(DCO03)

Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25

3 V

0.08

0.13

0.16

MHz

f(DCO13)

Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25

2.2 V

0.14

0.19

0.23

MHz

f(DCO13)

Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25

3 V

0.14

0.18

0.22

MHz

f(DCO23)

Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25

2.2 V

0.22

0.3

0.36

MHz

f(DCO23)

Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25

3 V

0.22

0.28

0.34

MHz

f(DCO33)

Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25

2.2 V

0.37

0.49

0.59

MHz

f(DCO33)

Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25

3 V

0.37

0.47

0.56

MHz

f(DCO43)

Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25

2.2 V

0.61

0.77

0.93

MHz

f(DCO43)

Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25

3 V

0.61

0.75

0.9

MHz

f(DCO53)

Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25

2.2 V

1.2

1.5

MHz

f(DCO53)

Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25

3 V

1.3

1.5

MHz

f(DCO63)

Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25

2.2 V

1.6

1.9

2.2

MHz

f(DCO63)

Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25

3 V

1.69

2.29

MHz

f(DCO73)

Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25

2.2 V

2.4

2.9

3.4

MHz

f(DCO73)

Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25

3 V

2.7

3.2

3.65

MHz

f(DCO77)

Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25

2.2 V

4.5

4.9

MHz

f(DCO77)

Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25

3 V

4.4

4.9

5.4

MHz

f(DCO47)

Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25

2.2 V/3 V

fDCO40

MHz

f(DCO47)

Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25

2.2 V/3 V

fDCO40

x1.7

fDCO40

x2.1

fDCO40

x2.5

MHz

S(Rsel)

SR = fRsel+1/fRsel

2.2 V/3 V

1.35

1.65

ratio

S(DCO)

SDCO = fDCO+1/fDCO

2.2 V/3 V

1.07

1.12

1.16

ratio

Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1)

2.2 V

-0.31

-0.36

-0.4

Temperature drift, Rsel = 4, DCO = 3, MOD = 0 (see Note 1)

3 V

-0.33

-0.38

-0.43

Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0
(see Note 1)

2.2 V/3 V

%/V

NOTES:

1. These parameters are not production tested.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)

ÎÎÎÎÎÎ

2.2 V

3 V

VCC

Max

Min

Max

Min

f(DCOx7)

f(DCOx0)

Frequency V

ariance

DCO Steps

f DCOCLK

Figure 9. DCO Characteristics

principle characteristics of the DCO

Individual devices have a minimum and maximum operation frequency. The specified parameters for
f

DCOx0

to f

DCOx7

are valid for all devices.

The DCO control bits DCO0, DCO1 and DCO2 have a step size as defined in parameter S

DCO

The modulation control bits MOD0 to MOD4 select how often f

DCO+1

is used within the period of 32 DCOCLK

cycles. f

DCO

is used for the remaining cycles. The frequency is an average = f

DCO

MOD/32

All ranges selected by R

sel(n)

overlap with R

sel(n+1)

: R

sel0

overlaps with R

sel1

, ... R

sel6

overlaps with R

sel7

wake-up from lower power modes (LPMx)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t(LPM0)

VCC = 2.2 V/3 V

100

t(LPM2)

VCC = 2.2 V/3 V

100

f(MCLK) = 1 MHz,

VCC = 2.2 V/3 V

t(LPM3)

Delay time (see Note 1)

f(MCLK) = 2 MHz,

VCC = 2.2 V/3 V

t(LPM3)

Delay time (see Note 1)

f(MCLK) = 3 MHz,

VCC = 2.2 V/3 V

f(MCLK) = 1 MHz,

VCC = 2.2 V/3 V

t(LPM4)

f(MCLK) = 2 MHz,

VCC = 2.2 V/3 V

t(LPM4)

f(MCLK) = 3 MHz,

VCC = 2.2 V/3 V

NOTES:

1. Parameter applicable only if DCOCLK is used for MCLK.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)

10-bit ADC, power supply and input range conditions (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

VCC

Analog supply voltage

VSS = 0 V

2.2

3.6

V(P6.x/Ax)

Analog input voltage
range (see Note 2)

All Ax terminals. Analog inputs
selected in ADC10AE register and PxSel.x=1
VSS

VPx.x/Ax

VCC

IADC10

Operating supply current
into VCC terminal

fADC10CLK = 5.0 MHz
ADC10ON = 1, REFON = 0

2.2 V

0.52

1.05

IADC10

into VCC terminal
(see Note 3)

ADC10ON = 1, REFON = 0
ADC10SHT0=1, ADC10SHT1=0,
ADC10DIV=0

3 V

0.6

1.2

IREF+

Reference operating
supply current,
reference buffer disabled
(see Note 4)

fADC10CLK = 5.0 MHz
ADC10ON = 0,
REFON = 1, REF2_5V = x;
REFOUT = 0

2.2V/3 V

0.25

0.4

IREFB

Reference buffer
operating supply current

fADC10CLK = 5.0 MHz
ADC10ON = 0,

ADC10SR = 0

1.1

1.4

IREFB

operating supply current
(see Note 4)

ADC10ON = 0,
REFON = 1, REF2_5V = 0
REFOUT = 1

ADC10SR = 1

0.46

0.55

Input capacitance

Only one terminal can be selected
at one time, Px.x/Ax

2.2 V

Input MUX ON resistance

VAx

VCC

3 V

2000

Not production tested, limits verified by design
NOTES:

1. The leakage current is defined in the leakage current table with Px.x/Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter IADC10.
4. The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

10-bit ADC, external reference (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

VeREF+

Positive external
reference voltage input

VeREF+ > VREF-/VeREF- (see Note 2)

1.4

VCC

VREF- /VeREF-

Negative external
reference voltage input

VeREF+ > VREF-/VeREF- (see Note 3)

1.2

(VeREF+ -
VREF-/VeREF-)

Differential external
reference voltage input

VeREF+ > VREF-/VeREF- (see Note 4)

1.4

VCC

IVeREF+

Static input current

VeREF+

VCC

2.2 V/3 V

IVREF-/VeREF-

Static input current

VeREF-

VCC

2.2 V/3 V

NOTES:

1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also

the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)

10-bit ADC, built-in reference

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

VREF+

Positive built-in reference

REF2_5V = 1 for 2.5 V
IVREF+

IVREF+max

3 V

2.35

2.5

2.65

VREF+

Positive built-in reference
voltage output

REF2_5V = 0 for 1.5 V
IVREF+

IVREF+max

2.2 V/3 V

1.41

1.5

1.59

VCC minimum voltage,

REF2_5V = 0, IVREF+

1mA

2.2

VCC(min)

VCC minimum voltage,
Positive built-in reference
active

REF2_5V = 1, IVREF+

0.5mA

VREF+ + 0.15

VCC(min)

Positive built-in reference
active

REF2_5V = 1, IVREF+

1mA

VREF+ + 0.15

IVREF+

Load current out of VREF+

2.2 V

0.5

IVREF+

Load current out of VREF+
terminal

3 V

IVREF+ = 500

A +/- 100

Analog input voltage ~0.75 V;

2.2 V

LSB

IL(VREF)+

Load-current regulation

VREF+

Analog input voltage ~0.75 V;
REF2_5V = 0

3 V

LSB

IL(VREF)+

Load-current regulation
VREF+ terminal

IVREF+ = 500

100

Analog input voltage ~1.25 V;
REF2_5V = 1

3 V

LSB

tDL(VREF) +

Load current regulation

IVREF+ =100

900

VCC=3 V, Ax ~0.5 x VREF+

ADC10SR = 0

400

tDL(VREF) +

Load current regulation
VREF+ terminal

VREF+

VCC=3 V, Ax ~0.5 x VREF+
Error of conversion result

1 LSB

ADC10SR = 1

2000

CVREF+

Capacitance at pin VREF+
(see Note 1)

REFON =1, IVREF+

1 mA

2.2 V/3 V

100

TREF+

Temperature coefficient of
built-in reference

IVREF+ is a constant in the range of
0 mA

IVREF+

1 mA

2.2 V/3 V

100

ppm/

Settle time of internal
reference voltage and

IVREF+ = 0.5 mA,VREF+ = 1.5 V, VCC = 3.6 V,
REFON = 0

tREFON

reference voltage and
VREF+
(see Note 2)

IVREF+ = 0.5 mA, VREF+ = 1.5 V,

ADC10SR = 0

0.8

VREF+
(see Note 2)

IVREF+ = 0.5 mA, VREF+ = 1.5 V,
VCC = 2.2 V, REFON = 1

ADC10SR = 1

2.5

Not production tested, limits characterized
Not production tested, limits verified by design
NOTES:

1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT=1),

must be limited; the reference buffer may become unstable otherwise.

NOTES:

2. The condition is that the error in a conversion started after tREFON is less than

0.5 LSB.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)

10-bit ADC, timing parameters

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

fADC10CLK

Error of conversion result

ADC10SR = 0

0.450

6.3

MHz

fADC10CLK

Error of conversion result

LSB

ADC10SR = 1

0.450

1.5

MHz

fADC10OSC

ADC10DIV=0,
fADC10CLK=fADC10OSC

2.2 V/ 3V

3.7

6.3

MHz

tCONVERT

Conversion time

Internal oscillator,
fADC10OSC = 3.7 MHz to
6.3 MHz

2.2 V/ 3 V

2.06

3.51

tCONVERT

Conversion time

External fADC10CLK from ACLK, MCLK or SMCLK:
ADC10SSEL

ADC10DIV

1/fADC10CLK

tADC10ON

Turn on settling time of
the ADC

(see Note 1)

100

tSample

Sampling time

RS = 400

, RI = 2000

3 V

1400

tSample

Sampling time

RS = 400

, RI = 2000

CI = 20 pF (see Note 2)

2.2 V

1400

Not production tested, limits characterized
Not production tested, limits verified by design
NOTES:

1. The condition is that the error in a conversion started after tADC10ON is less than

0.5 LSB. The reference and input signal are already

settled.

2. Approximately eight Tau (

) are needed to get an error of less than

0.5 LSB.

tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns. (ADC10SR = 0, n = ADC resolution = 10, RS = external source resistance)
tSample = ln(2n+1) x (RS + RI) x CI+ 2.5

s. (ADC10SR = 1, n = ADC resolution = 10, RS = external source resistance)

10-bit ADC, linearity parameters

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Integral linearity error

1.4 V

(VeREF+ - VREF-/VeREF-) min

1.6 V

2.2 V/3 V

LSB

Integral linearity error

1.6 V < (VeREF+ - VREF-/VeREF-) min

[VCC]

2.2 V/3 V

LSB

Differential linearity
error

(VeREF+ - VREF-/VeREF-)min

(VeREF+ - VREF-/VeREF-) 2.2 V/3 V

LSB

Offset error

(VeREF+ - VREF-/VeREF-)min

(VeREF+ - VREF-/VeREF-),

Internal impedance of source RS < 100

2.2 V/3 V

LSB

Gain error

(VeREF+ - VREF-/VeREF-)min

(VeREF+ - VREF-/VeREF-), 2.2 V/3 V

1.1

LSB

Total unadjusted
error

(VeREF+ - VREF-/VeREF-)min

(VeREF+ - VREF-/VeREF-), 2.2 V/3 V

LSB

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)

10-bit ADC, temperature sensor and built-in V

MID

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ISENSOR

Operating supply current into

REFON = 0, INCH = 0Ah,

2.2 V

120

ISENSOR

Operating supply current into
VCC terminal (see Note 1)

REFON = 0, INCH = 0Ah,
ADC10ON=NA, TA = 25

3 V

160

VSENSOR

ADC10ON = 1, INCH = 0Ah,

2.2 V

986

VSENSOR

ADC10ON = 1, INCH = 0Ah,
TA = 0

3 V

986

TCSENSOR

ADC10ON = 1, INCH = 0Ah

2.2 V

3.55

mV/

TCSENSOR

ADC10ON = 1, INCH = 0Ah

3 V

3.55

mV/

tSENSOR(sample)

Sample time required if channel

ADC10ON = 1, INCH = 0Ah,

2.2 V

tSENSOR(sample)

Sample time required if channel
10 is selected (see Note 2)

ADC10ON = 1, INCH = 0Ah,
Error of conversion result

1 LSB

3 V

IVMID

Current into divider at channel 11

ADC10ON = 1, INCH = 0Bh,

2.2 V

IVMID

Current into divider at channel 11
(see Note 3)

ADC10ON = 1, INCH = 0Bh,

3 V

VMID

VCC divider at channel 11

ADC10ON = 1, INCH = 0Bh,

2.2 V

1.1

0.04

VMID

VCC divider at channel 11

ADC10ON = 1, INCH = 0Bh,
VMID is ~0.5 x VCC

3 V

1.5

1.50

0.04

tVMID(sample)

Sample time required if channel

ADC10ON = 1, INCH = 0Bh,

2.2 V

1400

tVMID(sample)

Sample time required if channel
11 is selected (see Note 4)

ADC10ON = 1, INCH = 0Bh,
Error of conversion result

1 LSB

3 V

1220

Not production tested, limits characterized
NOTES:

1. The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal

is high). Therefore it includes the constant current through the sensor and the reference.

2. The typical equivalent impedance of the sensor is 51 k

. The sample time required includes the sensor-on time tSENSOR(on).

3. No additional current is needed. The VMID is used during sampling.
4. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)

Flash Memory

PARAMETER

TEST

CONDITIONS

VCC

MIN

NOM

MAX

UNIT

VCC(PGM/
ERASE)

Program and Erase supply voltage

2.7

3.6

fFTG

Flash Timing Generator frequency

257

476

kHz

IPGM

Supply current from VCC during program

2.7 V/ 3.6 V

IERASE

Supply current from VCC during erase

2.7 V/ 3.6 V

tCPT

Cumulative program time

see Note 1

2.7 V/ 3.6 V

tCMErase

Cumulative mass erase time

see Note 2

2.7 V/ 3.6 V

200

Program/Erase endurance

104

105

cycles

tRetention

Data retention duration

TJ = 25

100

years

tWord

Word or byte program time

tBlock, 0

Block program time for 1st byte or word

tBlock, 1-63

Block program time for each additional byte or word

see Note 3

tFTG

tBlock, End

Block program end-sequence wait time

see Note 3

tFTG

tMass Erase

Mass erase time

5297

tSeg Erase

Segment erase time

4819

NOTES:

1. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write

feature is used.

2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To

achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).

3. These values are hardwired into the Flash Controller's state machine; tFTG = 1/fFTG.

JTAG Interface

PARAMETER

TEST

CONDITIONS

VCC

MIN

NOM

MAX

UNIT

fTCK

TCK input frequency

see Note 1

2.2 V

MHz

fTCK

TCK input frequency

see Note 1

3 V

MHz

RInternal

Internal pull-up resistance on TMS, TCK, TDI/TCLK

see Note 2

2.2 V/ 3 V

NOTES:

1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all Flash versions.

JTAG Fuse (see Note 1)

PARAMETER

TEST

CONDITIONS

VCC

MIN

NOM

MAX

UNIT

VCC(FB)

Supply voltage during fuse-blow condition

TA = 25

2.5

VFB

Voltage level on TEST for fuse-blow

IFB

Supply current into TEST during fuse blow

100

tFB

Time to blow fuse

NOTES:

1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched

to bypass mode.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic

Port P1, P1.0 to P1.3, input/output with Schmitt-trigger

P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2

Interrupt

Edge

Select

Set

P1IE.x

P1IFG.x

P1IRQ.x

Interrupt
Flag

P1IES.x

P1SEL.x

Module X IN

P1IN.x

P1OUT.x

Module X OUT

Direction Control

From Module

P1DIR.x

P1SEL.x

Pad Logic

NOTE: x = Bit/identifier, 0 to 3 for port P1

PnSel.x

PnDIR.x

DIRECTION

CONTROL FROM

MODULE

PnOUT.x

MODULE X OUT

PnIN.x

MODULE X IN

PnIE.x

PnIFG.x

PnIES.x

P1Sel.0

P1DIR.0

P1OUT.0

ADC10CLK

P1IN.0

TACLK

P1IE.0

P1IFG.0

P1IES.0

P1Sel.1

P1DIR.1

P1OUT.1

Out0 signal

P1IN.1

CCI0A

P1IE.1

P1IFG.1

P1IES.1

P1Sel.2

P1DIR.2

P1OUT.2

Out1 signal

P1IN.2

CCI1A

P1IE.2

P1IFG.2

P1IES.2

P1Sel.3

P1DIR.3

P1OUT.3

Out2 signal

P1IN.3

CCI2A

P1IE.3

P1IFG.3

P1IES.3

Signal from or to Timer_A

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features

P1.4-P1.7

Interrupt

Edge

Select

Set

P1IE.x

P1IFG.x

P1IRQ.x

Interrupt
Flag

P1IES.x

P1SEL.x

Module X IN

P1IN.x

P1OUT.x

Module X OUT

Direction Control

From Module

P1DIR.x

P1SEL.x

Pad Logic

Bus Keeper

60 k

Control by

JTAG

TDO

Controlled By JTAG

P1.x

TDI

P1.x

TST

TMS

TST

TCK

TST

Controlled by JTAG

TST

P1.x

NOTE: The test pin should be protected from potential EMI

and ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.

x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing
the fuse, the pin TDO/TDI is used to apply the test
input for JTAG circuitry.

P1.7/TA2/TDO/TDI

P1.6/TA1/TDI/TCLK

P1.5/TA0/TMS

P1.4/SMCLK/TCK

Typical

TEST

Bum

and

Test Fuse

DVCC

PnSel.x

PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x

MODULE X OUT

PnIN.x

MODULE X IN

PnIE.x

PnIFG.x

PnIES.x

P1Sel.4

P1DIR.4

P1OUT.4

SMCLK

P1IN.4

unused

P1IE.4

P1IFG.4

P1IES.4

P1Sel.5

P1DIR.5

P1OUT.5

Out0 signal

P1IN.5

unused

P1IE.5

P1IFG.5

P1IES.5

P1Sel.6

P1DIR.6

P1OUT.6

Out1 signal

P1IN.6

unused

P1IE.6

P1IFG.6

P1IES.6

P1Sel.7

P1DIR.7

P1OUT.7

Out2 signal

P1IN.7

unused

P1IE.7

P1IFG.7

P1IES.7

Signal from or to Timer_A

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, P2.0 to P2.2, input/output with Schmitt-trigger

P2OUT.x

Module X Out

P2DIR.x

Direction Control

From Module

P2SEL.x

Interrupt

Edge

Select

P2IES.x

P2SEL.x

P2IE.x

P2IFG.x

P2IRQ.x

Set

to ADC10,

P2.0/ACLK/A0

P2.1/INCLK/A1

P2.2/TA0/A2

Module X In

P2IN.x

a0, or a1, or a2

selected in

ADC10

Pad Logic

0: input
1: output

Bus

Keeper

ADC10AE.x

NOTE: 0

a0, or a1, or a2

PnSel.x

PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x

MODULE X OUT

PnIN.x

MODULE X IN

PnIE.x

PnIFG.x

PnIES.x

P2Sel.0

P2DIR.0

P2OUT.0

ACLK

P2IN.0

unused

P2IE.0

P2IFG.0

P1IES.0

P2Sel.1

P2DIR.1

P2OUT.1

VSS

P2IN.1

INCLK

P2IE.1

P2IFG.1

P1IES.1

P2Sel.2

P2DIR.2

P2OUT.2

OUT0 signal

P2IN.2

CCI0B

P2IE.2

P2IFG.2

P1IES.2

Timer_A

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, P2.3 to P2.4, input/output with Schmitt-trigger

P2OUT.4

Module X Out

P2DIR.4

P2SEL.4

Interrupt

Edge

Select

P2IES.4

P2SEL.4

P2IE.4

P2IFG.4

P2IRQ.07

Set

to ADC10, a4

P2.4/

Unused

P2IN.4

a4 Selected

Pad Logic

0: input
1: output

Bus

Keeper

ADC10AE.4

P2DIR.4

TA2/
A4/
V

REF+

P2OUT.3

Module X Out

P2DIR.3

P2SEL.3

Interrupt

Edge

Select

P2IES.x

P2SEL.x

P2IE.4

P2IFG.4

P2IRQ.07

Set

to ADC10, a3

P2.3/

Module X In

P2IN.4

a3 Selected

Pad Logic

0: input
1: output

Bus

Keeper

ADC10AE.3

P2DIR.3

TA1/
A3/
VREF-

Reference Circuit

in ADC10 Module

Typ.

1.25 V

a10 on REFON

REF_x

OUT

REF+

2_5 V

V +

V -

SREF

ADC10

CTL0.12..14)

SREF.2

ADC10

CTL0.14)

0,4

1,5

/V eREF-

VeREF+

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P2, P2.3 to P2.4, input/output with Schmitt-trigger (continued)

PnSel.x

PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x

MODULE X OUT

PnIN.x

MODULE X IN

PnIE.x

PnIFG.x

PnIES.x

P2Sel.3

P2DIR.3

P2OUT.3

Out1 signal

P2IN.3

CCI1B

P2IE.3

P2IFG.3

P1IES.3

P2Sel.4

P2DIR.4

P2OUT.4

Out2 signal

P2IN.4

Unused

P2IE.4

P2IFG.4

P1IES.4

Timer_A

input/output schematic (continued)

Port P2, P2.5, input/output with Schmitt-trigger and R

OSC

function for the Basic Clock Module

P2.5/ROSC

Interrupt

Edge

Select

Set

P2IE.5

P2IFG.5

P2IRQ.5

Interrupt
Flag

P2IES.5

P2SEL.5

Module X IN

P2IN.5

P2OUT.5

Module X OUT

Direction Control

From Module

P2DIR.5

P2SEL.5

Pad Logic

NOTE: DCOR: Control bit from Basic Clock Module: if it is set P2.5 is disconnected from P2.5 pad.

Bus Keeper

VCC

Internal to
Basic Clock
Module

DCOR

DC
Generator

0: Input
1: Output

PnSel.x

PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x

MODULE X OUT

PnIN.x

MODULE X IN

PnIE.x

PnIFG.x

PnIES.x

P2Sel.5

P2DIR.5

P2OUT.5

VSS

P2IN.5

unused

P2IE.5

P2IFG.5

P2IES.5

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

Port P2, unbonded bits P2.6 and P2.7

Interrupt

Edge

Select

Set

P2IE.x

P2IFG.x

P2IRQ.x

Interrupt
Flag

P2IES.x

P2SEL.x

Module X IN

P2IN.x

P2OUT.x

Module X OUT

Direction Control

From Module

P2DIR.x

P2SEL.x

Bus Keeper

0: Input
1: Output

Node Is Reset With PUC

PUC

NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins

P2Sel.x

P2DIR.x

DIRECTION

CONTROL

FROM MODULE

P2OUT.x

MODULE X OUT

P2IN.x

MODULE X IN

P2IE.x

P2IFG.x

P2IES.x

P2Sel.6

P2DIR.6

P2OUT.6

VSS

P2IN.6

unused

P2IE.6

P2IFG.6

P2IES.6

P2Sel.7

P2DIR.7

P2OUT.7

VSS

P2IN.7

unused

P2IE.7

P2IFG.7

P2IES.7

NOTE: Unbonded bits 6 and 7 of port P2 can be used as interrupt flags. Only software can affect the interrupt flags. They work as software

interrupts.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

port P3, P3.0, P3.6 and P3.7 input/output with Schmitt-trigger

P3OUT.x

Module X Out

P3DIR.x

Direction Control

From Module

P3SEL.x

To ADC10

P3.0/STE0/A5

P3.6/A6

P3.7/A7

Module X In

P3IN.x

a5, or a6, or a7

selected in

ADC10

Pad Logic

0: input
1: output

Bus

Keeper

ADC10AE.x

NOTE: x (0,6,7)

a5, or a6, or a7

PnSel.x

PnDIR.x

Direction Control

From Module

PnOUT.x

Module X OUT

PnIN.x

Module X IN

P3Sel.0

P3DIR.0

VSS

P3OUT.0

VSS

P3IN.0

STE0

P3Sel.6

P3DIR.1

P3DIR.6

P3OUT.6

VSS

P3IN.6

Unused

P3Sel.7

P3DIR.2

P3DIR.7

P3OUT.7

VSS

P3IN.7

Unused

USART0

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

port P3, P3.1 input/output with Schmitt-trigger

P3.1/SIMO0

P3IN.1

Pad Logic

P3OUT1

P3DIR.1

P3SEL.1

(SI)MO0

DCM_SIMO

SYNC

STE

STC

From USART0

SI(MO)0

To USART0

0: Input
1: Output

port P3, P3.2, input/output with Schmitt-trigger

P3.2/SOMI0

P3IN.2

Pad Logic

P3OUT.2

P3DIR.2

P3SEL.2

DCM_SOMI

SYNC

STE

STC

SO(MI)0

From USART0

(SO)MI0

To USART0

0: Input
1: Output

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

port P3, P3.3, input/output with Schmitt-trigger

P3.3/UCLK0

P3IN.3

Pad Logic

P3OUT.3

P3DIR.3

P3SEL.3

UCLK.0

DCM_UCLK

SYNC

STE

STC

From USART0

UCLK0

To USART0

0: Input
1: Output

NOTE: UART mode:

The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.

SPI, slave mode:

The clock applied to UCLK0 is used to shift data in and out.

SPI, master mode:

The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).

port P3, P3.4, and P3.5 input/output with Schmitt-trigger

P3IN.x

Module X IN

Pad Logic

P3OUT.x

P3DIR.x

P3SEL.x

Module X OUT

Direction Control

From Module

P3.4/UTXD0

P3.5/URXD0

0: Input
1: Output

x {4,5}

PnSel.x

PnDIR.x

DIRECTION

CONTROL

FROM MODULE

PnOUT.x

MODULE X OUT

PnIN.x

MODULE X IN

P3Sel.4

P3DIR.4

VCC

P3OUT.4

UTXD0

P3IN.4

Unused

P3Sel.5

P3DIR.5

VSS

P3OUT.5

VSS

P3IN.5

URXD0

Output from USART0 module
Input to USART0 module

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

APPLICATION INFORMATION

JTAG fuse check mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I

, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care

must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.

When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense
currents are terminated.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.

The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 10). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).

Time TMS Goes Low After POR

TMS

ITF

ITEST

Figure 10. Fuse Check Mode Current, MSP430F11x2, MSP430F12x2

The JTAG pins are terminated internally, and therefore do not require external termination.

NOTE:

The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader
access key is used. Also, see the bootstrap loader section for more information.

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MECHANICAL DATA

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

4040000 / D 01/00

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

0.012 (0,30)

0.004 (0,10)

0.020 (0,51)

0.014 (0,35)

0.291 (7,39)

0.299 (7,59)

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

0.600

0.610

(17,78)

0.700

(18,03)

0.710

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

- 8

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

0,10

0,25

0,50

0,75

0,15 NOM

Gage Plane

9,80

9,60

7,90

7,70

6,60

6,40

4040064/F 01/97

0,30

6,60
6,20

0,19

4,30

4,50

0,15

1,20 MAX

5,10

4,90

3,10

2,90

A MAX

A MIN

DIM

PINS **

0,05

4,90

5,10

Seating Plane

- 8

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

MSP430x11x2, MSP430x12x2

MIXED SIGNAL MICROCONTROLLER

SLAS361C - JANUARY 2002 - REVISED DECEMBER 2003

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

RHB (S-PQFP-N32)

PLASTIC QUAD FLATPACK

ÇÇÇÇÇ

4204326/A 04/02

0,05 MAX

SEATING PLANE

5,00

0,80

1,00

0,08

5,00

3,25
3,00

0,20 REF

DIE PAD

3,50

0,50
0,30

32X

0,50

0,18

0,30

0,10 M C A B

32X

EXPOSED THERMAL

0,23

0,18

PIN 1
INDEX AREA

IDENTIFIER

PIN 1

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. QFN (Quad Flatpack No-Lead) Package configuration.
D. The Package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane. This pad is

electrically and thermally connected to the backside of the die and possibly selected ground leads.

E. Falls within JEDEC MO-220.

MECHANICAL DATA

MTSS001C JANUARY 1995 REVISED FEBRUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

0,10

0,25

0,50

0,75

0,15 NOM

Gage Plane

9,80

9,60

7,90

7,70

6,60

6,40

4040064/F 01/97

0,30

6,60
6,20

0,19

4,30

4,50

0,15

1,20 MAX

5,10

4,90

3,10

2,90

A MAX

A MIN

DIM

PINS **

0,05

4,90

5,10

Seating Plane

 8

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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