FEATURES
q
Very Low Noise: 8nV/
Hz at 10kHz
q
Low V
OS
: 1mV max
q
Low Drift: 10
V/
C max
q
Low I
B
: 10pA max
q
Fast Settling Time: 2
s to 0.01%
q
Unity-Gain Stable
Precision Dual
Difet
Operational Amplifier
OPA2107
DESCRIPTION
The OPA2107 dual
operational amplifier provides precision
Difet performance with the cost and space savings of a dual
op amp. It is useful in a wide range of precision and low-noise
analog circuitry and can be used to upgrade the performance
of designs currently using BIFET
type amplifiers.
The OPA2107 is fabricated on a proprietary dielectrically
isolated (
Difet ) process. This holds input bias currents to
very low levels without sacrificing other important param-
eters, such as input offset voltage, drift and noise. Laser-
trimmed input circuitry yields excellent dc performance. Su-
perior dynamic performance is achieved, yet quiescent cur-
rent is held to under 2.5mA per amplifier. The OPA2107 is
unity-gain stable.
The OPA2107 is available in DIP-8 and SO-8 packages.
Cascode
In
(2, 6)
+In
(3, 5)
+V
(8)
S
Output
(1, 7)
V
(4)
S
APPLICATIONS
q
Data Acquisition
q
DAC Output Amplifiers
q
Optoelectronics
q
High-Impedance Sensor Amps
q
High-Performance Audio Circuitry
q
Medical Equipment, CT Scanners
OPA2107
OPA2107
SBOS161A JANUARY 1989 REVISED JULY 2003
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1989-2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
OPA2107
2
SBOS161A
www.ti.com
PIN CONFIGURATION
Top View
DIP, SO
8
7
1
4
5
3
2
6
V
S
Out B
+V
A
B
S
Out A
In B
+In B
In A
+In A
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage ...................................................................................
18V
Input Voltage Range .....................................................................
V
S
2V
Differential Input Voltage ....................................................... Total V
S
4V
Operating Temperature
P and U Packages ........................................................ 25
C to + 85
C
Storage Temperature
P and U Packages ....................................................... 40
C to +125
C
Output Short Circuit to Ground (T
A
= +25
C) ........................... Continuous
Junction Temperature .................................................................... +175
C
Lead Temperature
P Package (soldering, 10s) ......................................................... +300
C
U Package, SOIC (3s) ................................................................ +260
C
NOTE: Stresses above these ratings may cause permanent damage.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
OPA2107
DIP-8
P
25
C to +85
C
OPA2107AP
OPA2107AP
Tube, 50
OPA2107
SO-8
D
25
C to +85
C
OPA2107AU
OPA2107AU
Tube, 100
"
"
"
"
"
OPA2107AU/2K5
Tape and Reel, 2500
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PACKAGE/ORDERING INFORMATION
OPA2107
3
SBOS161A
www.ti.com
ELECTRICAL CHARACTERISTICS
At T
A
= +25
C, V
S
=
15V, unless otherwise noted.
OPA2107AP, AU
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
OFFSET VOLTAGE
(1)
Input Offset Voltage
V
CM
= 0V
0.1
1
mV
Over Specified Temperature
0.5
2
mV
Average Drift Over Specified Temperature
3
10
V/
C
Power Supply Rejection
V
S
=
10 to
18V
80
96
dB
INPUT BIAS CURRENT
(1)
Input Bias Current
V
CM
= 0V
4
10
pA
Over Specified Temperature
0.25
1.5
nA
Input Offset Current
V
CM
= 0V
1
8
pA
Over Specified Temperature
1
nA
INPUT NOISE
Voltage: f = 10Hz
R
S
= 0
30
nV/
Hz
f = 100Hz
12
nV/
Hz
f = 1kHz
9
nV/
Hz
f = 10kHz
8
nV/
Hz
BW = 0.1 to 10Hz
1.2
Vp-p
BW = 10 to 10kHz
0.85
Vrms
Current: f = 0.1Hz thru 20kHz
1.2
fA/
Hz
BW = 0.1Hz to 10Hz
23
fAp-p
INPUT IMPEDANCE
Differential
10
13
|| 2
|| pF
Common-Mode
10
14
|| 4
|| pF
INPUT VOLTAGE RANGE
Common-Mode Input Range
10.5
11
V
Over Specified Temperature
10.2
10.5
V
Common-Mode Rejection
V
CM
=
10V
80
94
dB
OPEN-LOOP GAIN
Open-Loop Voltage Gain
V
O
=
10V, R
L
= 2k
82
96
dB
Over Specified Temperature
80
94
dB
DYNAMIC RESPONSE
Slew Rate
G = +1
13
18
V/
s
Settling Time: 0.1%
G = 1, 10V Step
1.5
s
0.01%
2
s
Gain Bandwidth Product
G = 100
4.5
MHz
THD + Noise
G = +1, f = 1kHz
0.001
%
Channel Separation
f = 100Hz, R
L
= 2k
120
dB
POWER SUPPLY
Specified Operating Voltage
15
V
Operating Voltage Range
4.5
V
Current
4.5
mA
OUTPUT
Voltage Output
R
L
= 2k
11
12
V
Over Specified Temperature
10.5
11.5
V
Short Circuit Current
10
40
mA
Output Resistance, Open-Loop
1MHz
70
Capacitive Load Stability
G = +1
1000
pF
TEMPERATURE RANGE
Specification
25
+85
C
Operating
25
+85
C
Storage
40
+125
C
Thermal Resistance (
J-A
)
DIP-8
90
C/W
SO-8
175
C/W
NOTE: (1) Specified with devices fully warmed up.
OPA2107
4
SBOS161A
www.ti.com
TYPICAL CHARACTERISTICS
T
A
= +25
C, V
S
=
15V unless otherwise noted.
INPUT VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
1k
100
10
1
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Voltage Noise (nV/ Hz)
Voltage Noise
Voltage Noise
100
10
1
0.1
Current Noise (
A/ Hz)
Current Noise
Current Noise
E
O
R
S
TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY
at 1kHz vs SOURCE RESISTANCE
1k
100
10
1
100
1k
10k
100k
1M
10M
100M
Source Resistance ( )
Voltage Noise, E (n/V/ Hz)
O
OPA2107 + Resistor
Resistor Noise Only
Bias Current
Offset Current
INPUT BIAS AND OFFSET CURRENT
vs TEMPERATURE
10nA
1nA
1
50
25
0
+25
+50
+75
Ambient Temperature (C)
Bias Current (pA)
10nA
1nA
0.1
100
10
1
0.1
+100
+125
100
10
1
Offset Current (pA)
INPUT BIAS AND OFFSET CURRENT
vs INPUT COMMON-MODE VOLTAGE
10
1
0.1
0.01
Bias Current (pA)
15
10
5
0
+5
+10
+15
Common-Mode Voltage (V)
10
1
0.1
0.01
Offset Current (pA)
Offset Current
POWER SUPPLY AND COMMON-MODE
REJECTION vs FREQUENCY
120
100
80
60
40
20
0
10
100
1k
10k
100k
1M
10M
PSR, CMR (dB)
120
100
80
60
40
20
0
PSR
CMR
+PSR
Frequency (Hz)
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
110
100
90
80
70
15
10
5
0
+5
+10
+15
Common-Mode Rejection (dB)
Common-Mode Voltage (V)
OPA2107
5
SBOS161A
www.ti.com
MAXIMUM OUTPUT VOLTAGE SWING
vs FREQUENCY
30
20
10
0
Output Voltage (Vp-p)
10k
100k
1M
10M
Frequency (Hz)
R = 2k
L
GAIN-BANDWIDTH AND SLEW RATE
vs TEMPERATURE
8
6
4
2
0
50
25
0
+25
+50
+75
+100
+125
Ambient Temperature (C)
Gain-Bandwidth (MHz)
25
20
15
10
5
Slew Rate (V/s)
Slew Rate
Gain-Bandwidth
GAIN-BANDWIDTH AND SLEW RATE
vs SUPPLY VOLTAGE
6
5
4
5
10
15
20
Supply Voltage (V )
S
Gain-Bandwidth (MHz)
22
20
18
16
14
Slew Rate (V/s)
Gain-Bandwidth
Slew Rate
A = +100
R = 2k
V
L
SETTLING TIME vs CLOSED-LOOP GAIN
5
4
3
2
1
0
1
10
100
1000
Closed-Loop Gain (V/V)
Settling Time (s)
0.1%
V = 10V Step
R = 2k
C = 100pF
O
L
L
0.01%
SUPPLY CURRENT vs TEMPERATURE
7
6
5
4
3
50
25
0
+25
+50
+75
+100
+125
Ambient Temperature (C)
Supply Current (mA)
Total of Both Op Amps
TYPICAL CHARACTERISTICS
(Cont.)
T
A
= +25
C, V
S
=
15V unless otherwise noted.
OPEN-LOOP FREQUENCY RESPONSE
120
100
80
60
40
20
0
1
10
100
1k
10k
100k
1M
10M
0
45
90
135
180
Voltage Gain (dB)
Phase Shift (Degrees)
Frequency (Hz)
R = 2k
L
C = 100pF
L
A
OL
OPA2107
6
SBOS161A
www.ti.com
TYPICAL CHARACTERISTICS
(Cont.)
T
A
= +25
C, V
S
=
15V unless otherwise noted.
CHANNEL SEPARATION vs FREQUENCY
150
140
130
120
110
10
100
1k
10k
100k
Frequency (Hz)
Channel Separation (dB)
R =
L
R = 2k
L
TOTAL HARMONIC DISTORTION vs FREQUENCY
1
0.1
0.01
0.001
1
10
100
1k
10k
100k
Frequency (Hz)
THD + Noise (%rms)
A = +101V/V
V
A = +11V/V
V
A = +1V/V
V
6.5Vrms
2k
R
S
THD + NOISE vs FREQUENCY AND OUTPUT VOLTAGE
1
0.1
0.01
0.001
1
10
100
1k
10k
100k
Frequency (Hz)
THD + Noise (%rms)
Noise Limited
A = +11V/V
V
2Vp-p
Noise Limited
Noise Limited
10Vp-p
20Vp-p
2k
R
S
OPEN-LOOP GAIN vs SUPPLY VOLTAGE
120
110
100
90
80
70
5
10
15
20
Supply Voltage (V )
S
Voltage Gain (dB)
LARGE-SIGNAL RESPONSE
Time (2
s/div)
Output Voltage (5V/div)
SMALL-SIGNAL RESPONSE
Time (200ns/div)
Output Voltage (20mV/div)
OPA2107
7
SBOS161A
www.ti.com
FIGURE 2. FET Input Instrumentation Amplifier.
I
B
= 5pA Max
Gain = 100
CMRR ~ 95dB
R
IN
= 10
13
~
Differential Voltage Gain = 1 + 2R
F
/R
G
= 100
A
1
Output
3
2
B
7
6
5
1
In
+In
R
F
5k
R
F
5k
R
G
101
25k
25k
1/2
OPA2107
1/2
OPA2107
25k
25k
6
5
3
2
INA105
FIGURE 3. Precision Instrumentation Amplifier.
Using the INA106 for an output difference amplifier extends the input
common-mode range of an instrumentation amplifier (IA) to
10V.
A conventional IA with a unity-gain difference amplifier has an input
common-mode range limited to
5V for an output swing of
10V. This is
because a unity-gain difference amplifier needs
5V at the input for 10V
at the output, allowing only 5V additional for common-mode range.
E
O
= [10 (1 + 2R
F
/R
G
) (E
2
E
1
)] = 1000 (E
2
E
1
)
A
1
E
Output
3
2
B
7
6
5
1
E
In
R
F
10k
R
F
10k
R
G
202
10k
10k
1/2
OPA2107
1/2
OPA2107
100k
100k
6
5
3
2
INA106
1
O
E
+In
2
APPLICATIONS INFORMATION
AND CIRCUITS
The OPA2107 is unity-gain stable and has an excellent
phase margin. This makes it easy to use in a wide variety of
applications.
Power-supply connections should be bypassed with capaci-
tors positioned close to the amplifier pins. In most cases,
0.1
F ceramic capacitors are adequate. Applications with
larger load currents and fast transient signals may need up
to 1
F tantalum bypass capacitors.
INPUT BIAS CURRENT
The OPA2107
Difet input stages have very low input bias
current--an order of magnitude lower than BIFET op amps.
Circuit-board leakage paths can significantly degrade per-
formance. This is especially evident with the SO-8 surface-
mount package where pin-to-pin dimensions are particularly
small. Residual soldering flux, dirt, and oils, which conduct
leakage current, can be removed by proper cleaning. In most
instances, a two-step cleaning process is adequate using a
clean organic solvent rinse followed by deionized water.
Each rinse should be followed by a 30-minute bake at 85
C.
A circuit-board guard pattern effectively reduces errors due
to circuit-board leakage (Figure 1). By encircling critical high-
impedance nodes with a low-impedance connection at the
same circuit potential, any leakage currents will flow harm-
lessly to the low-impedance node. Guard traces should be
placed on all levels of a multiple-layer circuit board.
A
In
Non-Inverting
1
A
In
Buffer
1
Out
2
3
A
In
Inverting
1
Out
2
3
Out
2
3
FIGURE 1. Connection of Input Guard.
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA2107AP
ACTIVE
PDIP
P
8
50
OPA2107AU
ACTIVE
SOIC
D
8
100
OPA2107AU/2K5
ACTIVE
SOIC
D
8
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
MECHANICAL DATA
MPDI001A JANUARY 1995 REVISED JUNE 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
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amplifier.ti.com
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2003, Texas Instruments Incorporated
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