Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE/ORDERING INFORMATION
- PIN CONFIGURATION
- ELECTRICAL CHARACTERISTICS: V S =5V
- ELECTRICAL CHARACTERISTICS: V S =+5V
- TYPICAL CHARACTERISTICS: V S =5V
- TYPICAL CHARACTERISTICS: V S =+5V
- APPLICATIONS INFORMATION
- WIDEBAND BUFFER OPERATION
- VIDEO RGB AMPLIFIER
- HIGH-SPEED INSTRUMENTATION AMPLIFIER
- MULTIPLEXED CONVERTER DRIVER
- LOW-PASS FILTER
- DESIGN-IN TOOLS
- DEMONSTRATION BOARDS
- MACROMODELS AND APPLICATIONS SUPPORT
- OPERATING SUGGESTIONS
- GAIN SETTING
- OUTPUT CURRENT AND VOLTAGE
- DRIVING CAPACITIVE LOADS
- DISTORTION PERFORMANCE
- NOISE PERFORMANCE
- DC ACCURACY
- DISABLE OPERATION
- THERMAL ANALYSIS
- BOARD LAYOUT GUIDELINES
- PACKAGE DRAWINGS
- D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
- DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE
Triple, Wideband, Fixed Gain
Video BUFFER AMPLIFIER With Disable
FEATURES
q
FLEXIBLE SUPPLY RANGE:
+5V to +12V Single Supply
2.5V to
6V Dual Supplies
q
INTERNALLY FIXED GAIN: +2 or
1
q
HIGH BANDWIDTH (G = +2): 225MHz
q
LOW SUPPLY CURRENT: 5.1mA/ch
q
LOW DISABLED CURRENT: 150
A/ch
q
HIGH OUTPUT CURRENT: 190mA
q
OUTPUT VOLTAGE SWING:
4.0V
q
IMPROVED HIGH-FREQUENCY PINOUT
APPLICATIONS
q
RGB VIDEO LINE DRIVERS
q
MULTIPLE LINE VIDEO DAs
q
PORTABLE INSTRUMENTS
q
ADC BUFFERS
q
ACTIVE FILTERS
q
WIDEBAND DIFFERENTIAL RECEIVERS
q
IMPROVED UPGRADE TO OPA3682
DESCRIPTION
The OPA3692 provides an easy-to-use, broadband fixed
gain, triple buffer amplifier. Depending on the external
connections, the internal resistor network may be used to
provide either a fixed gain of +2 video buffer, or a gain of +1
or 1 voltage buffer. Operating on a very low 5.1mA/ch
supply current, the OPA3692 offers a slew rate and output
power normally associated with a much higher supply cur-
rent. A new output stage architecture delivers high output
current with minimal headroom and crossover distortion.
This gives exceptional single-supply operation. Using a
single +5V supply, the OPA3692 can deliver a 1V to 4V
output swing with over 120mA drive current and > 200MHz
bandwidth. This combination of features makes the OPA3692
an ideal RGB line driver or single-supply, triple Analog-to-
Digital Converter (ADC) input driver.
The low 5.1mA/ch supply current of the OPA3692 is precisely
trimmed at +25
C. This trim, along with low drift over tempera-
ture, ensures lower maximum supply current than competing
products that report only a room temperature nominal supply
current. System power can be further reduced by using the
optional disable control pin. Leaving this disable pin open, or
holding it HIGH, gives normal operation. If pulled LOW, the
OPA3692 supply current drops to less than 150
A/ch while
the output goes into a high-impedance state. This feature
may be used for power savings.
OPA3692
SBOS228C FEBRUARY 2002 REVISED JANUARY 2003
www.ti.com
Copyright 2002-2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OPA3692 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
Voltage-Feedback
OPA690
OPA2690
OPA3690
Current-Feedback
OPA691
OPA2691
OPA3691
Fixed Gain
OPA692
--
OPA3682
OPA3692
1/3
OPA3692
402
402
75.0
75.0
RG-59
V
R
1/3
OPA3692
402
402
75.0
75.0
RG-59
V
G
1/3
OPA3692
402
402
75.0
75
Cable
75
Cable
75
Cable
75.0
RG-59
V
B
RGB Line Driver
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OPA3692
SBOS228C
2
www.ti.com
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (V
O
< 0.5Vp-p)
G = +1
280
MHz
typ
C
G = +2
225
185
180
170
MHz
min
B
G = 1
220
MHz
typ
C
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
< 0.5Vp-p
120
40
35
30
MHz
min
B
Peaking at a Gain of +1
V
O
< 0.5Vp-p
0.2
1
1.5
2
dB
max
B
Large-Signal Bandwidth
G = +2, V
O
= 5Vp-p
220
MHz
typ
C
Slew Rate
G = +2, 4V Step
2000
1400
1375
1350
V/
s
min
B
Rise-and-Fall Time
G = +2, V
O
= 0.5V Step
1.6
ns
typ
C
G = +2, V
O
= 5V Step
1.9
ns
typ
C
ABSOLUTE MAXIMUM RATINGS
(1)
Power Supply ...............................................................................
6.5V
DC
Internal Power Dissipation
(2)
............................ See Thermal Information
Differential Input Voltage
(3)
...............................................................
1.2V
Input Voltage Range ............................................................................
V
S
Storage Temperature Range: D, DBQ ........................... 40
C to +125
C
Lead Temperature (soldering, 10s) .............................................. +300
C
Junction Temperature (T
J
) ........................................................... +175
C
ESD Resistance: HBM .................................................................... 2000V
CDM .................................................................... 1500V
MM ........................................................................ 200V
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) Packages must be derated based on specified
JA
.
Maximum T
J
must be observed. (3) Noninverting input to internal inverting node.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PIN CONFIGURATION
Top View
SSOP, SO
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
OPA3692
SO-16
D
40
C to +85
C
OPA3692
OPA3692ID
Rails, 48
"
"
"
"
"
OPA3692IDR
Tape and Reel, 2500
OPA3692
SSOP-16
DBQ
40
C to +85
C
OPA3692
OPA3692IDBQT
Tape and Reel, 250
"
"
"
"
"
OPA3692IDBQR
Tape and Reel, 2500
PACKAGE/ORDERING INFORMATION
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN A
+IN A
DIS B
IN B
+IN B
DIS C
IN C
+IN C
DIS A
+V
S
OUT A
V
S
OUT B
+V
S
OUT C
V
S
OPA3692
402
402
402
402
402
402
ELECTRICAL CHARACTERISTICS: V
S
=
5V
Boldface limits are tested at +25
C.
G = +2 (IN grounded) and R
L
= 100
(see Figure 1 for AC performance only), unless otherwise noted.
OPA3692ID, OPA3692IDBQ
TYP
MIN/MAX OVER TEMPERATURE
(1)
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
70
C
+85
C
UNITS
MAX
LEVEL
(2 )
OPA3692
SBOS228C
3
www.ti.com
AC PERFORMANCE (Cont.)
Settling Time to 0.02%
G = +2, V
O
= 2V Step
12
ns
typ
C
0.1%
G = +2, V
O
= 2V Step
8
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd-Harmonic
R
L
= 100
69
62
59
57
dBc
max
B
R
L
500
79
70
67
65
dBc
max
B
3rd-Harmonic
R
L
= 100
76
72
70
68
dBc
max
B
R
L
500
94
87
82
78
dBc
max
B
Input Voltage Noise
f > 1MHz
1.7
2.5
2.9
3.1
nV/
Hz
max
B
Noninverting Input Current Noise
f > 1MHz
12
14
15
15
pA/
Hz
max
B
Inverting Input Current Noise (Internal)
f > 1MHz
15
17
18
19
pA/
Hz
max
B
Differential Gain
NTSC, R
L
= 150
0.07
%
typ
C
NTSC, R
L
= 37.5
0.17
%
typ
C
Differential Phase
NTSC, R
L
= 150
0.02
deg
typ
C
NTSC, R
L
= 37.5
0.07
deg
typ
C
Channel-to-Channel Crosstalk
f = 5MHz, Input Referred, All Hostile
82
dBc
typ
C
DC PERFORMANCE
(3)
Gain Error
G = +1
0.2
%
typ
C
G = +2
0.3
1.5
1.6
1.7
%
max
A
G = 1
0.2
1.5
1.6
1.7
%
max
B
Internal R
F
and R
G
Maximum
402
457
462
464
max
A
Minimum
402
347
342
340
min
A
Average Drift
0.13
0.13
0.13
%/
C
max
B
Input Offset Voltage
V
CM
= 0V
0.8
3
3.7
4.3
mV
max
A
Average Offset Voltage Drift
V
CM
= 0V
12
20
V/
C
max
B
Noninverting Input Bias Current
V
CM
= 0V
+15
+35
+43
+45
A
max
A
Average Noninverting Input Bias Current Drift
V
CM
= 0V
300
300
nA/
C
max
B
Inverting Input Bias Current
V
CM
= 0V
5
25
30
40
A
max
A
Average Inverting Input Bias Current Drift
V
CM
= 0V
90
200
nA
C
max
B
INPUT
Common-Mode Input Range
3.5
3.4
3.3
3.2
V
min
B
Noninverting Input Impedance
100 || 2
k
|| pF
typ
C
OUTPUT
Voltage Output Swing
No Load
4.0
3.8
3.7
3.6
V
min
A
100
Load
3.9
3.7
3.6
3.3
V
min
A
Current Output, Sourcing
+190
+160
+140
+100
mA
min
A
Sinking
190
160
140
100
mA
min
A
Short-Circuit Current
250
mA
typ
C
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.12
typ
C
DISABLE/POWER DOWN (DIS Pin)
Power-Down Supply Current (+V
S
)
V
DIS
= 0, All Channels
450
900
1050
1200
A
max
A
Disable Time
V
IN
= +1V
DC
1
s
typ
C
Enable Time
V
IN
= +1V
DC
25
ns
typ
C
Off Isolation
G = +2, 5MHz
74
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn-On Glitch
G = +2, R
L
= 150
, V
IN
= 0V
50
mV
typ
C
Turn-Off Glitch
G = +2, R
L
= 150
, V
IN
= 0V
20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current
V
DIS
= 0, Each Channel
75
130
150
160
A
max
A
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage Range
6
6
6
V
max
A
Maximum Quiescent Current (3 Channels)
V
S
=
5V
15.3
15.9
16.8
17.4
mA
max
A
Minimum Quiescent Current (3 Channels)
V
S
=
5V
15.3
14.7
13.2
12.75
mA
min
A
Power-Supply Rejection Ratio (PSRR)
Input Referred
58
52
50
49
dB
min
A
TEMPERATURE RANGE
Specification: D, DBQ
40 to +85
C
typ
C
Thermal Resistance,
JA
D
SO-16
100
C/W
typ
C
DBQ
SSOP-16
100
C/W
typ
C
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25
C specifications. Junction temperature = ambient temperature +15
C at
high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25
C. Over-temperature limits by characterization and simulation. (B) Limits set by
characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. V
CM
is the input common-mode voltage.
ELECTRICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
Boldface limits are tested at +25
C.
G = +2 (IN grounded) and R
L
= 100
(see Figure 1 for AC performance only), unless otherwise noted.
OPA3692ID, OPA3692IDBQ
TYP
MIN/MAX OVER TEMPERATURE
(1)
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
70
C
+85
C
UNITS
MAX
LEVEL
(2 )
OPA3692
SBOS228C
4
www.ti.com
OPA3692ID, OPA3692IDBQ
TYP
MIN/MAX OVER TEMPERATURE
(1)
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
70
C
+85
C
UNITS
MAX
LEVEL
(2 )
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth (V
O
< 0.5Vp-p)
G = +1
240
MHz
typ
C
G = +2
190
168
160
140
MHz
min
B
G = 1
195
MHz
typ
C
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
< 0.5Vp-p
90
40
30
25
MHz
min
B
Peaking at a Gain of +1
V
O
< 0.5Vp-p
0.2
1
2.5
3
dB
max
B
Large-Signal Bandwidth
G = +2, V
O
= 2Vp-p
210
MHz
typ
C
Slew Rate
G = +2, 2V Step
830
600
575
550
V/
s
min
B
Rise-and-Fall Time
G = +2, V
O
= 0.5V Step
2.0
ns
typ
C
G = +2, V
O
= 2V Step
2.3
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
14
ns
typ
C
0.1%
G = +2, V
O
= 2V Step
10
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd-Harmonic
R
L
= 100
to V
S
/2
66
58
57
56
dBc
max
B
R
L
500
to V
S
/2
73
65
63
62
dBc
max
B
3rd-Harmonic
R
L
= 100
to V
S
/2
72
68
67
65
dBc
max
B
R
L
500
to V
S
/2
77
72
70
69
dBc
max
B
Input Voltage Noise
f > 1MHz
1.7
2.5
2.9
3.1
nV/
Hz
max
B
Noninverting Input Current Noise
f > 1MHz
12
14
15
15
pA/
Hz
max
B
Inverting Input Current Noise
f > 1MHz
15
17
18
19
pA/
Hz
max
B
DC PERFORMANCE
(3)
Gain Error
G = +1
0.2
%
typ
C
G = +2
0.3
1.5
1.6
1.7
%
max
A
G = 1
0.2
1.5
1.6
1.7
%
max
B
Internal R
F
and R
G
Minimum
402
457
462
464
min
B
Maximum
402
347
342
340
max
B
Average Drift
0.13
0.13
0.13
%/
C
max
B
Input Offset Voltage
V
CM
= 2.5V
0.8
3.5
4.1
4.8
mV
max
A
Average Offset Voltage Drift
V
CM
= 2.5V
12
20
V/
C
max
B
Noninverting Input Bias Current
V
CM
= 2.5V
+20
+40
+46
+56
A
max
A
Average Noninverting Input Bias Current Drift
V
CM
= 2.5V
250
250
nA/
C
max
B
Inverting Input Bias Current
V
CM
= 2.5V
5
20
25
35
A
max
A
Average Inverting Input Bias Current Drift
V
CM
= 2.5V
112
200
nA
C
max
B
INPUT
Least Positive Input Voltage
1.5
1.6
1.7
1.8
V
max
B
Most Positive Input Voltage
3.5
3.4
3.3
3.2
V
min
B
Noninverting Input Impedance
100 || 2
k
|| pF
typ
C
OUTPUT
Most Positive Output Voltage
No Load
4.0
3.8
3.7
3.5
V
min
A
R
L
= 100
3.9
3.7
3.6
3.4
V
min
A
Least Positive Output Voltage
No Load
1.0
1.2
1.3
1.5
V
max
A
R
L
= 100
1.1
1.3
1.4
1.6
V
max
A
Current Output, Sourcing
+160
+120
+100
+80
mA
min
A
Sinking
160
120
100
80
mA
min
A
Short-Circuit Current
250
mA
typ
C
Output Impedance
G = +2, f = 100kHz
0.12
typ
C
DISABLE/POWER DOWN (DIS Pin)
Power-Down Supply Current (+V
S
)
V
DIS
= 0, All Channels
450
900
1050
1200
A
max
A
Off Isolation
G = +2, 5MHz
65
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn-On Glitch
G = +2, R
L
= 150
, V
IN
= 2.5V
50
mV
typ
B
Turn-Off Glitch
G = +2, R
L
= 150
, V
IN
= 2.5V
20
mV
typ
B
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current (DIS)
V
DIS
= 0, Each Channel
75
130
150
160
A
typ
C
POWER SUPPLY
Specified Single-Supply Operating Voltage
5
V
typ
C
Maximum Single-Supply Operating Voltage
12
12
12
V
max
A
Maximum Quiescent Current (3 Channels)
V
S
= +5V
13.5
14.4
15.3
15.9
mA
max
A
Minimum Quiescent Current (3 Channels)
V
S
= +5V
13.5
12.3
11.4
11.0
mA
min
A
Power-Supply Rejection Ratio (+PSRR)
Input Referred
62
dB
typ
C
TEMPERATURE RANGE
Specification: D, DBQ
40 to +85
C
typ
C
Thermal Resistance,
JA
D
SO-16
100
C/W
typ
C
DBQ SSOP-16
100
C/W
typ
C
NOTES: (1) Junction temperature = ambient temperature for low temperature limit and +25
C specifications. Junction temperature = ambient temperature +15
C at
high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25
C. Over-temperature limits by characterization and simulation. (B) Limits set by
characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. V
CM
is the input common-mode voltage.
ELECTRICAL CHARACTERISTICS: V
S
= +5V
Boldface limits are tested at +25
C.
G = +2 (IN grounded though 0.1
F) and R
L
= 100
to V
S
/2 (see Figure 2 for AC performance only), unless otherwise noted.
OPA3692
SBOS228C
5
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
T
A
= +25
C, G = +2 (In grounded), and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
1
0
1
2
3
4
5
6
7
8
Frequency (50MHz/div)
0
500MHz
250MHz
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = +2
G = +1
G = 1
7
6
5
4
3
2
Frequency (25MHz/div)
0
250MHz
125MHz
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (1dB/div)
V
O
= 1Vp-p
V
O
= 2Vp-p
V
O
= 7Vp-p
V
O
= 4Vp-p
400
300
200
100
0
100
200
300
400
SMALL-SIGNAL PULSE RESPONSE
Output Voltage (100mV/div)
V
O
= 0.5Vp-p
G = +2
Time (5ns/div)
4
3
2
1
0
1
2
3
4
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (1V/div)
V
O
= 5Vp-p
G = +2
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
Number of 150
Loads
1
2
3
4
COMPOSITE VIDEO dG/dP
dP
dP
dG
dG
dG/dP (%/
)
1/3
OPA3692
Video In
Video Loads
5V
+5V
DIS
Optional
1.3k
Pull-Down
No Pull-Down
With 1.3k
Pull-Down
DISABLED FEEDTHROUGH vs FREQUENCY
50
55
60
65
70
75
80
85
90
95
Frequency (MHz)
1
0.5
10
100
Feedthrough (dB)
V
DIS
= 0
OPA3692
SBOS228C
6
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
T
A
= +25
C, G = +2 (In grounded), and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
60
65
70
75
80
85
90
95
100
Load Resistance (
)
100
1000
HARMONIC DISTORTION vs LOAD RESISTANCE
Harmonic Distortion (dBc)
V
O
= 2Vp-p
f = 5MHz
2nd-Harmonic
3rd-Harmonic
50
55
60
65
70
75
80
85
90
Supply Voltage (
V
S
)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
HARMONIC DISTORTION vs SUPPLY VOLTAGE
Harmonic Distortion (dBc)
V
O
= 2Vp-p
R
L
= 100
f = 5MHz
2nd-Harmonic
3rd-Harmonic
50
60
70
80
90
100
HARMONIC DISTORTION vs FREQUENCY (G = +2)
Frequency (MHz)
0.1
1
10
20
Harmonic Distortion (dBc)
dBc = dB Below Carrier
V
O
= 2Vp-p
R
L
= 100
3rd-Harmonic
2nd-Harmonic
65
70
75
80
85
Output Voltage Swing (Vp-p)
0.1
1
5
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Harmonic Distortion (dBc)
R
L
= 100
f = 5MHz
2nd-Harmonic
3rd-Harmonic
50
60
70
80
90
100
HARMONIC DISTORTION vs FREQUENCY (G = 1)
Frequency (MHz)
0.1
1
10
20
Harmonic Distortion (dBc)
dBc = dB Below Carrier
V
O
= 2Vp-p
R
L
= 100
3rd-Harmonic
2nd-Harmonic
HARMONIC DISTORTION vs FREQUENCY (G = +1)
Frequency (MHz)
0.1
1
10
20
Harmonic Distortion (dBc)
50
60
70
80
90
100
dBc = dB Below Carrier
V
O
= 2Vp-p
R
L
= 100
2nd-Harmonic
3rd-Harmonic
OPA3692
SBOS228C
7
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
T
A
= +25
C, G = +2 (In grounded), and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
100
10
1
INPUT VOLTAGE AND CURRENT NOISE DENSITY
Frequency (Hz)
100
1k
10k
100k
1M
10M
Current Noise (pA/
Hz)
Voltage Noise (nV/
Hz)
Noninverting Current Noise (12pA/
Hz)
Inverting Input Current Noise (15pA/
Hz)
Voltage Noise (1.7nV/
Hz)
30
40
50
60
70
80
90
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
Single-Tone Load Power (dBm)
8
6
4
2
0
2
4
6
8
10
3rd-Order Spurious Level (dBc)
dBc = dB below carriers
50MHz
20MHz
10MHz
Load Power at Matched 50
Load
60
50
40
30
20
10
0
Capacitive Load (pF)
1
10
100
1k
RECOMMENDED R
S
vs CAPACITIVE LOAD
R
S
(
)
9
6
3
0
3
6
9
Frequency (25MHz/div)
0
250MHz
125MHz
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
1/3
OPA3692
R
S
V
IN
V
O
C
L
1k
402
402
1k
is optional.
C
L
= 10pF
C
L
= 22pF
C
L
= 47pF
C
L
= 100pF
65
60
55
50
45
40
35
30
25
20
Frequency (Hz)
1k
10k
100k
1M
10M
100M
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
PSRR (dB)
+PSRR
PSRR
10
8
6
4
2
0
250
200
150
100
50
0
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (
C)
50
25
0
25
50
75
100
125
Supply Current (2mA/div)
Output Current (50mA/div)
Quiescent Supply Current
(1 Channel)
Sinking Output Current
Sourcing Output Current
OPA3692
SBOS228C
8
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
T
A
= +25
C, G = +2 (In grounded), and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
2
1.5
1
0.5
0
0.5
1
1.5
2
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (
C)
50
25
0
25
50
75
100
125
Input Offset Voltage (mV)
40
30
20
10
0
10
20
30
40
Input Bias Currents (
A)
Input Offset Voltage
Noninverting Input Bias Current
Inverting Input Bias Current
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
Output V
oltage (400mV/div)
Time (200ns/div)
2.0
1.6
1.2
0.8
0.4
0
V
DIS
(2V/div)
6.0
4.0
2.0
0
Output Voltage
V
DIS
V
IN
= +1V
10
1
0.1
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Frequency (Hz)
10k
100M
100k
1M
10M
Output Impedance (
)
1/3
OPA3692
402
+5V
5V
402
50
Z
O
DISABLE/ENABLE GLITCH
Output V
oltage (10mV/div)
Time (20ns/div)
30
20
10
0
10
20
V
DIS
(2V/div)
6.0
4.0
2.0
0
Output Voltage
V
IN
= 0V
V
DIS
ALL HOSTILE CROSSTALK
55
60
65
70
75
80
85
90
95
100
Frequency (MHz)
1
0.3
10
100
Crosstalk (dB)
2 Channels Driving
Input Referred
Crosstalk to
Inactive Channel
5
4
3
2
1
0
1
2
3
4
5
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
300 250 200 150 100 50
0
50
100 150 200 250 300
V
O
(V)
100
Load Line
50
Load Line
25
Load Line
Output Current Limited
1W Internal
Power Limit
Single Channel
1W Internal
Power Limit
Single Channel
Output Current Limit
OPA3692
SBOS228C
9
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= +5V
T
A
= +25
C, G = +2 (In grounded), and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
G = +2
V
O
= 0.5Vp-p
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
LARGE-SIGNAL PULSE RESPONSE
Output Voltage (400mV/div)
G = +2
V
O
= 2Vp-p
Time (5ns/div)
70
60
50
40
30
20
10
0
Capacitive Load (pF)
1
10
100
1k
RECOMMENDED R
S
vs CAPACITIVE LOAD
R
S
(
)
9
6
3
0
3
6
9
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (25MHz/div)
0
250MHz
125MHz
Normalized Gain to
Capacitive Load (dB)
C
L
= 10pF
C
L
= 22pF
C
L
= 47pF
C
L
= 100pF
1/3
OPA3692
402
402
57.6
806
806
50
Source
VIN
Dis
+5V
VS/2
100
VO
(1k
is optional)
0.1
F
6.8
F
+
0.1
F
0.1
F
1
0
1
2
3
4
5
6
7
8
Frequency (50MHz/div)
0
500MHz
250MHz
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = +1
G = +2
G = 1
7
6
5
4
3
2
1
0
Frequency (25MHz/div)
0
250MHz
125MHz
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (1dB/div)
R
L
= 100
to 2.5V
V
O
= 0.5Vp-p
V
O
= 1Vp-p
V
O
= 2Vp-p
OPA3692
SBOS228C
10
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= +5V
(Cont.)
T
A
= +25
C, G = +2 (In grounded), and R
L
= 100
, (see Figure 1 for AC performance only), unless otherwise noted.
60
65
70
75
80
Load Resistance (
)
100
1k
HARMONIC DISTORTION vs LOAD RESISTANCE
Harmonic Distortion (dBc)
2nd-Harmonic
3rd-Harmonic
V
O
= 2Vp-p
f = 5MHz
HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1
1
10
20
Harmonic Distortion (dBc)
50
60
70
80
90
V
O
= 2Vp-p
R
L
= 100
to 2.5V
2nd-Harmonic
3rd-Harmonic
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1
1
2
3
Harmonic Distortion (dBc)
60
65
70
75
80
R
L
= 100
to 2.5V
f = 5MHz
2nd-Harmonic
3rd-Harmonic
30
35
40
45
50
55
60
65
70
75
80
Single-Tone Load Power (dBm)
14
12
10
8
6
4
2
0
2
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
3rd-Order Spurious Level (dBc)
dBc = dB Below Carriers
Load Power at Matched 50
Load
50MHz
20MHz
10MHz
OPA3692
SBOS228C
11
www.ti.com
APPLICATIONS INFORMATION
WIDEBAND BUFFER OPERATION
The OPA3692 gives the exceptional AC performance of a
wideband, current-feedback op amp with a highly linear,
high-power output stage. It features internal R
F
and R
G
resistors that make it easy to select a gain of +2, +1, or
1 without external resistors. Requiring only 5.1mA/ch quies-
cent current, the OPA3692 swings to within 1V of either
supply rail and delivers in excess of 160mA at room tempera-
ture. This low output headroom requirement, along with
supply voltage independent biasing, gives remarkable +5V
single-supply operation. The OPA3692 will deliver greater
than 200MHz bandwidth driving a 2Vp-p output into 100
on
a +5V single supply. Previous boosted output stage amplifi-
ers have typically suffered from very poor crossover distor-
tion as the output current goes through zero. The OPA3692
achieves a comparable power gain with much better linearity.
Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit configuration used as the basis of the
5V
Electrical and Typical Characteristics. For test purposes, the
input impedance is set to 50
with a resistor to ground and
the output impedance is set to 50
with a series output
resistor. Voltage swings reported in the specifications are
taken directly at the input and output pins while load powers
(dBm) are defined at a matched 50
load. For the circuit of
Figure 1, the total effective load will be 100
|| 804
= 89
.
The disable control line (DIS) is typically left open to ensure
normal amplifier operation. In addition to the usual power-
supply decoupling capacitors to ground, a 0.1
F capacitor
can be included between the two power-supply pins. This
optional capacitor typically improves the 2nd-harmonic dis-
tortion performance by 3dB to 6dB.
Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration used as the basis of the +5V Electrical and
Typical Characteristics. Though not a rail-to-rail design, the
OPA3692 requires minimal input and output voltage headroom
compared to other very wideband, current-feedback op amps.
It will deliver a 3Vp-p output swing on a single +5V supply with
greater than 150MHz bandwidth. The key requirement of
broadband single-supply operation is to maintain input and
output signal swings within the usable voltage ranges at both
the input and the output. The circuit in Figure 2 establishes an
input midpoint bias using a simple resistive divider from the
+5V supply (two 806
resistors). The input signal is then AC-
coupled into this midpoint voltage bias. The input voltage can
swing to within 1.5V of either supply pin, giving a 2Vp-p input
signal range centered between the supply pins. The input
impedance matching resistor (57.6
) used for testing is ad-
justed to give a 50
input match when the parallel combination
of the biasing divider network is included. The gain resistor
(R
G
) is AC-coupled, giving the circuit a DC gain of +1, which
puts the input DC bias voltage (2.5V) on the output as well.
Again, on a single +5V supply, the output voltage can swing to
within 1V of either supply pin while delivering more than 120mA
output current. A demanding 100
load to a midpoint bias is
used in this characterization circuit. The new output stage used
in the OPA3692 can deliver large bipolar output currents into
this midpoint load with minimal crossover distortion, as shown
by the +5V supply, 3rd-harmonic distortion plots. Although
Figure 2 shows a single +5V operation, this same circuit is
suitable for applications up to a single +12V supply.
1/3
OPA3692
+5V
5V
50
Load
50
50
50
Source
R
G
402
R
F
402
+
6.8
F
0.1
F
+
6.8
F
0.1
F
DIS
V
IN
1/3
OPA3692
+5V
+V
S
DIS
V
S
/2
806
100
V
O
V
IN
806
R
G
402
R
F
402
0.1
F
0.1
F
+
6.8
F
0.1
F
50
Source
57.6
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifica-
tion and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification
and Test Circuit.
VIDEO RGB AMPLIFIER
The front page shows an RGB amplifier based on the
OPA3692. The package pinout supports a signal flow-through
PCB layout. The internal resistors simplify the PCB even more,
while maintaining good gain accuracy. For systems that need
to conserve power, the total supply current for the disabled
OPA3692 is only 450
A.
This triple op amp could also be used to drive triple video ADCs
to digitize component video.
OPA3692
SBOS228C
12
www.ti.com
HIGH-SPEED INSTRUMENTATION AMPLIFIER
Figure 3 shows an instrumentation amplifier based on the
OPA3692. The offset matching between inputs makes this an
attractive input stage for this application. The differential-to-
single-ended gain for this circuit is 2.0V/V. The inputs are high
impedance, with only 1pF to ground at each input. The loads
on the OPA3692 outputs are equal for the best harmonic
distortion possible.
1/3
OPA3692
1/3
OPA3692
1/3
OPA3692
402
402
402
402
402
200
200
402
V
2
V
OUT
V
1
1/3
OPA3692
402
402
100
V
1
1/3
OPA3692
402
402
100
V
2
1/3
OPA3692
402
402
100
V
3
Selection
Logic
ADS826
10-Bit
60MSPS
0.1
F
0.1
F
4.99k
0.1
F
4.99k
0.1
F
100pF
REFT
+3.5V
REFB
+1.5V
+In
In
CM
FIGURE 3. High-Speed Instrumentation Amplifier.
FIGURE 5. Multiplexed Converter Driver.
As shown in Figure 4, the OPA3692 used as an instrumenta-
tion amplifier has a 240MHz, 3dB bandwidth. This plot has
been made for a 1Vp-p output signal using a low-impedance
differential input source.
FIGURE 4. High-Speed Instrumentation Amplifier Response.
7
6
5
4
3
2
1
0
1
2
3
Frequency (MHz)
1
400
10
100
Gain (dB)
20log
V
OUT
|V
1
V
2
|
MULTIPLEXED CONVERTER DRIVER
The converter driver in Figure 5 multiplexes among the three
input signals. The OPA3692s enable and disable times
support multiplexing among video signals. The make-before-
break disable characteristic of the OPA3692 ensures that the
output is always under control. To avoid large switching
glitches, switch during the sync or retrace portions of the
video signal--the two inputs should be almost equal at these
times. The output is always under control, so the switching
glitches for two 0V inputs are < 20mV. With standard
video signals levels at the inputs, the maximum differential
voltage across the disabled inputs will not exceed the
1.2V
maximum rating.
The output resistors isolate the outputs from each other
when switching between channels. The feedback network of
the disabled channels forms part of the load seen by the
enabled amplifier, attenuating the signal slightly.
OPA3692
SBOS228C
13
www.ti.com
LOW-PASS FILTER
The circuit in Figure 6 realizes a 7th-order Butterworth low-
pass filter with a 3dB bandwidth of 20MHz. This filter is based
on the KRC active filter topology, which uses an amplifier with
the fixed gain
1. The OPA3692 makes a good amplifier for
this type of filter. The component values have been adjusted
to compensate for the parasitic effects of the op amp.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA3692 in its two package
style. All of these are available free as an unpopulated PC
board delivered with descriptive documentation. The sum-
mary information for these boards are shown in Table I.
To request any of these boards, check the Texas Instruments
web site at www.ti.com.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and RF
amplifier circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A SPICE
model for the OPA692 is available through the Texas Instru-
ments web site at www.ti.com. Use three of these models to
simulate the OPA3692. These models do a good job of
predicting small-signal AC and transient performance under
a wide variety of operating conditions. They do not do as well
in predicting the harmonic distortion or dG/dP characteristics.
These models do not attempt to distinguish between the
package types in their small-signal AC performance.
FIGURE 6. 7th-Order Butterworth Filter.
BOARD
LITERATURE
PART
REQUEST
PRODUCT
PACKAGE
NUMBER
NUMBER
OPA3692IDBQ
SSOP-16
DEM-OPA368xE
SBOU006
OPA3692ID
SO-16
DEM-OPA368xU
SBOU007
TABLE I. OPA3692 Demonstration Boards.
1/3
OPA3692
402
402
120pF
82pF
220pF
22pF
68pF
47.5
124
1/3
OPA3692
402
56pF
110
255
402
1/3
OPA3692
402
402
180pF
48.7
95.3
49.9
(open)
(open)
V
OUT
V
IN
20
0
20
40
60
80
100
Frequency (MHz)
1
1000
3
10
30
100
300
7TH-ORDER BUTTERWORTH
FILTER RESPONSE
Gain (dB)
OPA3692
SBOS228C
14
www.ti.com
OPERATING SUGGESTIONS
GAIN SETTING
Setting the gain with the OPA3692 is very easy. For a gain of
+2, ground the IN pin and drive the +IN pin with the signal.
For a gain of +1, leave the IN pin open and drive the +IN pin
with the signal. For a gain of 1, ground the +IN pin and drive
the IN pin with the signal. As the internal resistor values (not
their ratios) change significantly over temperature and pro-
cess, external resistors should not be used to modify the
gain.
OUTPUT CURRENT AND VOLTAGE
The OPA3692 provides output voltage and current capabili-
ties that are unsurpassed in a low-cost monolithic op amp.
Under no-load conditions at 25
C, the output voltage typically
swings closer than 1V to either supply rail; the tested swing
limit is within 1.2V of either rail. Into a 15
load (the minimum
tested load), it is tested to deliver more than
160mA.
The specifications described previously, though familiar in
the industry, consider voltage and current limits separately. In
many applications, it is the voltage current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA3692 output drive capabilities, noting
that the graph is bounded by a safe operating area of 1W
maximum internal power dissipation. Superimposing resistor
load lines onto the plot shows that the OPA3692 can drive
2.5V into 25
or
3.5V into 50
without exceeding the
output capabilities or the 1W dissipation limit. A 100
load
line (the standard test circuit load) shows the full
3.9V
output swing capability, as shown in the Electrical Character-
istics.
The minimum specified output voltage and current over-
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold start-up does the output
current and voltage decrease to the numbers shown in the
Electrical Characteristic tables. As the output transistors
deliver power, their junction temperatures increase, decreas-
ing their V
BE
s (increasing the available output voltage swing)
and increasing their current gains (increasing the available
output current). In steady-state operation, the available out-
put voltage and current is always greater than that shown in
the over-temperature specifications because the output stage
junction temperatures are higher than the minimum specified
operating ambient.
To protect the output stage from accidental shorts to ground
and the power supplies, output short-circuit protection is
included in the OPA3692. This circuit acts to limit the maxi-
mum source or sink current to approximately 250mA.
DRIVING CAPACITIVE LOADS
One of the most demanding, but yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC--including additional
external capacitance that may be recommended to improve
ADC linearity. A high-speed amplifier like the OPA3692 can be
very susceptible to decreased stability and closed-loop re-
sponse peaking when a capacitive load is placed directly on
the output pin. When the amplifier open-loop output resistance
is considered, this capacitive load introduces an additional
pole in the signal path that can decrease the phase margin.
Several external solutions to this problem have been sug-
gested. When the primary considerations are frequency re-
sponse flatness, pulse response fidelity, and/or distortion, the
simplest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive load.
This does not eliminate the pole from the loop response, but
rather shifts it and adds a zero at a higher frequency. The
additional zero acts to cancel the phase lag from the capaci-
tive load pole, thus increasing the phase margin and improv-
ing stability.
The Typical Characteristics show the recommended R
S
ver-
sus capacitive load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can begin
to degrade the performance of the OPA3692. Long PC board
traces, unmatched cables, and connections to multiple de-
vices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA3692 output pin
(see the Board Layout Guidelines section).
DISTORTION PERFORMANCE
The OPA3692 provides good distortion performance into a
100
load on
5V supplies. Relative to alternative solutions, it
provides exceptional performance into lighter loads and/or
operating on a single +5V supply. Generally, until the funda-
mental signal reaches very high frequency or power levels, the
2nd-harmonic dominates the distortion with a negligible 3rd-
harmonic component. Focusing then on the 2nd-harmonic,
increasing the load impedance improves distortion directly.
Remember that the total load includes the feedback network in
the noninverting configuration (see Figure 1); this is the sum
R
F
+ R
G
, whereas in the inverting configuration, it is just R
F
.
Also, providing an additional supply decoupling capacitor (0.1
F)
between the supply pins (for bipolar operation) improves the
2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing increases
harmonic distortion directly. The Typical Characteristics show the
2nd-harmonic increasing at a little less than the expected 2X rate
while the 3rd-harmonic increases at a little less than the expected
3X rate. Where the test power doubles, the 2nd-harmonic
increases only by less than the expected 6dB, whereas the 3rd-
OPA3692
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harmonic increases by less than the expected 12dB. This also
shows up in the 2-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are extremely
low at low output power levels. The output stage continues to
hold them low even as the fundamental power reaches very high
levels. As the Typical Characteristics show, the spurious
intermodulation powers do not increase as predicted by a
traditional intercept model. As the fundamental power level
increases, the dynamic range does not decrease significantly.
For two tones centered at 20MHz, with 10dBm/tone into a
matched 50
load (i.e., 2Vp-p for each tone at the load, which
requires 8Vp-p for the overall 2-tone envelope at the output pin),
the Typical Characteristics show a 58dBc difference between the
test-tone power and the 3rd-order intermodulation spurious
levels. This exceptional performance improves further when
operating at lower frequencies.
NOISE PERFORMANCE
The OPA3692 offers an excellent balance between voltage
and current noise terms to achieve low output noise. The
inverting current noise (15pA/
Hz) is significantly lower than
earlier solutions while the input voltage noise (1.7nV/
Hz) is
lower than most unity-gain stable, wideband, voltage-feedback
op amps. This low input voltage noise was achieved at the
price of higher noninverting input current noise (12pA/
Hz). As
long as the AC source impedance looking out of the
noninverting node is less than 100
, this current noise will not
contribute significantly to the total output noise. The op amp
input voltage noise and the two input current noise terms
combine to give low output noise under a wide variety of
operating conditions. Figure 7 shows the op amp noise analy-
sis model with all the noise terms included. In this model, all
noise terms are taken to be noise voltage or current density
terms in either nV/
Hz or pA/
Hz.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the output
noise voltage using the terms shown in Figure 7.
(1)
E
E
I
R
kTR
NG
I R
kTR NG
O
NI
BN S
S
BI F
F
=
+
(
)
+
+
(
)
+
2
2
2
2
4
4
Dividing this expression by the noise gain (NG = (1+R
F
/R
G
))
gives the equivalent input-referred spot noise voltage at the
noninverting input as shown in Equation 2.
(2)
E
E
I
R
kTR
I R
NG
kTR
NG
N
NI
BN S
S
BI F
F
=
+
(
)
+
+
+
2
2
2
4
4
Evaluating these two equations for the OPA3692 circuit and
component values shown in Figure 1 gives a total output spot
noise voltage of 8nV/
Hz and a total equivalent input spot
noise voltage of 4nV/
Hz. This total input-referred spot noise
voltage is higher than the 1.7nV/
Hz specification for the op
amp voltage noise alone. This reflects the noise added to the
output by the inverting current noise times the feedback
resistor. This inverting node current noise is modeled as
internal to the OPA3692 with R
F
set internally as well.
DC ACCURACY
The OPA3692 provides exceptional bandwidth in high gains,
giving fast pulse settling but only moderate DC accuracy. The
Electrical Characteristics show an input offset voltage com-
parable to high-speed voltage-feedback amplifiers. However,
the two input bias currents are somewhat higher and are
unmatched. Bias current cancellation techniques do not
reduce the output DC offset for OPA3692. As the two input
bias currents are unrelated in both magnitude and polarity,
matching the source impedance looking out of each input to
reduce their error contribution to the output is ineffective.
Evaluating the configuration of Figure 1, using worst-case
+25
C input offset voltage and the two input bias currents,
gives a worst-case output offset range equal to:
(NG V
OS(MAX)
) + (I
BN
R
S
/2 NG)
(I
BI
R
F
)
where NG = noninverting signal gain
=
(2 3mV) + (35
A 25
2)
(402
25
A)
=
6mV + 1.75mV
10.05mV
= 14.3mV
+17.8mV
Minimizing the resistance seen by the noninverting input will
give the best DC offset performance.
4kT
R
G
R
G
R
F
R
S
OPA3692
I
BI
E
O
I
BN
4kT = 1.6E 20J
at 290
K
E
RS
E
NI
4kTR
S
4kTR
F
FIGURE 7. Noise Model.
OPA3692
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DISABLE OPERATION
The OPA3692 provides an optional disable feature that can
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control pin
is left unconnected, the OPA3692 operates normally. To
disable, the control pin must be asserted LOW. Figure 8
shows a simplified internal circuit for the disable control
feature.
In normal operation, base current to Q1 is provided through the
110k
resistor while the emitter current through the 15k
resistor sets up a voltage drop that is inadequate to turn on the
two diodes in the Q1 emitter. As V
DIS
is pulled LOW, additional
current is pulled through the 15k
resistor, eventually turning
on these two diodes (
75
A). At this point, any additional
current pulled out of V
DIS
goes through those diodes holding
the emitter-base voltage of Q1 at approximately 0V. This shuts
off the collector current out of Q1, turning the amplifier off. The
supply current in the disable mode is only what is required to
operate the circuit of Figure 8. Additional circuitry ensures that
turn-on time occurs faster than turn-off time (make-before-
break).
When disabled, the output and input nodes go to a high-
impedance state. If the OPA3692 is operating in a gain of +1,
this shows a very high impedance (2pF || 1M
) at the output
and exceptional signal isolation. If operating at a gain of +2, the
total feedback network resistance (R
F
+ R
G
) will appear as the
impedance looking back into the output, but the circuit will still
show very high forward and reverse isolation. If configured as
an inverting amplifier, the input and output will be connected
through the feedback network resistance (R
F
+ R
G
) giving
relatively poor input to output isolation.
25k
110k
15k
I
S
Control
V
S
+V
S
V
DIS
Q1
FIGURE 8. Simplified Disable Control Circuit.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Typical
Characteristics show these glitches for the circuit of Figure 1
with the input signal set to 0V. The glitch waveform at the
output pin is plotted along with the DIS pin voltage.
The transition edge rate (dV/dt) of the DIS control line
influences this glitch. For the curve, "Disable/Enable Glitch",
shown in the Typical Characteristics, the edge rate was
reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate can
be achieved by adding a simple RC filter into the V
DIS
pin
from a higher speed logic line. If extremely fast transition
logic is used, a 2k
series resistor between the logic gate
and the DIS input pin provides adequate bandlimiting using
just the parasitic input capacitance on the DIS pin while still
ensuring an adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA3692,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described following. In no case should the maximum junction
temperature be allowed to exceed 175
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
JA
.
The total internal power dissipation (P
D
) is the sum of quies-
cent power (P
DQ
) and additional power dissipated in the output
stage (P
DL
) to deliver load power. Quiescent power is simply
the specified no-load supply current times the total supply
voltage across the part. P
DL
depends on the required output
signal and load but, for a grounded resistive load, be at a
maximum when the output is fixed at a voltage equal to
1/2 of either supply voltage (for equal bipolar supplies). Under
this condition P
DL
= V
S
2
/(4 R
L
), where R
L
includes feedback
network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA3692 in the circuit of Figure 1 operating at the maximum
specified ambient temperature of +85
C with all three outputs
driving a grounded 100
load to +2.5V:
P
D
= 10V 17.4mA + 3 (5
2
/(4 (100
|| 804
)) = 384mW
Maximum T
J
= +85
C + (0.384W 100
C/W) = 123.4
C
This worst-case condition is within the maximum junction
temperature. Normally, this extreme case is not encountered.
Careful attention to internal power dissipation is required.
OPA3692
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BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency ampli-
fier like the OPA3692 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output pin can cause instability: on the noninverting input, it
can react with the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of the
ground and power planes around those pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high frequency 0.1
F decoupling capacitors. At
the device pins, the ground and power plane layout should
not be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 9, 11, 13, and 15) should always be
decoupled with these capacitors. An optional supply
decoupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd-harmonic distortion per-
formance. Larger (2.2
F to 6.8
F) decoupling capacitors,
effective at lower frequency, should also be used on the main
supply pins. These may be placed somewhat farther from the
device and may be shared among several devices in the
same area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA3692. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition, axially-
leaded resistors can also provide good high-frequency per-
formance. Again, keep their leads and PC board trace length
as short as possible. Never use wirewound type resistors in
a high-frequency application. Other network components,
such as noninverting input termination resistors, should also
be placed close to the package.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-
board transmission lines. For short connections, consider
the trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set R
S
from the plot of recommended R
S
versus Capaci-
tive Load. Low parasitic capacitive loads (< 5pF) may not
need an R
S
because the OPA3692 is nominally compen-
sated to operate with a 2pF parasitic load. If a long trace is
required, and the 6dB signal loss intrinsic to a doubly-
terminated transmission line is acceptable, implement a
matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50
environ-
ment is normally not necessary on board, and in fact, a
higher impedance environment will improve distortion as
shown in the Distortion versus Load plots. With a character-
istic board trace impedance defined based on board material
and trace dimensions, a matching series resistor into the
trace from the output of the OPA3692 is used as well as a
terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and the input
impedance of the destination device; this total effective
impedance should be set to match the trace impedance. The
high output voltage and current capability of the OPA3692
allows multiple destination devices to be handled as sepa-
rate transmission lines, each with their own series and shunt
terminations. If the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be series-
terminated at the source end only. Treat the trace as a
capacitive load in this case and set the series resistor value
as shown in the plot of R
S
versus Capacitive Load. This will
not preserve signal integrity as well as a doubly-terminated
line. If the input impedance of the destination device is low,
there will be some signal attenuation due to the voltage
divider formed by the series output into the terminating
impedance.
e) Socketing a high-speed part like the OPA3692 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA3692
onto the board.
INPUT AND ESD PROTECTION
The OPA3692 is built using a very high-speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry de-
vices. These breakdowns are reflected in the Absolute Maxi-
mum Ratings table. All device pins have limited ESD protec-
tion using internal diodes to the power supplies as shown in
Figure 9.
External
Pin
+V
CC
V
CC
Internal
Circuitry
FIGURE 9. Internal ESD Protection.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with
15V supply
parts driving into the OPA3692), current-limiting series resis-
tors should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
OPA3692
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18
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PACKAGE DRAWINGS
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
OPA3692
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19
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PACKAGE DRAWINGS
(Cont.)
DBQ (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
Gage Plane
0.008 (0,20) NOM
0.010 (0,25)
0.016 (0,40)
0.035 (0,89)
24
20
Seating Plane
(8,74)
(8,56)
0.337
0.337
(8,56)
(8,74)
0.344
0.344
4073301/E 10/00
13
0.150 (3,81)
0.157 (3,99)
0.012 (0,30)
0.008 (0,20)
12
A
24 PINS SHOWN
1
24
16
DIM
PINS **
A MIN
A MAX
0.004 (0,10)
0.010 (0,25)
0.069 (1,75) MAX
0.244 (6,20)
0.228 (5,80)
0.197
(5,00)
(4,78)
0.188
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,64)
0
8
28
(10,01)
(9,80)
0.386
0.394
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-137
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA3692ID
ACTIVE
SOIC
D
16
48
OPA3692IDBQR
ACTIVE
SSOP
DBQ
16
2500
OPA3692IDBQT
ACTIVE
SSOP
DBQ
16
250
OPA3692IDR
ACTIVE
SOIC
D
16
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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