Wideband, Single-Supply

OPERATIONAL AMPLIFIERS

OPA634
OPA635

FEATURES

HIGH BANDWIDTH: 150MHz (G = +2)

+3V TO +10V SUPPLY OPERATION

ZERO POWER DISABLE (OPA635)

INPUT RANGE INCLUDES GROUND

4.8V OUTPUT SWING ON +5V SUPPLY

HIGH OUTPUT CURRENT: 80mA

HIGH SLEW RATE: 250V/

LOW INPUT VOLTAGE NOISE: 5.6nV/

AVAILABLE IN SOT23 PACKAGE

DESCRIPTION

The OPA634 and OPA635 are low-power, voltage-
feedback, high-speed amplifiers designed to operate on
+3V or +5V single-supply voltages. Operation on

or +10V supplies is also supported. The input range
extends below ground and to within 1.2V of the positive
supply. Using complementary common-emitter outputs
provides an output swing to within 30mV of ground and
140mV of positive supply. The high output drive cur-
rent, low differential gain and phase errors make them
ideal for single-supply composite video line driving.

Low-distortion operation is ensured by the high gain
bandwidth product (140MHz) and slew rate (250V/

s).

This makes the OPA634 and OPA635 ideal input buffer
stages to 3V and 5V CMOS converters. Unlike other
low-power, single-supply operational amplifiers, distor-
tion performance improves as the signal swing is de-
creased.

A low 5.6nV input voltage noise supports wide dynamic
range operation. Multiplexing or system power reduc-
tion can be achieved using the high-speed disable line
with the OPA635. Power dissipation can be reduced to
zero by taking the disable line HIGH.

The OPA634 and OPA635 are available in an industry
standard SO-8 package. The OPA634 is also available in
an ultra-small SOT23-5 package, while the OPA635 is
available in the SOT23-6. Where lower supply current
and speed are required, consider the OPA631 and OPA632.

APPLICATIONS

SINGLE-SUPPLY ADC INPUT BUFFERS

SINGLE SUPPLY VIDEO LINE DRIVERS

WIRELESS LAN IF AMPLIFIERS

CCD IMAGING CHANNELS

LOW-POWER ULTRASOUND

OPA6

DESCRIPTION

SINGLES

DUALS

Medium Speed, No Disable

OPA631

OPA2631

With Disable

OPA632

High Speed, No Disable

OPA634

OPA2634

With Disable

OPA635

RELATED PRODUCTS

SBOS097A

Printed in U.S.A. February, 2001

www.ti.com

OPA635

750

562

2.26k

374

22pF

+3V

100

Pwrdn

DIS

Disable

+3V

ADS900

10-Bit

20Msps

OPA634, OPA635

SBOS097A

OPA634U, N
OPA635U, N

TYP

GUARANTEED

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

+85

UNITS

MAX

LEVEL

(1)

SPECIFICATIONS: V

= +5V

At T

= 25

C, G = +2, R

= 750

, and R

= 150

to V

/2, unless otherwise noted (see Figure 1).

AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth

G = +2, V

0.5Vp-p

150

100

MHz

min

G = +5, V

0.5Vp-p

MHz

min

G = +10, V

0.5Vp-p

MHz

min

Gain Bandwidth Product

+10

140

100

MHz

min

Peaking at a Gain of +1

0.5Vp-p

typ

Slew Rate

G = +2, 2V Step

250

170

125

115

min

Rise Time

0.5V Step

2.4

3.4

4.7

5.2

max

Fall Time

0.5V Step

2.4

3.5

4.5

4.8

max

Settling Time to 0.1%

G = +2, 1V Step

max

Spurious Free Dynamic Range

= 2Vp-p, f = 5MHz

dBc

min

Input Voltage Noise

f > 1MHz

5.6

6.2

7.3

7.7

nV/

max

Input Current Noise

f > 1MHz

2.8

3.8

4.2

pA/

max

NTSC Differential Gain

0.10

typ

NTSC Differential Phase

0.16

degrees

typ

DC PERFORMANCE
Open-Loop Voltage Gain

min

Input Offset Voltage

max

Average Offset Voltage Drift

4.6

max

Input Bias Current

= 2.0V

max

Input Offset Current

= 2.0V

0.6

2.25

2.6

4.5

max

Input Offset Current Drift

nA/

max

INPUT
Least Positive Input Voltage

0.24

0.1

0.05

0.01

max

Most Positive Input Voltage

3.8

3.5

3.45

3.4

min

Common-Mode Rejection (CMRR)

Input Referred

min

Input Impedance

Differential-Mode

10 || 2.1

|| pF

typ

Common-Mode

400 || 1.2

|| pF

typ

OUTPUT
Least Positive Output Voltage

= 1k

to 2.5V

0.03

0.07

0.08

0.09

max

= 150

to 2.5V

0.1

0.14

0.15

0.22

max

Most Positive Output Voltage

= 1k

to 2.5V

4.86

4.8

4.75

4.7

min

= 150

to 2.5V

4.65

4.55

4.5

4.4

min

Current Output, Sourcing

min

Current Output, Sinking

100

min

Short-Circuit Current (output shorted to either supply)

100

typ

Closed-Loop Output Impedance

G = +2, f

100kHz

0.2

typ

DISABLE (OPA635 only)
On Voltage (device enabled Low)

1.0

1.0

1.0

max

Off Voltage (device disabled High)

4.0

4.1

4.2

4.3

min

On Disable Current (DIS pin)

110

120

max

Off Disable Current (DIS pin)

typ

Disabled Quiescent Current

max

Disable Time

100

typ

Enable Time

typ

Off Isolation

f = 5MHz, Input to Output

typ

POWER SUPPLY
Minimum Operating Voltage

2.7

min

Maximum Operating Voltage

10.5

10.5

max

Maximum Quiescent Current

12.7

13.2

13.5

max

Minimum Quiescent Current

11.3

9.75

8.5

min

Power Supply Rejection Ratio (PSRR)

Input Referred

min

THERMAL CHARACTERISTICS
Specification: U, N

40 to +85

typ

Thermal Resistance

SO-8

125

C/W

typ

SOT23-5, SOT23-6

150

C/W

typ

NOTE: (1) Test Levels: (A) 100% tested at 25

C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.

OPA634, OPA635

SBOS097A

OPA634U, N
OPA635U, N

TYP

GUARANTEED

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

+85

UNITS

MAX LEVEL

(1)

SPECIFICATIONS: V

= +3V

At T

= 25

C, G = +2 and R

= 150

to V

/2, unless otherwise noted (see Figure 2).

AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth

G = +2, V

0.5Vp-p

110

MHz

min

G = +5, V

0.5Vp-p

MHz

min

G = +10, V

0.5Vp-p

MHz

min

Gain Bandwidth Product

+10

150

100

MHz

min

Peaking at a Gain of +1

0.5Vp-p

typ

Slew Rate

1V Step

215

160

123

min

Rise Time

0.5V Step

2.8

4.3

4.5

6.3

max

Fall Time

0.5V Step

3.0

4.4

4.6

6.0

max

Settling Time to 0.1%

1V Step

max

Spurious Free Dynamic Range

= 1Vp-p, f = 5MHz

dBc

min

Input Voltage Noise

f > 1MHz

5.6

6.2

7.3

7.7

nV/

max

Input Current Noise

f > 1MHz

2.8

3.7

4.2

4.4

pA/

max

DC PERFORMANCE
Open-Loop Voltage Gain

min

Input Offset Voltage

1.5

max

Average Offset Voltage Drift

max

Input Bias Current

= 1.0V

max

Input Offset Current

= 1.0V

0.6

2.3

max

Input Offset Current Drift

nA/

max

INPUT
Least Positive Input Voltage

0.25

0.1

0.05

0.01

max

Most Positive Input Voltage

1.8

1.6

1.55

1.5

min

Common-Mode Rejection (CMRR)

Input Referred

min

Input Impedance

Differential-Mode

10 || 2.1

|| p

typ

Common-Mode

400 || 1.2

|| p

typ

OUTPUT
Least Positive Output Voltage

= 1k

to 1.5V

0.035

0.043

0.045

0.06

max

= 150

to 1.5V

0.06

0.16

0.19

0.43

max

Most Positive Output Voltage

= 1k

to 1.5V

2.9

2.86

2.85

2.45

min

= 150

to 1.5V

2.8

2.70

2.69

2.65

min

Current Output, Sourcing

min

Current Output, Sinking

min

Short Circuit Current (output shorted to either supply)

100

typ

Closed-Loop Output Impedance

Figure 2, f < 100kHz

0.2

typ

DISABLE (OPA635 only)
On Voltage (device enabled Low)

1.0

0.5

0.5

max

Off Voltage (device disabled High)

1.8

1.9

2.1

2.2

min

On Disable Current (DIS pin)

100

110

max

Off Disable Current (DIS pin)

typ

Disabled Quiescent Current

max

Disable Time

100

typ

Enable Time

typ

Off Isolation

f = 5MHz, Input to Output

typ

POWER SUPPLY
Minimum Operating Voltage

2.7

min

Maximum Operating Voltage

10.5

10.5

max

Maximum Quiescent Current

10.8

11.5

11.8

max

Minimum Quiescent Current

10.8

10.1

8.6

8.0

min

Power Supply Rejection Ratio (PSRR)

Input Referred

min

THERMAL CHARACTERISTICS
Specification: U, N

40 to +85

typ

Thermal Resistance

SO-8

125

C/W

typ

SOT23-5, SOT23-6

150

C/W

typ

NOTE: (1) Test Levels: (A) 100% tested at 25

C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.

OPA634, OPA635

SBOS097A

Inverting Input

Non-Inverting Input

GND

DIS (OPA635 only)

Output

PIN CONFIGURATIONS

ABSOLUTE MAXIMUM RATINGS

Power Supply ................................................................................ +11V

Internal Power Dissipation .................................... See Thermal Analysis
Differential Input Voltage ..................................................................

1.2V

Input Voltage Range ............................................................... 0.5 to +V

Storage Temperature Range: P, U, N ........................... 40

C to +125

Lead Temperature (soldering, 10s) .............................................. +300

Junction Temperature (T

) ........................................................... +175

ELECTROSTATIC
DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from perfor-
mance degradation to complete device failure. Burr-Brown Corpo-
ration recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.

Output

GND

Non-Inverting Input

DIS

Inverting Input

A35

Pin Orientation/Package Marking

PACKAGE

SPECIFIED

DRAWING

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE

NUMBER

RANGE

MARKING

NUMBER

(1)

MEDIA

OPA634U

SO-8 Surface-Mount

182

C to +85

OPA634U

Rails

OPA634U/2K5

Tape and Reel

OPA634N

SOT23-5

331

C to +85

B34

OPA634N/250

Tape and Reel

OPA634N/3K

Tape and Reel

OPA635U

SO-8 Surface-Mount

182

C to +85

OPA635U

Rails

OPA635U/2K5

Tape and Reel

OPA635N

SOT23-6

332

C to +85

A35

OPA635N/250

Tape and Reel

OPA635N/3K

Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 3000 pieces
of "OPA635N/3K" will get a single 3000-piece Tape and Reel.

PACKAGE/ORDERING INFORMATION

Output

GND

Non-Inverting Input

Inverting Input

B34

Pin Orientation/Package Marking

Top View--OPA634, OPA635

Top View--OPA634

SOT23-5

Top View--OPA635

SOT23-6

OPA634, OPA635

SBOS097A

TYPICAL PERFORMANCE CURVES: V

= +5V

(Cont.)

At T

= 25

C, G = +2, R

= 750

, and R

= 150

to V

/2, unless otherwise noted (see Figure 1).

5MHz 2nd-HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage (Vp-p)

0.1

2nd-Harmonic Distortion (dBc)

= 150

= 250

= 500

5MHz 3rd-HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage (Vp-p)

0.1

3rd-Harmonic Distortion (dBc)

= 500

= 250

= 150

10MHz 2nd-HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage (Vp-p)

0.1

2nd-Harmonic Distortion (dBc)

= 150

= 250

= 500

10MHz 3rd-HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage (Vp-p)

0.1

3rd-Harmonic Distortion (dBc)

= 250

= 150

= 500

20MHz 2nd-HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage (Vp-p)

0.1

2nd-Harmonic Distortion (dBc)

= 500

= 150

= 250

20MHz 3rd-HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage (Vp-p)

0.1

3rd-Harmonic Distortion (dBc)

= 500

= 150

= 250

OPA634, OPA635

SBOS097A

TYPICAL PERFORMANCE CURVES: V

= +5V

(Cont.)

At T

= 25

C, G = +2, R

= 750

, and R

= 150

to V

/2, unless otherwise noted (see Figure 1).

2nd-HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

2nd-Harmonic Distortion (dBc)

= 2Vp-p

= 100

G = +2

G = +10

G = +5

3rd-HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

3rd-Harmonic Distortion (dBc)

= 2Vp-p

= 100

G = +5

G = +2

G = +10

HARMONIC DISTORTION vs LOAD RESISTANCE

(

)

100

200

300

400

500

Harmonic Distortion (dBc)

= 2Vp-p

= 5MHz

3rd-Harmonic

Distortion

2nd-Harmonic

Distortion

TWO-TONE, 3rd-ORDER

INTERMODULATION SPURIOUS

Single-Tone Load Power (dBm)

3rd-Order Spurious Level (dBc)

= 5MHz

= 10MHz

= 20MHz

Load Power at

Matched 50

Load

CMRR AND PSRR vs FREQUENCY

Frequency (Hz)

100

10k

100k

10M

Rejection Ratio, Input Referred (dB)

PSRR

CMRR

100

INPUT NOISE DENSITY vs FREQUENCY

Frequency (Hz)

100

10k

100k

10M

Voltage Noise (nV/

Hz)

Current Noise (pA/

Hz)

Voltage Noise, e

= 5.6nV/

Current Noise, i

= 2.8pA/

OPA634, OPA635

SBOS097A

TYPICAL PERFORMANCE CURVES: V

= +5V

(Cont.)

At T

= 25

C, G = +2, R

= 750

, and R

= 150

to V

/2, unless otherwise noted (see Figure 1).

1000

100

vs CAPACITIVE LOAD

Capacitive Load (pF)

100

1000

(

)

FREQUENCY RESPONSE vs CAPACITIVE LOAD

Frequency (MHz)

100

300

Normalized Gain (dB)

= 0.2Vp-p

OPA63x

= 100pF

= 1000pF

= 10pF

100

OPEN-LOOP GAIN AND PHASE

Frequency (Hz)

10k

100k

10M

100M

Open-Loop Gain (dB)

120

150

180

210

240

270

300

330

360

Open-Loop Phase (

)

Open-Loop Phase

Open-Loop Gain

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

INPUT DC ERRORS vs TEMPERATURE

Temperature (

100

Input Offset Voltage (mV)

Input Bias Current (

10X Input Offset Current (

Input Offset Voltage

Input Bias Current

10X Input Offset Current

100

0.1

CLOSED-LOOP OUTPUT IMPEDANCE

vs FREQUENCY

Frequency (Hz)

10k

100k

10M

100M

Output Impedance (

)

G = +1

= 25

SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

Temperature (

100

Power-Supply Current (mA)

160

140

120

100

Output Current (mA)

Sinking Output Current

Sourcing Output Current

Quiescent Supply Current

OPA634, OPA635

SBOS097A

TYPICAL PERFORMANCE CURVES: V

= +3V

At T

= 25

C, G = +2, R

= 750

, and R

= 150

to V

/2, unless otherwise noted (see Figure 2).

LARGE-SIGNAL FREQUENCY RESPONSE

Frequency (MHz)

Gain (dB)

100

300

= 0.2Vp-p

= 2Vp-p

= 1Vp-p

SMALL-SIGNAL FREQUENCY RESPONSE

Frequency (MHz)

Normalized Gain (dB)

100

300

= 0.2Vp-p

G = +10

G = +2

G = +5

HARMONIC DISTORTION vs LOAD RESISTANCE

(

)

100

500

400

300

200

Harmonic Distortion (dBc)

= 1Vp-p

= 5MHz

3rd-Harmonic

Distortion

2nd-Harmonic

Distortion

TWO-TONE, 3rd-ORDER

INTERMODULATION SPURIOUS

Single-Tone Load Power (dBm)

3rd-Order Spurious Level (dBc)

= 20MHz

= 10MHz

= 5MHz

Load Power at

Matched 50

Load

2nd-HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

2nd-Harmonic Distortion (dBc)

G = +10

G = +5

G = +2

= 1Vp-p

= 100

3rd-HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

3rd-Harmonic Distortion (dBc)

G = +10

= 1Vp-p

= 100

G = +5

G = +2

OPA634, OPA635

SBOS097A

APPLICATIONS INFORMATION

WIDEBAND VOLTAGE FEEDBACK OPERATION

The OPA634 and OPA635 are unity-gain stable, very high-
speed voltage feedback op amps designed for single supply
operation (+3V to +10V). The input stage supports input
voltages below ground, and to within 1.2V of the positive
supply. The complementary common-emitter output stage
provides an output swing to within 30mV of ground and
140mV of the positive supply. They are compensated to
provide stable operation with a wide range of resistive loads.
The OPA635's internal disable circuitry is designed to
minimize supply current when disabled.

Figure 1 shows the AC-coupled, gain of +2 configuration
used for the +5V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50

with a resistor to ground. Voltage swings reported in the
Specifications are taken directly at the input and output pins.
For the circuit of Figure 1, the total effective load on the
output at high frequencies is 150

|| 1500

. The disable pin

needs to be driven by a low impedance source, such as a
CMOS inverter. The 1.50k

resistors at the non-inverting

input provide the common-mode bias voltage. Their parallel
combination equals the DC resistance at the inverting input,
(R

), minimizing the DC offset.

SINGLE SUPPLY ADC CONVERTER INTERFACE

The front page shows a DC-coupled, single-supply ADC
(Analog-to-Digital Converter) driver circuit. Many systems
are now requiring +3V supply capability of both the ADC
and its driver. The OPA635 provides excellent performance
in this demanding application. Its large input and output
voltage ranges, and low distortion, support converters such
as the ADS900 shown in this figure. The input level-shifting
circuitry was designed so that V

can be between 0V and

0.5V, while delivering an output voltage of 1V to 2V for the
ADS900. Both the OPA635 and ADS900 have power reduc-
tion pins with the same polarity for those systems that need
to conserve power.

Figure 2 shows the DC-coupled, gain of +2 configuration
used for the +3V Specifications and Typical Performance
Curves. For test purposes, the input impedance is set to 50

with a resistor to ground. Though not strictly a "rail-to-rail"
design, these parts come very close, while maintaining
excellent performance. They will deliver

2.8Vp-p on a

single +3V supply with 70MHz bandwidth. The 374

and

2.26k

resistors at the input level-shift V

so that V

OUT

within the allowed output voltage range when V

= 0. See

the typical performance curves for information on driving
capacitive loads.

FIGURE 1. AC-Coupled Signal--Resistive Load to Supply

Midpoint.

FIGURE 2. DC-Coupled Signal--Resistive Load to Supply

Midpoint.

OPA63x

= 5V

DIS (OPA635 only)

OUT

53.6

1.50k

150

6.8

0.1

750

OPA63x

= 3V

DIS (OPA635 only)

OUT

57.6

750

562

374

2.26k

150

6.8

0.1

OPA634, OPA635

SBOS097A

DC LEVEL SHIFTING

Figure 3 shows a DC-coupled non-inverting amplifier that
level-shifts the input up to accommodate the desired output
voltage range. Given the desired signal gain (G), and the
amount V

OUT

needs to be shifted up (

OUT

) when V

is at

the center of its range, the following equations give the
resistor values that produce the desired performance. Start
by setting R

between 200

and 1.5k

NG = G +

OUT

= R

/(NG G)

= R

/(NG 1)

where:

NG = 1 + R

OUT

= (G)V

+ (NG G)V

Make sure that V

and V

OUT

stay within the specified input

and output voltage ranges.

NON-INVERTING AMPLIFIER WITH
REDUCED PEAKING

Figure 4 shows a non-inverting amplifier that reduces peak-
ing at low gains. The resistor R

compensates the OPA634

or OPA635 to have higher Noise Gain (NG), which reduces
the AC response peaking (typically 5dB at G = +1 without
R

) without changing the DC gain. V

needs to be a low

impedance source, such as an op amp. The resistor values
are low to reduce noise. Using both R

and R

helps

minimize the impact of parasitic impedances.

OPA63x

OUT

FIGURE 3. DC Level-Shifting Circuit.

OPA63x

OUT

FIGURE 4. Compensated Non-Inverting Amplifier.

The front page circuit is a good example of this type
of application. It was designed to take V

between

0V and 0.5V, and produce V

OUT

between 1V and 2V,

when using a +3V supply. This means G = 2.00, and

OUT

= 1.50V G · 0.25V = 1.00V. Plugging into the

above equations (with R

= 750

) gives: NG = 2.33,

= 375

, R

= 2.25k

, and R

= 563

. The resistors

were changed to the nearest standard values.

The Noise Gain can be calculated as follows:

G G

= +

A unity gain buffer can be designed by selecting R

= R

20.0

and R

= 40.2

(do not use R

). This gives a Noise

Gain of 2, so its response will be similar to the Characteris-
tics Plots with G = +2. Decreasing R

to 20.0

will increase

the Noise Gain to 3, which typically gives a flat frequency
response, but with less bandwidth.

The circuit in Figure 1 can be redesigned to have less
peaking by increasing the noise gain to 3. This is accom-
plished by adding R

= 2.55k

between the op amps inputs.

OPA634, OPA635

SBOS097A

DESIGN-IN TOOLS

DEMONSTRATION BOARDS

Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA634 and OPA635 in
their three package styles. These are available free as an
unpopulated PC board delivered with descriptive documen-
tation. The summary information for these boards is shown
in Table I.

BANDWIDTH VERSUS GAIN: NON-INVERTING OPERATION

Voltage feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the non-inverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90

, as it

does in high gain configurations. At low gains (increased
feedback factors), most amplifiers will exhibit a more com-
plex response with lower phase margin. The OPA634 and
OPA635 are compensated to give a slightly peaked response
in a non-inverting gain of 2 (Figure 1). This results in a
typical gain of +2 bandwidth of 150MHz, far exceeding that
predicted by dividing the 140MHz GBP by 2. Increasing the
gain will cause the phase margin to approach 90

and the

bandwidth to more closely approach the predicted value of
(GBP/NG). At a gain of +10, the 16MHz bandwidth shown
in the Typical Specifications is close to that predicted using
the simple formula and the typical GBP.

The OPA634 and OPA635 exhibit minimal bandwidth re-
duction going to +3V single supply operation as compared
with +5V supply. This is because the internal bias control
circuitry retains nearly constant quiescent current as the total
supply voltage between the supply pins is changed.

INVERTING AMPLIFIER OPERATION

Since the OPA634 and OPA635 are general-purpose, wideband
voltage- feedback op amps, all of the familiar op amp appli-
cation circuits are available to the designer. Figure 5 shows a
typical inverting configuration where the I/O impedances and
signal gain from Figure 1 are retained in an inverting circuit
configuration. Inverting operation is one of the more common
requirements and offers several performance benefits. The
inverting configuration shows improved slew rate and distor-
tion. It also allows the input to be biased at V

/2 without any

headroom issues. The output voltage can be independently
moved to be within the output voltage range with coupling
capacitors, or bias adjustment resistors.

BOARD

LITERATURE

PART

REQUEST

PRODUCT

PACKAGE

NUMBER

OPA63xU

SO-8

DEM-OPA68xU

MKT-351

OPA63xN

SOT23-5

DEM-OPA6xxN

MKT-348

SOT23-6

TABLE I. Demo Board Summary Information.

Contact the Texas Instruments Technical Applications Sup-
port Line at 1-972-644-5580 to request any of these boards.

OPERATING SUGGESTIONS

OPTIMIZING RESISTOR VALUES

Since the OPA634 and OPA635 are voltage feedback op
amps, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. For a non-inverting
unity gain follower application, the feedback connection
should be made with a 20

resistor, not a direct short (see

Figure 4 with R

). This will isolate the inverting input

capacitance from the output pin and improve the frequency
response flatness. Usually, for G > 1 application, the feed-
back resistor value should be between 200

and 1.5k

Below 200

, the feedback network will present additional

output loading which can degrade the harmonic distortion
performance. Above 1.5k

, the typical parasitic capacitance

(approximately 0.2pF) across the feedback resistor may
cause unintentional band-limiting in the amplifier response.

A good rule of thumb is to target the parallel combination of
R

and R

(Figure 1) to be less than approximately 400

The combined impedance R

|| R

interacts with the invert-

ing input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 3pF total parasitic on the inverting node, hold-
ing R

|| R

<400

will keep this pole above 130MHz. By

itself, this constraint implies that the feedback resistor R

can increase to several k

at high gains. This is acceptable

as long as the pole formed by R

and any parasitic capaci-

tance appearing in parallel is kept out of the frequency range
of interest.

FIGURE 5. AC-Coupled, Gain of 2 Example Circuit.

OPA63x

750

374

1.5k

57.6

Source

DIS

+5V

1.5k

0.1

6.8

0.1

Load

OPA634, OPA635

SBOS097A

In the inverting configuration, three key design consider-
ation must be noted. The first is that the gain resistor (R

)

becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted pair, long
PC board trace, or other transmission line conductor), R

may be set equal to the required termination value and R

adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise per-
formance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting R

for input matching eliminates the need for R

but

requires a 100

feedback resistor. This has the interesting

advantage of the noise gain becoming equal to 2 for a 50

source impedance--the same as the non-inverting circuits
considered above. However, the amplifier output will now
see the 100

feedback resistor in parallel with the external

load. In general, the feedback resistor should be limited to
the 200

to 1.5k

range. In this case, it is preferable to

increase both the R

and R

values, as shown in Figure 5,

and then achieve the input matching impedance with a third
resistor (R

) to ground. The total input impedance becomes

the parallel combination of R

and R

The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence influences the
bandwidth. For the example in Figure 5, the R

value

combines in parallel with the external 50

source imped-

ance (at high frequencies), yielding an effective driving
impedance of 50

|| 576

= 26.8

. This impedance is

added in series with R

for calculating the noise gain. The

resultant is 2.87 for Figure 5, as opposed to only 2 if R

could be eliminated as discussed above. The bandwidth will
therefore be lower for the gain of 2 circuit of Figure 5
(NG = +2.87) than for the gain of +2 circuit of Figure 1.

The third important consideration in inverting amplifier
design is setting the bias current cancellation resistors on the
non-inverting input (a parallel combination of R

= 750

If this resistor is set equal to the total DC resistance looking
out of the inverting node, the output DC error, due to the
input bias currents, will be reduced to (Input Offset Current)
times R

. With the DC blocking capacitor in series with R

the DC source impedance looking out of the inverting mode
is simply R

= 750

for Figure 5. To reduce the additional

high-frequency noise introduced by this resistor, and power-
supply feedthrough, R

is bypassed with a capacitor. As

long as R

< 400

, its noise contribution will be minimal.

As a minimum, the OPA634 and OPA635 require an R

value of 50

to damp out parasitic-induced peaking--a

direct short to ground on the non-inverting input runs the
risk of a very high-frequency instability in the input stage.

OUTPUT CURRENT AND VOLTAGE

The OPA634 and OPA635 provide outstanding output volt-
age capability. Under no-load conditions at +25

C, the

output voltage typically swings closer than 140mV to either
supply rail; the guaranteed over temperature swing is within
300mV of either rail (V

= +5V).

The minimum specified output voltage and current specifi-
cations over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold start-up will the
output current and voltage decrease to the numbers shown in
the guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
V

's (increasing the available output voltage swing) and

increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications, since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.

To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem, since most applications include a series
matching resistor at the output that will limit the internal
power dissipation if the output side of this resistor is shorted
to ground. However, shorting the output pin directly to the
adjacent positive power-supply pin (8-pin packages) will, in
most cases, destroy the amplifier. If additional short-circuit
protection is required, consider a small series resistor in the
power-supply leads. This will, under heavy output loads,
reduce the available output voltage swing.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC--including additional
external capacitance which may be recommended to im-
prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA634 and OPA635 can be very suscep-
tible to decreased stability and closed-loop response peaking
when a capacitive load is placed directly on the output pin.
When the primary considerations are frequency response
flatness, pulse response fidelity, and/or distortion, the sim-
plest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load.

The Typical Performance Curves show the recommended
R

versus capacitive load and the resulting frequency re-

sponse at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA634
and OPA635. Long PC board traces, unmatched cables, and
connections to multiple devices can easily exceed this value.
Always consider this effect carefully, and add the recom-
mended series resistor as close as possible to the output pin
(see Board Layout Guidelines section).

OPA634, OPA635

SBOS097A

The criterion for setting this R

resistor is a maximum

bandwidth, flat frequency response at the load. For a gain of
+2, the frequency response at the output pin is already
slightly peaked without the capacitive load, requiring rela-
tively high values of R

to flatten the response at the load.

Increasing the noise gain will also reduce the peaking (see
Figure 4).

DISTORTION PERFORMANCE

The OPA634 and OPA635 provide good distortion perfor-
mance into a 150

load. Relative to alternative solutions, it

provides exceptional performance into lighter loads and/or
operating on a single +3V supply. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd harmonic will dominate the distortion with a
negligible 3rd harmonic component. Focusing then on the
2nd harmonic, increasing the load impedance improves
distortion directly. Remember that the total load includes
the feedback network; in the non-inverting configuration
(Figure 1) this is sum of R

+ R

, while in the inverting

configuration, only R

needs to be included in parallel with

the actual load.

NOISE PERFORMANCE

High slew rate, unity gain stable, voltage-feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 5.6nV/

Hz input voltage noise for

the OPA634 and OPA635 is, however, much lower than
comparable amplifiers. The input-referred voltage noise,
and the two input-referred current noise terms (2.8pA/

Hz),

combine to give low output noise under a wide variety of
operating conditions. Figure 6 shows the op amp noise
analysis model with all the noise terms included. In this
model, all noise terms are taken to be noise voltage or
current density terms in either nV/

Hz or pA/

Hz.

The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 6:

(1)

(

)

+ 4

kTR

(

)

(

)

+ 4

kTR

Dividing this expression by the noise gain (NG = (1 + R

))

will give the equivalent input-referred spot noise voltage at
the non-inverting input, as shown in Equation 2:

(2)

(

)

+ 4

kTR

+ 4

kTR

Evaluating these two equations for the circuit and compo-
nent values shown in Figure 1 will give a total output spot
noise voltage of 12.5nV/

Hz and a total equivalent input

spot noise voltage of 6.3nV/

Hz. This is including the noise

added by the resistors. This total input-referred spot noise
voltage is not much higher than the 5.6nV/

Hz specification

for the op amp voltage noise alone. This will be the case as
long as the impedances appearing at each op amp input are
limited to the previously recommend maximum value of
400

, and the input attenuation is low.

DC ACCURACY AND OFFSET CONTROL

The balanced input stage of a wideband voltage-feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power-supply current trim for the OPA634
and OPA635 gives even tighter control than comparable
products. Although the high-speed input stage does require
relatively high input bias current (typically 25

A out of each

input terminal), the close matching between them may be
used to reduce the output DC error caused by this current.
This is done by matching the DC source resistances appear-
ing at the two inputs. Evaluating the configuration of
Figure 1 (which has matched DC input resistances), using
worst-case +25

C input offset voltage and current specifica-

tions, gives a worst-case output offset voltage equal to:
(NG = non-inverting signal gain at DC)

(NG · V

OS(MAX)

)

· I

OS(MAX)

)

(1 · 7.0mV)

(750

· 2.25

8.7mV

A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques are based on adding a DC
current through the feedback resistor. In selecting an offset
trim method, one key consideration is the impact on the
desired signal path frequency response. If the signal path is

FIGURE 6. Noise Analysis Model.

4kT

OPA63x

4kT = 1.6E 20J

at 290

4kTR

OPA634, OPA635

SBOS097A

intended to be non-inverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
inverting, applying the offset control to the non-inverting
input may be considered. Bring the DC offsetting current
into the inverting input node through resistor values that are
much larger than the signal path resistors. This will insure
that the adjustment circuit has minimal effect on the loop
gain and hence the frequency response.

DISABLE OPERATION

The OPA635 provides a disable feature that may be used
either to reduce system power or to implement a simple
channel multiplexing operation. To disable, the control pin
must be asserted HIGH. Figure 7 shows a simplified internal
circuit for the disable control feature.

output stage (P

) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total
supply voltage across the part. P

will depend on the

required output signal and load but would, for resistive load
connected to mid-supply (V

/2), be at a maximum when the

output is fixed at a voltage equal to V

/4 or 3V

/4. Under this

condition, P

= V

/(16 · R

), where R

includes feedback

network loading.

Note that it is the power in the output stage, and not into the
load, that determines internal power dissipation.

As a worst-case example, compute the maximum T

using

an OPA635 (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85

C and driving a 150

load at mid-supply.

= 10V · 13.5mA + 5

/(16 · (150

|| 1500

)) = 144mW

Maximum T

= +85

C + (0.14W · 150

C/W) = 107

Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. The highest
possible internal dissipation will occur if the load requires
current to be forced into the output at high output voltages
or sourced from the output at low output voltages. This puts
a high current through a large internal voltage drop in the
output transistors.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high frequency
amplifier like the OPA634 and OPA635 requires careful
attention to board layout parasitics and external component
types. Recommendations that will optimize performance
include:

a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.

b) Minimize the distance (<0.25") from the power-supply
pins to high frequency 0.1

F decoupling capacitors. At the

device pins, the ground and power plane layout should not be
in close proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between the pins
and the decoupling capacitors. Each power-supply connec-
tion should always be decoupled with one of these capacitors.
An optional supply decoupling capacitor (0.1

F) across the

two power supplies (for bipolar operation) will improve 2nd-
harmonic distortion performance. Larger (2.2

F to 6.8

decoupling capacitors, effective at lower frequency, should
also be used on the main supply pins. These may be placed
somewhat farther from the device and may be shared among
several devices in the same area of the PC board.

50k

Control

DIS

FIGURE 7. Simplified Disable Control Circuit (OPA635).

In normal operation, base current to Q1 is provided through
the 50k

resistor.

One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode.

The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. Adding a simple RC filter into the DIS
pin from a higher speed logic line will reduce the glitch. If
extremely fast transition logic is used, a 1k

series resistor

will provide adequate bandlimiting using just the parasitic
input capacitance on the DIS pin while still ensuring ad-
equate logic level swing.

THERMAL ANALYSIS

Maximum desired junction temperature will set the maxi-
mum allowed internal power dissipation, as described be-
low. In no case should the maximum junction temperature
be allowed to exceed 175

Operating junction temperature (T

) is given by T

+ P

The total internal power dissipation (P

) is the sum of

quiescent power (P

) and additional power dissipated in the

OPA634, OPA635

SBOS097A

c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance.
Resistors should be a very low reactance type. Surface-
mount resistors work best and allow a tighter overall layout.
Metal film or carbon composition axially-leaded resistors
can also provide good high-frequency performance. Again,
keep their leads and PC board traces as short as possible.
Never use wirewound type resistors in a high-frequency
application. Since the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position
the feedback and series output resistor, if any, as close as
possible to the output pin. Other network components, such
as non-inverting input termination resistors, should also be
placed close to the package. Where double-side component
mounting is allowed, place the feedback resistor directly
under the package on the other side of the board between the
output and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors, excessively high
resistor values can create significant time constants that can
degrade performance. Good axial metal film or surface-
mount resistors have approximately 0.2pF in shunt with the
resistor. For resistor values >1.5k

, this parasitic capaci-

tance can add a pole and/or zero below 500MHz that can
effect circuit operation. Keep resistor values as low as
possible consistent with load driving considerations. The
750

feedback used in the typical performance specifica-

tions is a good starting point for design

d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R

from the

typical performance curve "Recommended R

vs Capacitive

Load". Low parasitic capacitive loads (< 5pF) may not need
an R

since the OPA634 and OPA635 are nominally com-

pensated to operate with a 2pF parasitic load. Higher para-
sitic capacitive loads without an R

are allowed as the signal

gain increases (increasing the unloaded phase margin) If a
long trace is required, and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable, imple-
ment a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50

environ-

ment is normally not necessary on board, and in fact, a
higher impedance environment will improve distortion as
shown in the distortion versus load plots. With a character-
istic board trace impedance defined (based on board material
and trace dimensions), a matching series resistor into the
trace from the output of the OPA634 and OPA635 is used as
well as a terminating shunt resistor at the input of the
destination device. Remember also that the terminating

impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. If the 6dB attenuation of a doubly termi-
nated transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as a
capacitive load in this case and set the series resistor value
as shown in the typical performance curve "Recommended
R

vs Capacitive Load". This will not preserve signal integ-

rity as well as a doubly-terminated line. If the input imped-
ance of the destination device is low, there will be some
signal attenuation due to the voltage divider formed by the
series output into the terminating impedance.

e) Socketing a high-speed part is not recommended. The
additional lead length and pin-to-pin capacitance introduced
by the socket can create an extremely troublesome parasitic
network which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are obtained
by soldering the OPA634 and OPA635 onto the board. If
socketing for the DIP package is desired, high frequency
flush mount pins (e.g., McKenzie Technology #710C) can
give good results.

INPUT AND ESD PROTECTION

The OPA634 and OPA635 are is built using a very high-
speed complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very small
geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins are pro-
tected with internal ESD protection diodes to the power
supplies, as shown in Figure 8.

External

Internal
Circuitry

FIGURE 8. Internal ESD Protection.

These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with

15V supply

parts driving into the OPA634 and OPA635), current-limit-
ing series resistors should be added into the two inputs. Keep
these resistor values as low as possible, since high values
degrade both noise performance and frequency response.

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