Wideband, Current Feedback
OPERATIONAL AMPLIFIER With Disable
TM
DESCRIPTION
The OPA681 sets a new level of performance for broadband
current feedback op amps. Operating on a very low 6mA
supply current, the OPA681 offers a slew rate and output
power normally associated with a much higher supply cur-
rent. A new output stage architecture delivers a high output
current with minimal voltage headroom and crossover
distortion. This gives exceptional single-supply operation.
Using a single +5V supply, the OPA681 can deliver a 1V to
4V output swing with over 100mA drive current and 150MHz
bandwidth. This combination of features makes the OPA681
an ideal RGB line driver or single-supply ADC input driver.
The OPA681's low 6mA supply current is precisely trimmed
at 25
C. This trim, along with low drift over temperature,
OPA681
FEATURES
q
WIDEBAND +5V OPERATION: 225MHz (G = +2)
q
UNITY GAIN STABLE: 280MHz (G = 1)
q
HIGH OUTPUT CURRENT: 150mA
q
OUTPUT VOLTAGE SWING:
4.0V
q
HIGH SLEW RATE: 2100V/
s
q
LOW dG/d
: .001% /.01
q
LOW SUPPLY CURRENT: 6mA
q
LOW DISABLED CURRENT: 320
A
APPLICATIONS
q
xDSL LINE DRIVER
q
BROADBAND VIDEO BUFFERS
q
HIGH SPEED IMAGING CHANNELS
q
PORTABLE INSTRUMENTS
q
ADC BUFFERS
q
ACTIVE FILTERS
q
WIDEBAND INVERTING SUMMING
q
HIGH SFDR IF AMPLIFIER
guarantees lower guaranteed maximum supply current than
competing products. System power may be further reduced by
using the optional disable control pin. Leaving this disable pin
open, or holding it high, gives normal operation. If pulled low,
the OPA681 supply current drops to less than 320
A while the
output goes into a high impedance state. This feature may be
used for either power savings or for video MUX applications.
OPA681 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
Voltage Feedback
OPA680
OPA2680
OPA3680
Current Feedback
OPA681
OPA2681
OPA3681
Fixed Gain
OPA682
OPA2682
OPA3682
OPA681
OPA681
OPA6
81
Copyright 1997, Texas Instruments Incorporated
SBOS084A
Printed in U.S.A. February, 2001
100
50
OPA681
+5V
DIS
5V
V
O
=
(V
1
+ V
2
+ V
3
+ V
4
+ V
5
)
100MHz, 1dB Compression
= 15dBm
50
V
2
50
V
3
50
V
4
50
V
1
50
RG-58
50
V
5
23.7
200MHz RF Summing Amplifier
www.ti.com
OPA681
2
SBOS084A
SPECIFICATIONS: V
S
=
5V
R
F
= 402
, R
L
= 100
, and G = +2
,
(Figure 1 for AC performance only), unless otherwise noted.
OPA681P, U, N
TYP
GUARANTEED
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(2)
70
C
(3)
+85
C
(3)
UNITS
MAX
LEVEL
(1)
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth (V
O
= 0.5Vp-p)
G = +1, R
F
= 453
280
MHz
typ
C
G = +2, R
F
= 402
220
220
210
190
MHz
min
B
G = +5, R
F
= 261
185
MHz
typ
C
G = +10, R
F
= 180
180
MHz
typ
C
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
= 0.5Vp-p
90
50
45
45
MHz
min
B
Peaking at a Gain of +1
R
F
= 453, V
O
= 0.5Vp-p
0.4
2
4
dB
max
B
Large Signal Bandwidth
G = +2, V
O
= 5Vp-p
150
MHz
typ
C
Slew Rate
G = +2, 4V Step
2100
1600
1600
1200
V/
s
min
B
Rise/Fall Time
G = +2, V
O
= 0.5V Step
1.7
ns
typ
C
G = +2, 5V Step
2.0
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
12
ns
typ
C
0.1%
G = +2, V
O
= 2V Step
8
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd Harmonic
R
L
= 100
79
73
70
68
dBc
max
B
R
L
500
85
77
70
69
dBc
max
B
3rd Harmonic
R
L
= 100
74
71
71
68
dBc
max
B
R
L
500
77
75
74
72
dBc
max
B
Input Voltage Noise
f > 1MHz
2.5
3.0
3.4
3.6
nV/
Hz
max
B
Non-Inverting Input Current Noise
f > 1MHz
12
14
15
15
pA/
Hz
max
B
Inverting Input Current Noise
f > 1MHz
15
18
18
19
pA/
Hz
max
B
Differential Gain
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
0.001
%
typ
C
R
L
= 37.5
0.008
%
typ
C
Differential Phase
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
0.01
deg
typ
C
R
L
= 37.5
0.05
deg
typ
C
DC PERFORMANCE
(4)
Open-Loop Transimpedance Gain (Z
OL
)
V
O
= 0V, R
L
= 100
100
56
56
56
k
min
A
Input Offset Voltage
V
CM
= 0V
1.3
5
6.5
7.5
mV
max
A
Average Offset Voltage Drift
V
CM
= 0V
+35
+40
V/
C
max
B
Non-Inverting Input Bias Current
V
CM
= 0V
+30
+55
65
85
A
max
A
Average Non-Inverting Input Bias Current Drift
V
CM
= 0V
400
450
nA/
C
max
B
Inverting Input Bias Current
V
CM
= 0V
10
40
50
55
A
max
A
Average Inverting Input Bias Current Drift
V
CM
= 0V
125
150
nA
/C
max
B
INPUT
Common-Mode Input Range
(5)
3.5
3.4
3.3
3.2
V
min
A
Common-Mode Rejection
V
CM
= 0V
52
47
46
45
dB
min
A
Non-Inverting Input Impedance
100 || 2
k
|| pF
typ
C
Inverting Input Resistance (R
I
)
Open-Loop
42
typ
C
OUTPUTTM
Voltage Output Swing
No Load
4.0
3.8
3.7
3.6
V
min
A
100
Load
3.9
3.7
3.6
3.3
V
min
A
Current Output, Sourcing
V
O
= 0
+190
+160
+140
+80
mA
min
A
Current Output, Sinking
V
O
= 0
150
135
130
80
mA
min
A
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.03
typ
C
DISABLE (Disabled Low)
Power Down Supply Current (+V
S
)
V
DIS
= 0
320
A
typ
C
Disable Time
100
ns
typ
C
Enable Time
25
ns
typ
C
Off Isolation
G = +2, 5MHz
70
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn On Glitch
G = +2, R
L
= 150
, V
IN
= 0
50
mV
typ
C
Turn Off Glitch
G = +2, R
L
= 150
, V
IN
= 0
20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current (DIS)
V
DIS
= 0
100
160
160
160
A
max
A
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage Range
6
6
6
V
max
A
Max Quiescent Current
V
S
=
5V
6
6.4
6.5
6.6
mA
max
A
Min Quiescent Current
V
S
=
5V
6
5.6
5.5
5.0
mA
min
A
Power Supply Rejection Ratio (PSRR)
Input Referred
58
52
50
49
dB
min
A
TEMPERATURE RANGE
Specification: P, U, N
40 to +85
C
typ
C
Thermal Resistance,
JA
Junction-to-Ambient
P
8-Pin DIP
100
C/W
typ
C
U
SO-8
125
C/W
typ
C
N
SOT23-6
150
C/W
typ
C
NOTES: (1) Test levels: (A) 100% tested at 25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25
C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23
C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node.
V
CM
is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at
CMIR limits.
3
OPA681
SBOS084A
SPECIFICATIONS: V
S
= +5V
R
F
= 499
, R
L
= 100
to V
S
/2, and G = +2
,
(Figure 2 for AC performance only), unless otherwise noted.
OPA681P, U, N
TYP
GUARANTEED
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(2)
70
C
(3)
+85
C
(3)
UNITS
MAX
LEVEL
(1)
AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth (V
O
= 0.5Vp-p)
G = +1, R
F
= 649
250
MHz
typ
C
G = +2, R
F
= 499
225
180
140
110
MHz
min
B
G = +5, R
F
= 360
180
MHz
typ
C
G = +10, R
F
= 200
165
MHz
typ
C
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
< 0.5Vp-p
100
50
35
23
MHz
min
B
Peaking at a Gain of +1
R
F
= 649
, V
O
< 0.5Vp-p
0.4
2
4
dB
max
B
Large-Signal Bandwidth
G = +2, V
O
= 2Vp-p
200
MHz
typ
C
Slew Rate
G = +2, 2V Step
830
700
680
570
V/
s
min
B
Rise/Fall Time
G = +2, V
O
= 0.5V Step
1.5
ns
typ
C
G = +2, V
O
= 2V Step
2.0
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
14
ns
typ
C
0.1%
G = +2, V
O
= 2V Step
9
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd Harmonic
R
L
= 100
to V
S
/ 2
70
68
67
63
dBc
max
B
R
L
500
to V
S
/2
72
70
70
68
dBc
max
B
3rd Harmonic
R
L
= 100
to V
S
/ 2
72
65
65
62
dBc
max
B
R
L
500
to V
S
/2
73
68
67
67
dBc
max
B
Input Voltage Noise
f > 1MHz
2.2
3
3.4
3.6
nV/
Hz
max
B
Non-Inverting Input Current Noise
f > 1MHz
12
14
14
15
pA/
Hz
max
B
Inverting Input Current Noise
f > 1MHz
15
18
18
19
pA/
Hz
max
B
DC PERFORMANCE
(4)
Open-Loop Transimpedance Gain (Z
OL
)
V
O
= V
S
/2, R
L
= 100
to V
S
/2
100
60
53
51
k
min
A
Input Offset Voltage
V
CM
= 2.5V
1
5
6.0
7
mV
max
A
Average Offset Voltage Drift
V
CM
= 2.5V
+15
+20
V/
C
max
B
Non-Inverting Input Bias Current
V
CM
= 2.5V
+40
+65
+75
+95
A
max
A
Average Non-Inverting Input Bias Current Drift
V
CM
= 2.5V
300
350
nA/
C
max
B
Inverting Input Bias Current
V
CM
= 2.5V
5
20
25
35
A
max
A
Average Inverting Input Bias Current Drift
V
CM
= 2.5V
125
175
nA /
C
max
B
INPUT
Least Positive Input Voltage
(5)
1.5
1.6
1.7
1.8
V
max
A
Most Positive Input Voltage
(5)
3.5
3.4
3.3
3.2
V
min
A
Common-Mode Rejection Ratio (CMRR)
V
CM
= V
S
/2
51
45
44
44
dB
min
A
Non-Inverting Input Impedance
100 || 2
k
|| pF
typ
C
Min Inverting Input Resistance (R
I
)
Open-Loop
46
38
36
35
min
A
Max Inverting Input Resistance (R
I
)
Open-Loop
46
53
55
60
max
A
OUTPUT
Most Positive Output Voltage
No Load
4
3.8
3.7
3.5
V
min
A
R
L
= 100
to V
S
/2
3.9
3.7
3.6
3.4
V
min
A
Least Positive Output Voltage
No Load
1
1.2
1.3
1.5
V
max
A
R
L
= 100
to V
S
/2
1.1
1.3
1.4
1.6
V
max
A
Current Output, Sourcing
V
O
= V
S
/2
150
110
110
60
mA
min
A
Current Output, Sinking
V
O
= V
S
/2
110
75
70
50
mA
min
A
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.03
typ
C
DISABLE (Disable Low)
Power Down Supply Current (+V
S
)
V
DIS
= 0
270
A
typ
C
Disable Time
100
ns
typ
C
Enable Time
25
ns
typ
C
Off Isolation
G = +2, 5MHz
65
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn On Glitch
G = +2, R
L
= 150
, V
IN
= V
S
/2
50
mV
typ
C
Turn Off Glitch
G = +2, R
L
= 150
, V
IN
= V
S
/2
20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current (DIS)
V
DIS
= 0
100
A
typ
C
POWER SUPPLY
Specified Single-Supply Operating Voltage
5
V
typ
C
Max Single-Supply Operating Voltage
12
12
12
V
max
A
Max Quiescent Current
V
S
= +5V
5.3
5.4
5.5
5.5
mA
max
A
Min Quiescent Current
V
S
= +5V
5.3
4.1
3.7
3.6
mA
min
A
Power Supply Rejection Ratio (PSRR)
Input Referred
48
dB
typ
C
TEMPERATURE RANGE
Specification: P, U, N
40 to +85
C
typ
C
Thermal Resistance,
JA
Junction-to-Ambient
P
8-Pin DIP
100
C/W
typ
C
U
SO-8
125
C/W
typ
C
N
SOT23-6
150
C/W
typ
C
NOTES: (1) Test levels: (A) 100% tested at 25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25
C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23
C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node.
V
CM
is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at
CMIR limits.
OPA681
4
SBOS084A
ABSOLUTE MAXIMUM RATINGS
Power Supply ..............................................................................
6.5VDC
Internal Power Dissipation
(1)
............................ See Thermal Information
Differential Input Voltage ..................................................................
1.2V
Input Voltage Range ............................................................................
V
S
Storage Temperature Range: P, U, N ........................... 40
C to +125
C
Lead Temperature (soldering, 10s) .............................................. +300
C
Junction Temperature (T
J
) ........................................................... +175
C
NOTE:: (1) Packages must be derated based on specified
JA
. Maximum T
J
must be observed.
PACKAGE
SPECIFIED
DRAWING
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
(1)
RANGE
MARKING
NUMBER
(2)
MEDIA
OPA681P
8-Pin Plastic DIP
006
40
C to +85
C
OPA681P
OPA681P
Rails
OPA681U
SO-8 Surface Mount
182
40
C to +85
C
OPA681U
OPA681U
Rails
"
"
"
"
"
OPA681U/2K5
Tape and Reel
OPA681N
6-Lead SOT23-6
332
40
C to +85
C
A81
OPA681N/250
Tape and Reel
"
"
"
"
"
OPA681N/3K
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet. (2) Models with a slash (/) are available only as Tape and Reel in the quantity
indicated after the slash (e.g. /2K5 indicates 2500 devices per reel). Ordering 3000 pieces of the OPA681N/3K will get a single 3000-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from perfor-
mance degradation to complete device failure. Burr-Brown Corpo-
ration recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
1
2
3
6
5
4
Output
V
S
Non-Inverting Input
+V
S
DIS
Inverting Input
1
2
3
6
5
4
A81
Pin Orientation/Package Marking
PIN CONFIGURATION
Top View
DIP/SO-8
Top View
SOT23-6
1
2
3
4
8
7
6
5
NC
Inverting Input
Non-Inverting Input
V
S
DIS
+V
S
Output
NC
NC = No Connection
5
OPA681
SBOS084A
TYPICAL PERFORMANCE CURVES: V
S
=
5V
G = +2, R
F
= 402
, and R
L
= 100
, unless otherwise noted (see Figure 1).
+4
+3
+2
+1
0
1
2
3
4
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (1V/div)
G = +2
V
O
= 5Vp-p
400
300
200
100
0
100
200
300
400
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
G = +2
V
O
= 0.5Vp-p
DISABLED FEEDTHROUGH vs FREQUENCY
45
50
55
60
65
70
75
80
85
90
95
Frequency (MHz)
1
10
100
Feedthrough (5dB/div)
Forward
V
DIS
= 0
Reverse
8
7
6
5
4
3
2
1
0
1
2
Frequency (25MHz/div)
0
250MHz
125MHz
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (1dB/div)
2Vp-p
G = +2, R
L
= 100
1Vp-p
4Vp-p
7Vp-p
2.0
1.6
1.2
0.8
0.4
0
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
Time (50ns/div)
Output Voltage (400mV/div)
6.0
4.0
2.0
0
V
DIS
(2V/div)
V
DIS
Output Voltage
G = +2
V
IN
= +1V
2
1
0
1
2
3
4
5
6
7
8
Frequency (25MHz/div)
0
250MHz
125MHz
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = +10, R
F
= 180
G = +5, R
F
= 261
G = +1, R
F
= 453
G = +2, R
F
= 402
OPA681
6
SBOS084A
TYPICAL PERFORMANCE CURVES: V
S
=
5V
(Cont.)
G = +2, R
F
= 402
, and R
L
= 100
, unless otherwise noted (see Figure 1).
60
65
70
75
80
85
90
5MHz 2ND HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1
1
10
2nd Harmonic Distortion (dBc)
R
L
= 200
R
L
= 500
R
L
= 100
60
65
70
75
80
85
90
5MHz 3RD HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1
1
10
3rd Harmonic Distortion (dBc)
R
L
= 200
R
L
= 100
R
L
= 500
60
65
70
75
80
85
90
10MHz 2ND HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1
1
10
2nd Harmonic Distortion (dBc)
R
L
= 500
R
L
= 100
R
L
= 200
60
65
70
75
80
85
90
10MHz 3RD HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1
1
10
3rd Harmonic Distortion (dBc)
R
L
= 500
R
L
= 100
R
L
= 200
50
55
60
65
70
75
80
20MHz 2ND HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1
1
10
2nd Harmonic Distortion (dBc)
R
L
= 500
R
L
= 100
R
L
= 200
50
55
60
65
70
75
80
20MHz 3RD HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1
1
10
3rd Harmonic Distortion (dBc)
R
L
= 500
R
L
= 100
R
L
= 200
7
OPA681
SBOS084A
TYPICAL PERFORMANCE CURVES: V
S
=
5V
(Cont.)
G = +2, R
F
= 402
, and R
L
= 100
, unless otherwise noted (see Figure 1).
40
50
60
70
80
90
2ND HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1
1
10
20
2nd Harmonic Distortion (dBc)
V
O
= 2Vp-p
R
L
= 100
G = +2, R
F
= 402
G = +10, R
F
= 180
G = +5, R
F
= 261
40
50
60
70
80
90
3RD HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1
1
10
20
3rd Harmonic Distortion (dBc)
V
O
= 2Vp-p
R
L
= 100
G = +2,
R
F
= 402
G = +10, R
F
= 180
G = +5, R
F
= 261
40
45
50
55
60
65
70
75
80
85
90
TWO-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
Single-Tone Load Power (dBm)
8
6
4
2
0
2
4
6
8
10
3rd-Order Spurious Level (dBc)
dBc = dB below carriers
50MHz
20MHz
10MHz
Load Power at Matched 50
Load
60
50
40
30
20
10
0
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1
10
100
R
S
(
)
15
12
9
6
3
0
3
6
9
12
15
Frequency (30MHz/div)
0
300MHz
150MHz
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Gain to Capacitive Load (3dB/div)
OPA681
R
S
V
IN
V
O
C
L
1k
402
402
1k
is optional.
C
L
= 22pF
C
L
= 10pF
C
L
= 47pF
C
L
= 100pF
100
10
1
INPUT VOLTAGE AND CURRENT NOISE DENSITY
Frequency (Hz)
100
1k
10k
100k
1M
10M
Current Noise (pA/
Hz)
Voltage Noise (nV/
Hz)
Non-Inverting Input Current Noise
Inverting Input Current Noise
12.2pA/
Hz
15.1pA/
Hz
Voltage Noise
2.2nV/
Hz
OPA681
8
SBOS084A
TYPICAL PERFORMANCE CURVES: V
S
=
5V
(Cont.)
G = +2, R
F
= 402
, and R
L
= 100
, unless otherwise noted (see Figure 1).
5
4
3
2
1
0
1
2
3
4
5
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
300
200
100
0
100
200
300
V
O
(Volts)
100
Load Line
50
Load Line
25
Load Line
Output Current Limited
1W Internal
Power Limit
1W Internal
Power Limit
Output Current Limit
10
7.5
5
2.5
0
200
150
100
50
0
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (C)
40
20
0
20
40
60
80
100
120
140
Supply Current (2.5mA/div)
Output Current (mA)
Quiescent Supply Current
Sourcing Output Current
Sinking Output Current
120
100
80
60
40
20
0
OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE
Frequency (Hz)
10
4
10
5
10
6
10
7
10
8
10
9
Transimpedance Gain (20dB
/div)
0
40
80
120
160
200
240
Transimpedance Phase (40
/div)
| Z
OL
|
Z
OL
0.05
0.04
0.03
0.02
0.01
0
Number of 150
Loads
1
2
3
4
COMPOSITE VIDEO dG/d
Positive Video
Negative Sync
d
dG
dG/d
(%/
)
5
4
3
2
1
0
1
2
3
4
5
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (
C)
40
20
V
IO
0
20
40
60
80
100
120
140
Input Offset Voltage (mV)
50
40
30
20
10
0
10
20
30
40
50
Input Bias Currents (
A)
Non-Inverting Input Bias Current
Inverting Input
Bias Current
70
65
60
55
50
45
40
35
30
25
20
Frequency (Hz)
10
2
10
3
10
4
10
5
10
6
10
7
10
8
CMRR AND PSRR vs FREQUENCY
Rejection Ratio (dB)
+PSRR
PSRR
CMRR
9
OPA681
SBOS084A
TYPICAL PERFORMANCE CURVES: V
S
= +5V
G = +2, R
F
= 499
, and R
L
= 100
to +2.5V, unless otherwise noted (see Figure 2).
2.10
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
G = +2
V
O
= 0.5Vp-p
2
1
0
1
2
3
4
5
6
7
8
Frequency (25MHz/div)
0
250
125
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = +2,
R
F
= 499
G = +10,
R
F
= 200
G = +5,
R
F
= 360
G = +1,
R
F
= 649
70
60
50
40
30
20
10
0
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1
10
100
R
S
(
)
8
7
6
5
4
3
2
1
0
1
2
Frequency (25MHz/div)
0
250
125
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (1dB/div)
G = +2
R
L
= 100
to 2.5V
V
O
= 0.5Vp-p
V
O
= 1Vp-p
V
O
= 2Vp-p
4.5
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
0.5
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (400mV/div)
G = +2
V
O
= 2Vp-p
15
12
9
6
3
0
3
6
9
12
15
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (20MHz/div)
0
200MHz
100MHz
Gain to Capacitive Load (3dB/div)
C
L
= 22pF
C
L
= 10pF
C
L
= 47pF
C
L
= 100pF
OPA681
499
499
57.6
806
806
1k
V
I
+5V
0.1
F
V
O
R
S
C
L
0.1
F
1k
is optional.
OPA681
10
SBOS084A
TYPICAL PERFORMANCE CURVES: V
S
= +5V
(Cont.)
G = +2, R
F
= 499
, and R
L
= 100
to +2.5V, unless otherwise noted (see Figure 2).
10
1
0.1
0.01
CLOSED-LOOP OUTPUT IMPEDANCE
Frequency (Hz)
10k
100M
100k
1M
10M
Output Impedance (
)
OPA681
402
+5
5
402
50
Z
O
45
50
55
60
65
70
75
80
85
Single-Tone Load Power (dBm)
14
12
10
8
6
4
2
0
2
TWO-TONE, 3RD ORDER SPURIOUS LEVEL
3rd Order Spurious (dBc)
50MHz
dBc = dB below carriers
20MHz
10MHz
Load Power at Matched 50
Load
40
50
60
70
80
2ND HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1
1
10
20
2nd Harmonic Distortion (dBc)
V
O
= 2Vp-p
R
L
= 100
to 2.5V
G = +2, R
F
= 499
G = +10, R
F
= 200
G = +5, R
F
= 360
3RD HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1
1
10
20
3rd Harmonic Distortion (dBc)
40
50
60
70
80
V
O
= 2Vp-p
R
L
= 100
to 2.5V
G = +10, R
F
= 200
G = +5, R
F
= 360
G = +2, R
F
= 499
2ND HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1
1
10
20
2nd Harmonic Distortion (dBc)
R
L
= 200
R
L
= 100
50
60
70
80
90
V
O
= 2Vp-p
G = +2
Loads to 2.5V
R
L
= 500
3RD HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1
1
10
20
3rd Harmonic Distortion (dBc)
50
60
70
80
90
V
O
= 2Vp-p
G = +2
R
L
= 100
R
L
= 500
R
L
= 200
Loads to 2.5V
11
OPA681
SBOS084A
APPLICATIONS INFORMATION
WIDEBAND CURRENT FEEDBACK OPERATION
The OPA681 gives the exceptional AC performance of a
wideband current feedback op amp with a highly linear, high
power output stage. Requiring only 6mA quiescent current,
the OPA681 will swing to within 1V of either supply rail and
deliver in excess of 135mA guaranteed at room temperature.
This low output headroom requirement, along with supply
voltage independent biasing, gives remarkable single (+5V)
supply operation. The OPA681 will deliver greater than
200MHz bandwidth driving a 2Vp-p output into 100
on a
single +5V supply. Previous boosted output stage amplifiers
have typically suffered from very poor crossover distortion
as the output current goes through zero. The OPA681
achieves a comparable power gain with much better linear-
ity. The primary advantage of a current feedback op amp
over a voltage feedback op amp is that AC performance
(bandwidth and distortion) is relatively independent of sig-
nal gain. For similar AC performance at low gain, with
improved DC accuracy, consider the high slew rate, unity
gain stable, voltage feedback OPA680.
Figure 1 shows the DC coupled, gain of +2, dual power
supply circuit configuration used as the basis of the
5V
Specifications and Typical Performance Curves. For test
purposes, the input impedance is set to 50
with a resistor
to ground and the output impedance is set to 50
with a
series output resistor. Voltage swings reported in the speci-
fications are taken directly at the input and output pins while
load powers (dBm) are defined at a matched 50
load. For
the circuit of Figure 1, the total effective load will be 100
|| 804
= 89
. The disable control line (DIS) is typically left
open to guarantee normal amplifier operation. One optional
component is included in Figure 1. In addition to the usual
power supply de-coupling capacitors to ground, a 0.1
F
capacitor is included between the two power supply pins. In
practical PC board layouts, this optional added capacitor
will typically improve the 2nd harmonic distortion perfor-
mance by 3dB to 6dB.
Figure 2 shows the AC-coupled, gain of +2, single supply
circuit configuration used as the basis of the +5V Specifica-
tions and Typical Performance Curves. Though not a "rail-
to-rail" design, the OPA681 requires minimal input and
output voltage headroom compared to other very wideband
current feedback op amps. It will deliver a 3Vp-p output
swing on a single +5V supply with greater than 150MHz
bandwidth. The key requirement of broadband single supply
operation is to maintain input and output signal swings
within the usable voltage ranges at both the input and the
output. The circuit of Figure 2 establishes an input midpoint
bias using a simple resistive divider from the +5V supply
(two 806
resistors). The input signal is then AC coupled
into this midpoint voltage bias. The input voltage can swing
to within 1.5V of either supply pin, giving a 2Vp-p input
signal range centered between the supply pins. The input
impedance matching resistor (57.6
) used for testing is
adjusted to give a 50
input match when the parallel
combination of the biasing divider network is included. The
gain resistor (R
G
) is AC-coupled, giving the circuit a DC
gain of +1--which puts the input DC bias voltage (2.5V) on
the output as well. The feedback resistor value has been
adjusted from the bipolar supply condition to re-optimize for
a flat frequency response in +5V, gain of +2, operation (see
Setting Resistor Values to Optimize Bandwidth). Again, on
a single +5V supply, the output voltage can swing to within
1V of either supply pin while delivering more than 80mA
output current. A demanding 100
load to a midpoint bias
is used in this characterization circuit. The new output stage
used in the OPA681 can deliver large bipolar output currents
into this midpoint load with minimal crossover distortion, as
shown by the +5V supply, 3rd harmonic distortion plots.
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifi-
cation and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single Supply Specifica-
tion and Test Circuit.
OPA681
+5V
+
DIS
5V
V
S
+V
S
50
Load
50
50
V
O
V
I
50
Source
R
G
402
R
F
402
+
6.8F
0.1F
6.8F
0.1F
0.1F
OPA681
+5V
DIS
V
S
/2
806
100
V
O
V
I
+V
S
57.6
806
R
F
499
R
G
499
0.1F
0.1F
6.8F
+
0.1F
OPA681
12
SBOS084A
SINGLE-SUPPLY A/D CONVERTER INTERFACE
Most modern, high performance A/D converters (such as the
Texas Instruments ADS8xx and ADS9xx series) operate on
a single +5V (or lower) power supply. It has been a consid-
erable challenge for single-supply op amps to deliver a low
distortion input signal at the ADC input for signal frequen-
cies exceeding 5MHz. The high slew rate, exceptional out-
put swing and high linearity of the OPA681 make it an ideal
single-supply ADC driver. Figure 3 shows an example input
interface to a very high performance 10-bit, 60MSPS CMOS
converter.
The OPA681 in the circuit of Figure 3 provides > 180MHz
bandwidth operating at a signal gain of +4 with a 2Vp-p
output swing. One of the primary advantages of the current
feedback internal architecture used in the OPA681 is that
high bandwidth can be maintained as the signal gain is
increased. The non-inverting input bias voltage is referenced
to the mid-point of the ADC signal range by dividing off the
top and bottom of the internal ADC reference ladder. With
the gain resistor (R
G
) AC-coupled, this bias voltage has a
gain of +1 to the output, centering the output voltage swing
as well. Tested performance at a 20MHz analog input
frequency and a 60MSPS clock rate on the converter gives
> 58dBc SFDR.
WIDEBAND INVERTING SUMMING AMPLIFIER
Since the signal bandwidth for a current feedback op amp
may be controlled independently of the noise gain (NG,
which is normally the same as the non-inverting signal gain),
very broadband inverting summing stages may be imple-
mented using the OPA681. The circuit on the front page of
this data sheet shows an example inverting summing ampli-
fier where the resistor values have been adjusted to maintain
both maximum bandwidth and input impedance matching. If
each RF signal is assumed to be driven from a 50
source,
the NG for this circuit will be (1 + 100
/(100
/5)) = 6. The
total feedback impedance (from V
O
to the inverting error
current) is the sum of R
F
+ (R
I
x
NG) where R
I
is the
impedance looking into the inverting input from the sum-
ming junction (see Setting Resistor Values to Optimize
Performance section). Using 100
feedback (to get a signal
gain of 2 from each input to the output pin) requires an
additional 20
in series with the inverting input to increase
the feedback impedance. With this resistor added to the
typical internal R
I
= 41
, the total feedback impedance is
100
+ (65
x
6) = 490
, which is equal to the required
value to get a maximum bandwidth flat frequency response
for NG = 6. Tested performance shows more than 200MHz
small signal bandwidth and a 1dBm compression of 15dBm
at the matched 50
load through 100MHz.
WIDEBAND VIDEO MULTIPLEXING
One common application for video speed amplifiers which
include a disable pin is to wire multiple amplifier outputs
together, then select which one of several possible video
inputs to source onto a single line. This simple "Wired-OR
Video Multiplexer" can be easily implemented using the
OPA681 as shown in Figure 4.
Typically, channel switching is performed either on sync or
retrace time in the video signal. The two inputs are approxi-
mately equal at this time. The "make-before-break" disable
characteristic of the OPA681 ensures that there is always
one amplifier controlling the line when using a wired-OR
circuit like that shown in Figure 4. Since both inputs may be
on for a short period during the transition between channels,
the outputs are combined through the output impedance
matching resistors (82.5
in this case). When one channel is
disabled, its feedback network forms part of the output
impedance and slightly attenuates the signal in getting out
onto the cable. The gain and output matching resistor have
been slightly increased to get a signal gain of +1 at the
matched load and provide a 75
output impedance to the
cable. The video multiplexer connection (Figure 4) also
insures that the maximum differential voltage across the
inputs of the unselected channel do not exceed the rated
1.2V maximum for standard video signal levels.
FIGURE 3. Wideband, AC-Coupled, Single-Supply A/D Driver.
OPA681
360
+2.5V DC Bias
ADS823
10-Bit
60MSPS
50
2Vp-p
DIS
22pF
Input
120
REFB
REFT
CM
Input
0.1
F
0.1
F
0.5Vp-p
2k
0.1
F
+3.5V
2k
0.1
F
+1.5V
+5V
Clock
+5V
R
G
R
F
13
OPA681
SBOS084A
FIGURE 4. Two-Channel Video Multiplexer.
The section on Disable Operation shows the turn-on and
turn-off switching glitches using a grounded input for a
single channel is typically less than
50mV. Where two
outputs are switched (as shown in Figure 6), the output line
is always under the control of one amplifier or the other due
to the "make-before-break" disable timing. In this case, the
switching glitches for two 0V inputs drop to <20mV.
SINGLE-SUPPLY "IF" AMPLIFIER
The high bandwidth provided by the OPA681 while operat-
ing on a single +5V supply lends itself well to IF amplifier
applications. One of the advantages of using an op amp like
the OPA681 as an IF amplifier is that precise signal gain is
achieved along with much lower 3rd-order intermodulation
versus quiescent power dissipation. In addition, the OPA681
in the SOT23-6 package offers a very small package with a
power shutdown feature for portable applications. One con-
cern with using op amps for an IF amplifier is their relatively
high noise figures. It is sometimes suggested that an opti-
mum source resistance can be used to minimize op amp
noise figure. Adding a resistor to reach this optimum value
may improve noise figure, but will actually decrease the
signal-to-noise ratio. A more effective way to move towards
an optimum source impedance is to bring the signal in
through an input transformer. Figure 5 shows an example
that is particularly useful for the OPA681.
FIGURE 5. Low Noise, Single Supply, IF Amplifier.
R
F
600
V
O
= 3V/V (9.54dB)
V
I
R
G
200
OPA681
+5V
DIS
Power Supply
de-coupling not shown
V
I
V
O
50
Load
50
50
Source
1:2
5k
5k
1F
0.1F
Bringing the signal in through a step up transformer to the
inverting input gain resistor has several advantages for the
OPA681. First, the decoupling capacitor on the non-invert-
ing input eliminates the contribution of the non-inverting
input current noise to the output noise. Secondly, the non-
inverting input noise voltage of the op amp is actually
OPA681
2k
82.5
75
Cable
RG-59
82.5
75
402
340
Video 1
+5V
+5V
5V
OPA681
2k
75
402
340
Video 2
5V
+5V
V
DIS
DIS
DIS
OPA681
14
SBOS084A
attenuated if reflected to the input side of R
G
. Using the 1:2
(turns ratio) step-up transformer reflects the 50
source imped-
ance at the primary through to the secondary as a 200
source
impedance (and the 200
R
G
resistor is reflected through to the
transformer primary as a 50
input matching impedance). The
noise gain (NG) to the amplifier output is then 1+ 600/400 =
2.5V/V. Taking the op amp's 2.2nV/
Hz input voltage noise
times this noise gain to the output, then reflecting this noise
term to the input side of the R
G
resistor, divides it by 3. This
gives a net gain of 0.833 for the non-inverting input voltage
noise when reflected to the input point for the op amp circuit.
This is further reduced when referred back to the transformer
primary.
The relatively low gain IF amplifier circuit of Figure 5 gives a
12dB noise figure at the input of the transformer. Increasing the
R
F
resistor to 600
(once R
G
is set to 200
for input impedance
matching) will slightly reduce the bandwidth. Measured results
show 150MHz small-signal bandwidth for the circuit of Figure
5 with exceptional flatness through 30MHz. Although the
OPA681 does not show an intercept characteristic for the
2-tone, 3rd-order intermodulation distortion, it does hold a very
high spurious free dynamic range through high output powers
and frequencies. The maximum single-tone power at the match-
ed load for the single-supply circuit of Figure 5 is 1dBm (this
requires a 2.8Vp-p swing at the output pin of the OPA681 for
the 2-tone envelope). Measured 2-tone SFDR at this maximum
load power for the circuit of Figure 5 exceeds 55dBc for
frequencies to 30MHz.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial
evaluation of circuit performance using the OPA681 in its
three package styles. All of these are available free as an
unpopulated PC board delivered with descriptive documen-
tation. The summary information for these boards is shown
in the table below.
TI Applications department (1-800-548-6132). The Appli-
cations department is also available for design assistance at
this number. These models do a good job of predicting
small-signal AC and transient performance under a wide
variety of operating conditions. They do not do as well in
predicting the harmonic distortion or dG/d
characteristics.
These models do not attempt to distinguish between the
package types in their small-signal AC performance.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO
OPTIMIZE BANDWIDTH
A current feedback op amp like the OPA681 can hold an almost
constant bandwidth over signal gain settings with the proper
adjustment of the external resistor values. This is shown in the
Typical Performance Curves; the small-signal bandwidth de-
creases only slightly with increasing gain. Those curves also
show that the feedback resistor has been changed for each gain
setting. The resistor "values" on the inverting side of the circuit
for a current feedback op amp can be treated as frequency
response compensation elements while their "ratios" set the
signal gain. Figure 6 shows the small-signal frequency response
analysis circuit for the OPA681.
FIGURE 6. Current Feedback Transfer Function Analysis
Circuit.
R
F
V
O
R
G
R
I
Z
(S)
i
ERR
i
ERR
V
I
BOARD
LITERATURE
PART
REQUEST
PRODUCT
PACKAGE
NUMBER
NUMBER
OPA681P
8-Pin DIP
DEM-OPA68xP
MKT-350
OPA681U
8-Pin SO-8
DEM-OPA68xU
MKT-351
OPA681N
6-Lead SOT23-6
DEM-OPA68xN
MKT-348
Contact the TI applications support line to request any of
these boards.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA681 is available through either the
TI web site (www.ti.com) or as one model on a disk from the
The key elements of this current feedback op amp model are:
Buffer gain from the non-inverting input to the inverting input
R
I
Buffer output impedance
i
ERR
Feedback error current signal
Z(s)
Frequency dependent open loop transimpedance gain from i
ERR
to V
O
The buffer gain is typically very close to 1.00 and is
normally neglected from signal gain considerations. It will,
however, set the CMRR for a single op amp differential
amplifier configuration. For a buffer gain
< 1.0, the
CMRR = 20
x
log (1
) dB.
R
I
, the buffer output impedance, is a critical portion of the
bandwidth control equation. The OPA681 is typically about
41
.
15
OPA681
SBOS084A
A current feedback op amp senses an error current in the
inverting node (as opposed to a differential input error
voltage for a voltage feedback op amp) and passes this on to
the output through an internal frequency dependent
transimpedance gain. The Typical Performance Curves show
this open-loop transimpedance response. This is analogous
to the open-loop voltage gain curve for a voltage feedback
op amp. Developing the transfer function for the circuit of
Figure 6 gives Equation 1:
This is written in a loop gain analysis format where the
errors arising from a non-infinite open-loop gain are shown
in the denominator. If Z(s) were infinite over all frequencies,
the denominator of Equation 1 would reduce to 1 and the
ideal desired signal gain shown in the numerator would be
achieved. The fraction in the denominator of Equation 1
determines the frequency response. Equation 2 shows this as
the loop gain equation:
If 20
x
log (R
F
+ NG
x
R
I
) were drawn on top of the open-
loop transimpedance plot, the difference between the two
would be the loop gain at a given frequency. Eventually,
Z(s) rolls off to equal the denominator of Equation 2 at
which point the loop gain has reduced to 1 (and the curves
have intersected). This point of equality is where the
amplifier's closed-loop frequency response given by Equa-
tion 1 will start to roll off, and is exactly analogous to the
frequency at which the noise gain equals the open-loop
voltage gain for a voltage feedback op amp. The difference
here is that the total impedance in the denominator of
Equation 2 may be controlled somewhat separately from the
desired signal gain (or NG).
The OPA681 is internally compensated to give a maximally
flat frequency response for R
F
= 402
at NG = 2 on
5V
supplies. Evaluating the denominator of Equation 2 (which
is the feedback transimpedance) gives an optimal target of
484
. As the signal gain changes, the contribution of the
NG
x
R
I
term in the feedback transimpedance will change,
but the total can be held constant by adjusting R
F
. Equation
3 gives an approximate equation for optimum R
F
over signal
gain:
Eq. 3
As the desired signal gain increases, this equation will
eventually predict a negative R
F
. A somewhat subjective
limit to this adjustment can also be set by holding R
G
to a
minimum value of 20
. Lower values will load both the
buffer stage at the input and the output stage if R
F
gets too
low--actually decreasing the bandwidth. Figure 7 shows the
recommended R
F
vs NG for both
5V and a single +5V
operation. The values for R
F
versus gain shown here are
approximately equal to the values used to generate the
Typical Performance Curves. They differ in that the opti-
mized values used in the Typical Performance Curves are
also correcting for board parasitics not considered in the
simplified analysis leading to Equation 3. The values shown
in Figure 7 give a good starting point for design where
bandwidth optimization is desired.
Z
(S)
R
F
+
R
I
NG
=
Loop Gain
Eq. 2
V
O
V
I
=
1
+
R
F
R
G
1
+
R
F
+
R
I
1
+
R
F
R
G
Z
(S)
=
NG
1
+
R
F
+
R
I
NG
Z
(S)
Eq. 1
NG
=
1
+
R
F
R
G
FIGURE 7. Recommended Feedback Resistor vs Noise Gain.
600
500
400
300
200
100
0
Noise Gain
0
20
10
15
5
FEEDBACK RESISTOR vs NOISE GAIN
Feedback Resistor (
)
+5V
5V
The total impedance going into the inverting input may be
used to adjust the closed-loop signal bandwidth. Inserting a
series resistor between the inverting input and the summing
junction will increase the feedback impedance (denominator
of Equation 2), decreasing the bandwidth. This approach to
bandwidth control is used for the inverting summing circuit
on the front page. The internal buffer output impedance for
the OPA681 is slightly influenced by the source impedance
looking out of the non-inverting input terminal. High source
resistors will have the effect of increasing R
I
, decreasing the
bandwidth. For those single-supply applications which de-
velop a midpoint bias at the non-inverting input through
high valued resistors, the decoupling capacitor is essential
for power supply noise rejection, non-inverting input noise
current shunting, and to minimize the high frequency value
for R
I
in Figure 6.
INVERTING AMPLIFIER OPERATION
Since the OPA681 is a general purpose, wideband current
feedback op amp, most of the familiar op amp application
circuits are available to the designer. Those applications that
require considerable flexibility in the feedback element
(e.g., integrators, transimpedance, some filters) should con-
R
NG R
F
I
=
484
OPA681
16
SBOS084A
sider the unity gain stable voltage feedback OPA680, since
the feedback resistor is the compensation element for a
current feedback op amp. Wideband inverting operation
(and especially summing) is particularly suited to the
OPA681. Figure 8 shows a typical inverting configuration
where the I/O impedances and signal gain from Figure 1 are
retained in an inverting circuit configuration.
ground on the non-inverting input to achieve bias current
error cancellation at the output. The input bias currents for
a current feedback op amp are not generally matched in
either magnitude or polarity. Connecting a resistor to ground
on the non-inverting input of the OPA681 in the circuit of
Figure 8 will actually provide additional gain for that input's
bias and noise currents, but will not decrease the output DC
error since the input bias currents are not matched.
OUTPUT CURRENT AND VOLTAGE
The OPA681 provides output voltage and current capabili-
ties that are unsurpassed in a low cost monolithic op amp.
Under no-load conditions at 25
C, the output voltage typi-
cally swings closer than 1V to either supply rail; the guaran-
teed swing limit is within 1.2V of either rail. Into a 15
load
(the minimum tested load), it is guaranteed to deliver more
than
135mA.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage
x
current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" plot in the Typi-
cal Performance Curves. The X and Y axes of this graph
show the zero-voltage output current limit and the zero-
current output voltage limit, respectively. The four quad-
rants give a more detailed view of the OPA681's output
drive capabilities, noting that the graph is bounded by a
"Safe Operating Area" of 1W maximum internal power
dissipation. Superimposing resistor load lines onto the plot
shows that the OPA681 can drive
2.5V into 25
or
3.5V
into 50
without exceeding the output capabilities or the
1W dissipation limit. A 100
load line (the standard test
circuit load) shows the full
3.9V output swing capability,
as shown in the Typical Specifications.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
V
BE
's (increasing the available output voltage swing) and
increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem since most applications include a series match-
ing resistor at the output that will limit the internal power
dissipation if the output side of this resistor is shorted to
ground. However, shorting the output pin directly to the
adjacent positive power supply pin (8-pin packages) will, in
most cases, destroy the amplifier. If additional short-circuit
protection is required, consider a small series resistor in the
power supply leads. This will, under heavy output loads,
FIGURE 8. Inverting Gain of 2 with Impedance Matching.
OPA681
R
F
365
R
G
182
DIS
+5V
5V
50
50
Load
V
O
Power supply
de-coupling
not shown
V
I
50
Source
R
M
68.1
In the inverting configuration, two key design consider-
ations must be noted. The first is that the gain resistor (R
G
)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted pair, long
PC board trace or other transmission line conductor), it is
normally necessary to add an additional matching resistor to
ground. R
G
by itself is normally not set to the required input
impedance since its value, along with the desired gain, will
determine an R
F
which may be non-optimal from a fre-
quency response standpoint. The total input impedance for
the source becomes the parallel combination of R
G
and R
M
.
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes part
of the noise gain equation and will have slight effect on the
bandwidth through Equation 1. The values shown in Figure
8 have accounted for this by slightly decreasing R
F
(from
Figure 1) to re-optimize the bandwidth for the noise gain of
Figure 8 (NG = 2.74) In the example of Figure 8, the R
M
value combines in parallel with the external 50
source
impedance, yielding an effective driving impedance of
50
|| 68
= 28.8
. This impedance is added in series with
R
G
for calculating the noise gain--which gives NG = 2.74.
This value, along with the R
F
of Figure 8 and the inverting
input impedance of 41
, are inserted into Equation 3 to get
a feedback transimpedance nearly equal to the 484
opti-
mum value.
Note that the non-inverting input in this bipolar supply
inverting application is connected directly to ground. It is
often suggested that an additional resistor be connected to
17
OPA681
SBOS084A
reduce the available output voltage swing. A 5
series
resistor in each power supply lead will limit the internal
power dissipation to less than 1W for an output short circuit
while decreasing the available output voltage swing only
0.5V for up to 100mA desired load currents. Always place
the 0.1
F power supply decoupling capacitors after these
supply current limiting resistors directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter--including
additional external capacitance which may be recommended
to improve A/D linearity. A high speed, high open-loop gain
amplifier like the OPA681 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When
the amplifier's open-loop output resistance is considered,
this capacitive load introduces an additional pole in the
signal path that can decrease the phase margin. Several
external solutions to this problem have been suggested.
When the primary considerations are frequency response
flatness, pulse response fidelity and/or distortion, the sim-
plest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load. This does not eliminate the pole from the loop re-
sponse, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Performance Curves show the recommended
R
S
vs Capacitive Load and the resulting frequency response
at the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA681. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA681 output pin
(see Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA681 provides good distortion performance into a
100
load on
5V supplies. Relative to alternative solu-
tions, it provides exceptional performance into lighter loads
and/or operating on a single +5V supply. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd harmonic will dominate the distortion with a
negligible 3rd harmonic component. Focusing then on the
2nd harmonic, increasing the load impedance improves
distortion directly. Remember that the total load includes the
feedback network--in the non-inverting configuration (Fig-
ure 1) this is the sum of R
F
+ R
G
, while in the inverting
configuration it is just R
F
. Also, providing an additional
supply de-coupling capacitor (0.1
F) between the supply
pins (for bipolar operation) improves the 2nd-order distor-
tion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. The Typical Perfor-
mance Curves show the 2nd harmonic increasing at a little
less than the expected 2X rate while the 3rd harmonic
increases at a little less than the expected 3X rate. Where the
test power doubles, the difference between it and the 2nd
harmonic decreases less than the expected 6dB while the
difference between it and the 3rd decreases by less than the
expected 12dB. This also shows up in the 2-tone, 3rd-order
intermodulation spurious (IM3) response curves. The 3rd-
order spurious levels are extremely low at low output power
levels. The output stage continues to hold them low even as
the fundamental power reaches very high levels. As the
Typical Performance Curves show, the spurious
intermodulation powers do not increase as predicted by a
traditional intercept model. As the fundamental power level
increases, the dynamic range does not decrease significantly.
For two tones centered at 20MHz, with 10dBm/tone into a
matched 50
load (i.e., 2Vp-p for each tone at the load,
which requires 8Vp-p for the overall 2-tone envelope at the
output pin), the Typical Performance Curves show 62dBc
difference between the test-tone power and the 3rd-order
intermodulation spurious levels. This exceptional perfor-
mance improves further when operating at lower frequen-
cies.
NOISE PERFORMANCE
Wideband current feedback op amps generally have a higher
output noise than comparable voltage feedback op amps.
The OPA681 offers an excellent balance between voltage
and current noise terms to achieve low output noise. The
inverting current noise (15pA/
Hz) is significantly lower
than earlier solutions while the input voltage noise
(2.2nV/
Hz) is lower than most unity gain stable, wideband,
voltage feedback op amps. This low input voltage noise was
achieved at the price of higher non-inverting input current
noise (12pA/
Hz). As long as the AC source impedance
looking out of the non-inverting node is less than 100
, this
current noise will not contribute significantly to the total
output noise. The op amp input voltage noise and the two
input current noise terms combine to give low output noise
under a wide variety of operating conditions. Figure 9 shows
the op amp noise analysis model with all the noise terms
FIGURE 9. Op Amp Noise Analysis Model.
4kT
R
G
R
G
R
F
R
S
OPA681
I
BI
E
O
I
BN
4kT = 1.6E 20J
at 290K
E
RS
E
NI
4kTR
S
4kTR
F
OPA681
18
SBOS084A
included. In this model, all noise terms are taken to be
noise voltage or current density terms in either nV/
Hz or
pA/
Hz.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms shown in Figure 9.
Dividing this expression by the noise gain (NG = (1+R
F
/R
G
))
will give the equivalent input-referred spot noise voltage at the
non-inverting input as shown in Equation 5.
Evaluating these two equations for the OPA681 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 8.4nV/
Hz and a total equivalent input
spot noise voltage of 4.2nV/
Hz. This total input-referred
spot noise voltage is higher than the 2.2nV/
Hz specifica-
tion for the op amp voltage noise alone. This reflects the
noise added to the output by the inverting current noise times
the feedback resistor. If the feedback resistor is reduced in
high gain configurations (as suggested previously), the total
input-referred voltage noise given by Equation 5 will ap-
proach just the 2.2nV/
Hz of the op amp itself. For example,
going to a gain of +10 using R
F
= 180
will give a total
input-referred noise of 2.4nV/
Hz .
DC ACCURACY AND OFFSET CONTROL
A current feedback op amp like the OPA681 provides
exceptional bandwidth in high gains, giving fast pulse set-
tling but only moderate DC accuracy. The Typical Specifi-
cations show an input offset voltage comparable to high
speed voltage feedback amplifiers. However, the two input
bias currents are somewhat higher and are unmatched.
Whereas bias current cancellation techniques are very effec-
tive with most voltage feedback op amps, they do not
generally reduce the output DC offset for wideband current
feedback op amps. Since the two input bias currents are
unrelated in both magnitude and polarity, matching the
source impedance looking out of each input to reduce their
error contribution to the output is ineffective. Evaluating the
configuration of Figure 1, using worst-case +25
C input
offset voltage and the two input bias currents, gives a worst-
case output offset range equal to:
(NG
x
V
OS(MAX)
) + (I
BN
x
R
S
/2 x NG)
(I
BI
x
R
F
)
where NG = non-inverting signal gain
=
(2
x
5.0mV) + (55
A
x
25
x
2)
(402
x
40
A)
=
10mV + 2.75mV
16mV
= 23.25mV
+28.25mV
A fine-scale, output offset null, or DC operating point
adjustment, is sometimes required. Numerous techniques
are available for introducing DC offset control into an op
amp circuit. Most simple adjustment techniques do not
correct for temperature drift. It is possible to combine a
lower speed, precision op amp with the OPA681 to get the
DC accuracy of the precision op amp along with the signal
bandwidth of the OPA681. Figure 10 shows a non-inverting
G = +10 circuit that holds an output offset voltage less than
7.5mV over temperature with > 150MHz signal band-
width.
This DC-coupled circuit provides very high signal band-
width using the OPA681. At lower frequencies, the output
voltage is attenuated by the signal gain and compared to the
original input voltage at the inputs of the OPA237 (this is a
low cost, precision voltage feedback op amp with 1.5MHz
gain bandwidth product). If these two don't agree (due to
DC offsets introduced by the OPA681), the OPA237 sums
in a correction current through the 2.86k
inverting sum-
ming path. Several design considerations will allow this
circuit to be optimized. First, the feedback to the OPA237's
non-inverting input must be precisely matched to the high
speed signal gain. Making the 2k
resistor to ground an
adjustable resistor would allow the low and high frequency
gains to be precisely matched. Secondly, the crossover
frequency region where the OPA237 passes control to the
OPA681 must occur with exceptional phase linearity. These
two issues reduce to designing for pole/zero cancellation in
the overall transfer function. Using the 2.86k
resistor will
nominally satisfy this requirement for the circuit in Figure
10. Perfect cancellation over process and temperature is not
possible. However, this initial resistor setting and precise
gain matching will minimize long term pulse settling tails.
DISABLE OPERATION
The OPA681 provides an optional disable feature that may
be used either to reduce system power or to implement a
OPA681
180
2.86k
20
DIS
+5V
5V
V
O
Power supply
de-coupling not shown
OPA237
5V
+5V
V
I
18k
2k
1.8k
FIGURE 10. Wideband, Precision, G = +10 Composite Amplifier.
Eq. 5
E
N
=
E
NI
2
+
I
BN
R
S
(
)
2
+
4kTR
S
+
I
BI
R
F
NG
2
+
4kTR
F
NG
Eq. 4
E
O
=
E
NI
2
+
I
BN
R
S
(
)
2
+
4kTR
S
(
)
NG
2
+
I
BI
R
F
(
)
2
+
4kTR
F
NG
19
OPA681
SBOS084A
simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA681 will operate normally.
To disable, the control pin must be asserted low. Figure 11
shows a simplified internal circuit for the disable control
feature.
In normal operation, base current to Q1 is provided through
the 110k
resistor while the emitter current through the
15k
resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1's emitter. As V
DIS
is pulled
low, additional current is pulled through the 15k
resistor
eventually turning on these two diodes (
100
A). At this
point, any further current pulled out of V
DIS
goes through
those diodes holding the emitter-base voltage of Q1 at
approximately zero volts. This shuts off the collector current
out of Q1, turning the amplifier off. The supply current in
the disable mode are only those required to operate the
circuit of Figure 11. Additional circuitry ensures that turn-on
time occurs faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA681 is operating in a gain of +1,
this will show a very high impedance (4pF || 1M
) at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(R
F
+ R
G
) will appear as the impedance looking back into the
output, but the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (R
F
+ R
G
) giving relatively poor input to
output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 12
shows these glitches for the circuit of Figure 1 with the input
signal set to zero volts. The glitch waveform at the output
pin is plotted along with the DIS pin voltage.
The transition edge rate (dV/dT) of the DIS control line will
influence this glitch. For the plot of Figure 12, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
V
DIS
pin from a higher speed logic line. If extremely fast
transition logic is used, a 2k
series resistor between the
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring an adequate logic level swing.
25k
110k
15k
I
S
Control
V
S
+V
S
V
DIS
Q1
FIGURE 11. Simplified Disable Control Circuit.
40
20
0
20
40
Time (20ns/div)
Output Voltage (20mV/div)
Output Voltage
(0V Input)
V
DIS
0.2V
4.8V
FIGURE 12. Disable/Enable Glitch.
THERMAL ANALYSIS
Due to the high output power capability of the OPA681,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
x
JA
. The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in
the output stage (P
DL
) to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. P
DL
will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition P
DL
= V
S
2
/(4
x
R
L
) where R
L
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA681N (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85
C and driving a grounded 20
load to +2.5V DC:
P
D
= 10V
x
7.2mA + 5
2
/ (4
x
(20
|| 804
)) = 392mW
Maximum T
J
= +85
C + (0.39W (150
C/W) = 144
C
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. Remember,
this is a worst-case internal power dissipation--use your
actual signal and load to compute P
DL
. The highest possible
OPA681
20
SBOS084A
internal dissipation will occur if the load requires current to
be forced into the output for positive output voltages or
sourced from the output for negative output voltages. This
puts a high current through a large internal voltage drop in
the output transistors. The Output Voltage and Current
Limitations plot shown in the Typical Performance Curves
include a boundary for 1W maximum internal power dissi-
pation under these conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA681 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power supply
pins to high frequency 0.1
F decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply decoupling ca-
pacitor across the two power supplies (for bipolar operation)
will improve 2nd harmonic distortion performance. Larger
(2.2
F to 6.8
F) decoupling capacitors, effective at lower
frequency, should also be used on the main supply pins.
These may be placed somewhat farther from the device and
may be shared among several devices in the same area of the
PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA681. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter over-
all layout. Metal-film and carbon composition, axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads and PC board trace length as short as
possible. Never use wirewound type resistors in a high
frequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as non-inverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. The
frequency response is primarily determined by the feedback
resistor value as described previously. Increasing its value
will reduce the bandwidth, while decreasing it will give a
more peaked frequency response. The 402
feedback resis-
tor used in the typical performance specifications at a gain
of +2 on
5V supplies is a good starting point for design.
Note that a 453
feedback resistor, rather than a direct short,
is recommended for the unity gain follower application. A
current feedback op amp requires a feedback resistor even in
the unity gain follower configuration to control stability.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
S
from the
plot of recommended R
S
versus Capacitive Load. Low
parasitic capacitive loads (< 5pF) may not need an R
S
since
the OPA681 is nominally compensated to operate with a 2pF
parasitic load. If a long trace is required, and the 6dB signal
loss intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance transmission
line using microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout tech-
niques). A 50
environment is normally not necessary on
board, and in fact, a higher impedance environment will
improve distortion as shown in the Distortion vs Load plots.
With a characteristic board trace impedance defined based
on board material and trace dimensions, a matching series
resistor into the trace from the output of the OPA681 is used
as well as a terminating shunt resistor at the input of the
destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device:
this total effective impedance should be set to match the
trace impedance. The high output voltage and current capa-
bility of the OPA681 allows multiple destination devices to
be handled as separate transmission lines, each with their
own series and shunt terminations. If the 6dB attenuation of
a doubly-terminated transmission line is unacceptable, a
long trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the plot of R
S
vs Capacitive
Load. This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the desti-
nation device is low, there will be some signal attenuation
due to the voltage divider formed by the series output into
the terminating impedance.
e) Socketing a high speed part like the OPA681 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA681
onto the board. If socketing for the DIP package is desired,
high frequency flush-mount pins (e.g., McKenzie Technol-
ogy #710C) can give good results.
21
OPA681
SBOS084A
INPUT AND ESD PROTECTION
The OPA681 is built using a very high speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry de-
vices. These breakdowns are reflected in the Absolute Maxi-
mum Ratings table. All device pins have limited ESD
protection using internal diodes to the power supplies as
shown in Figure 13.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with
15V supply
parts driving into the OPA681), current-limiting series resis-
tors should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
External
Pin
+V
CC
V
CC
Internal
Circuitry
FIGURE 13. Internal ESD Protection.
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA681N/250
OBSOLETE
SOP
DBV
6
OPA681N/3K
OBSOLETE
SOP
DBV
6
OPA681P
OBSOLETE
PDIP
P
8
OPA681U
OBSOLETE
SOIC
D
8
OPA681U/2K5
OBSOLETE
SOIC
D
8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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