PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

DESCRIPTION

The OPA695 is a very high bandwidth, current-feedback op
amp that combines exceptional 4300V/

s slew rate and low

input voltage noise to deliver a precision low cost, high
dynamic range Intermediate Frequency (IF) amplifier. Opti-
mized for high gain operation, the OPA695 is ideally suited to
buffering Surface Acoustic Wave (SAW) filters in an IF strip
or delivering high output power at low distortion for cable
modem upstream line drivers. Even higher bandwidth at
lower gains gives a 1400MHz video line driver for high
resolution RGB.

FEATURES

GAIN = +2 BANDWIDTH (1400MHz)

GAIN = +8 BANDWIDTH (450MHz)

OUTPUT VOLTAGE SWING:

4.2V

ULTRA-HIGH SLEW RATE: 4300V/

3RD-ORDER INTERCEPT: > 40dBm (f < 50MHz)

LOW POWER: 129mW

LOW DISABLED POWER: 0.5mW

APPLICATIONS

VERY WIDEBAND ADC DRIVER

LOW-COST PRECISION IF AMPLIFIER

BROADBAND VIDEO LINE DRIVER

PORTABLE INSTRUMENTS

ACTIVE FILTERS

ARB WAVEFORM OUTPUT DRIVER

OPA685 PERFORMANCE UPGRADE

OPA695 RELATED PRODUCTS

SINGLES

DUALS

OPA658

OPA2658

OPA691

OPA2691

OPA692

THS3202

OPA693

The OPA695's low 12.9mA supply current is precisely
trimmed at +25

C. This trim, along with a low temperature

drift, gives low system power over temperature. System
power may be further reduced using the optional disable
control pin. Leaving this pin open, or holding it HIGH, gives
normal operation. If pulled LOW, the OPA695 supply current
drops to less than 170

A. This power-saving feature, along

with exceptional single +5V operation and ultra-small
SOT23-6 packaging, make the OPA695 ideal for portable
applications.

OPA6

OPA695

SBOS293B DECEMBER 2003 REVISED MARCH 2004

www.ti.com

Ultra-Wideband, Current-Feedback

OPERATIONAL AMPLIFIER With Disable

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

OPA695

+5V

511

LOAD

RG-59

511

Gain 2V/V Video Line Driver

1.2

0.8

0.6

0.4

0.2

Time (1ns/div)

GAIN OF +2V/V VIDEO LINE DRIVER

PULSE RESPONSE

Input/Load Voltage (V)

Voltage at
Matched Load

125MHz Input

OPA695

SBOS293B

www.ti.com

SPECIFIED

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

DESIGNATOR

(1)

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

OPA695

SO-8

C to +85

OPA695

OPA695ID

Rails, 100

OPA695IDR

Tape and Reel, 2500

OPA695

SOT23-6

(2)

DBV

C to +85

A71L

OPA695IDBVT

Tape and Reel, 250

OPA695IDBVR

Tape and Reel, 3000

ABSOLUTE MAXIMUM RATINGS

(1)

Power Supply ...............................................................................

6.5V

Internal Power Dissipation ..................................... See Thermal Analysis
Differential Input Voltage ..................................................................

1.2V

Input Common-Mode Voltage Range .................................................

Storage Temperature Range: D, DBV ........................... 40

C to +125

Lead Temperature (soldering, 10s) .............................................. +300

Junction Temperature (T

) ........................................................... +150

ESD Rating
Human Body Model (HBM)

(2)

.......................................................... 1500V

Charge Device Model (CDM) .......................................................... 1000V
Machine Model (MM) ......................................................................... 100V

NOTES: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.

(2) Pin 2 on SO-8 package and pin 4 on SOT23-6 package > 500V

HBM.

PIN CONFIGURATIONS

Top View

NC = No Connection

Top View

SOT23-6

Inverting Input

Noninverting Input

DIS

Output

Noninverting Input

DIS

Inverting Input

Pin Orientation/Package Marking

A71L

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

(2) The SOT23-6 is shipped only as a lead-free and

green package. Check TI web site for lead-free availability of other packages.

OPA695

SBOS293B

www.ti.com

ELECTRICAL CHARACTERISTICS: V

Boldface limits are tested at +25

= 402

, R

= 100

, and G = +8

(see Figure 1 for AC performance only), unless otherwise noted.

OPA695ID, IDBV

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (V

= 0.5V

)

G = +1, R

= 523

1700

MHz

typ

G = +2, R

= 511

1400

MHz

typ

G = +8, R

= 402

450

400

380

350

MHz

min

G = +16, R

= 249

350

MHz

typ

Bandwidth for 0.2dB Gain Flatness

G = +2, V

= 0.5V

, R

=523

320

MHz

min

Peaking at a Gain of +1

= 523

, V

= 0.5V

4.6

5.4

5.8

6.0

max

Large-Signal Bandwidth

G = +8, V

= 4V

450

MHz

typ

Slew Rate

G = 8, V

= 4V Step

4300

3700

3600

3500

min

G = +8, V

= 4V Step

2900

2600

2500

2400

min

Rise-and-Fall Time

G = +8, V

= 0.5V Step

0.8

typ

G = +8, V

= 4V Step

1.0

typ

Settling Time to 0.02%

G = +8, V

= 2V Step

typ

0.1%

G = +8, V

= 2V Step

typ

Harmonic Distortion

G = +8, f = 10MHz, V

= 2V

2nd-Harmonic

= 100

dBc

max

500

dBc

max

3rd-Harmonic

= 100

dBc

max

500

dBc

max

Input Voltage Noise

f > 1MHz

1.8

2.7

2.9

nV/

max

Noninverting Input Current Noise

f > 1MHz

pA/

max

Inverting Input Current Noise

f > 1MHz

pA/

max

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.04

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.007

deg

typ

DC PERFORMANCE

(4)

Open-Loop Transimpedance Gain (Z

)

= 0V, R

= 100

min

Input Offset Voltage

= 0V

0.3

3.0

3.5

4.0

max

Average Offset Voltage Drift

= 0V

max

Noninverting Input Bias Current

= 0V

+13

max

Average Noninverting Input Bias Current Drift

= 0V

+150

+180

nA/

max

Inverting Input Bias Current

= 0V

max

Average Inverting Input Bias Current Drift

= 0V

120

160

max

INPUT
Common-Mode Input Range

(5)

(CMIR)

3.3

3.1

3.0

min

Common-Mode Rejection Ratio (CMRR)

= 0V

min

Noninverting Input Impedance

280 || 1.2

|| pF

typ

Inverting Input Resistance (R

)

Open-Loop

typ

OUTPUT
Voltage Output Swing

No Load

4.2

4.0

3.9

min

100

Load

3.9

3.7

3.7

3.6

min

Current Output, Sourcing

= 0

+120

+90

+80

+70

min

Current Output, Sinking

= 0

120

90

min

Closed-Loop Output Impedance

G = +8, f = 100kHz

0.04

typ

DISABLE (Disabled LOW)
Power-Down Supply Current (+V

)

DIS

= 0

100

170

186

192

typ

Disable Time

0.25V

typ

Enable Time

0.25V

typ

Off Isolation

G = +8, 10MHz

typ

Output Capacitance in Disable

typ

Turn On Glitch

G = +2, R

= 150

, V

= 0

100

typ

Turn Off Glitch

G = +2, R

= 150

, V

= 0

typ

Enable Voltage

3.3

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current (DIS)

DIS

= 0

130

143

145

max

POWER SUPPLY
Specified Operating Voltage

typ

Maximum Operating Voltage Range

max

Max Quiescent Current

12.9

13.3

13.7

14.1

max

Min Quiescent Current

12.9

12.6

11.8

11.0

min

Power-Supply Rejection Ratio (PSRR)

Input Referred

typ

TEMPERATURE RANGE
Specification: ID, IDBV

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

DBV

SOT23-6

150

C/W

typ

NOTES: (1) Junction temperature = ambient for +25

C specifications.

(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +15

C at high temperature limit for over temperature

specifications.

(3) Test levels: (A) 100% tested at +25

C. Over temperature limits by characterization and simulation.

(B) Limits set by characterization and simulation. (C) Typical value only for information.

(4) Current is considered positive out-of-node. V

is the input common-mode voltage.

(5) Tested < 3dB below minimum specified CMRR at

CMIR limits.

OPA695

SBOS293B

www.ti.com

OPA695ID, IDBV

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

ELECTRICAL CHARACTERISTICS: V

= +5V

Boldface limits are tested at +25

= 348

, R

= 100

to V

/2, and G = +8

(see Figure 3 for AC performance only), unless otherwise noted.

AC PERFORMANCE (see Figure 3)
Small-Signal Bandwidth (V

= 0.5V

)

G = +1, R

= 511

1400

MHz

typ

G = +2, R

= 487

960

MHz

min

G = +8, R

= 348

395

380

330

300

MHz

typ

G = +16, R

= 162

235

MHz

typ

Bandwidth for 0.2dB Gain Flatness

G = +2, V

< 0.5V

, R

= 487

230

180

135

110

MHz

min

Peaking at a Gain of +1

= 511

, V

< 0.5V

1.0

2.0

2.5

3.0

max

Large-Signal Bandwidth

G = +8, V

= 2V

310

MHz

typ

Slew Rate

G = +8, 2V Step

1700

1300

1200

1100

min

Rise-and-Fall Time

G = +8, V

= 0.5V Step

1.0

typ

G = +8, V

= 2V Step

1.0

typ

Settling Time to 0.02%

G = +8, V

= 2V Step

typ

0.1%

G = +8, V

= 2V Step

typ

Harmonic Distortion

G = +8, f = 10MHz, V

= 2V

2nd-Harmonic

= 100

to V

dBc

max

500

to V

dBc

max

3rd-Harmonic

= 100

to V

dBc

max

500

to V

dBc

max

Input Voltage Noise

f > 1MHz

1.8

2.7

2.9

nV/

max

Noninverting Input Current Noise

f > 1MHz

pA/

max

Inverting Input Current Noise

f > 1MHz

pA/

max

DC PERFORMANCE

(4)

Open-Loop Transimpedance Gain (Z

)

= V

/2, R

= 100

to V

min

Input Offset Voltage

= V

0.3

3.5

4.0

max

Average Offset Voltage Drift

= V

max

Noninverting Input Bias Current

= V

max

Average Noninverting Input Bias Current Drift

= V

110

170

nA/

max

Inverting Input Bias Current

= V

max

Average Inverting Input Bias Current Drift

= V

120

160

nA /

max

INPUT
Least Positive Input Voltage

(5)

1.7

1.8

1.9

max

Most Positive Input Voltage

(5)

3.3

3.2

3.1

min

Common-Mode Rejection Ratio (CMRR)

= V

min

Noninverting Input Impedance

280 || 1.2

|| pF

typ

Inverting Input Resistance (R

)

Open-Loop

typ

OUTPUT
Most Positive Output Voltage

No Load

4.2

4.0

3.9

3.8

min

= 100

to V

4.0

3.9

3.8

3.7

min

Least Positive Output Voltage

No Load

0.8

1.0

1.1

1.2

max

= 100

to V

1.0

1.1

1.2

1.3

max

Current Output, Sourcing

= V

min

Current Output, Sinking

= V

70

min

Closed-Loop Output Impedance

G = +2, f = 100kHz

0.05

typ

DISABLE (Disabled LOW)
Power Down Supply Current (+V

)

DIS

= 0

160

175

180

typ

Disable Time

typ

Enable Time

typ

Off Isolation

G = +8, 10MHz

typ

Output Capacitance in Disable

typ

Turn On Glitch

G = +2, R

= 150

, V

= V

100

typ

Turn Off Glitch

G = +2, R

= 150

, V

= V

typ

Enable Voltage

3.3

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current (DIS)

DIS

= 0

130

143

149

typ

POWER SUPPLY
Specified Single-Supply Operating Voltage

typ

Max Single-Supply Operating Voltage

max

Max Quiescent Current

= +5V

11.4

12.0

12.5

12.9

max

Min Quiescent Current

= +5V

11.4

10.9

9.4

9.1

min

Power-Supply Rejection Ratio (PSRR)

Input Referred

typ

TEMPERATURE RANGE
Specification: ID, IDBV

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

DBV

SOT23-6

150

C/W

typ

NOTES: (1) Junction temperature = ambient for +25

C specifications.

(2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +15

C at high temperature limit for over temperature

specifications.

(3) Test levels: (A) 100% tested at +25

C. Over temperature limits by characterization and simulation.

(B) Limits set by characterization and simulation. (C) Typical value only for information.

(4) Current is considered positive out-of-node. V

is the input common-mode voltage.

(5) Tested < 3dB below minimum specified CMRR at

CMIR limits.

OPA695

SBOS293B

www.ti.com

TYPICAL CHARACTERISTICS: V

G = +8, R

= 402

, R

= 100

unless otherwise noted.

Frequency (MHz)

200

400

1400

1200

1000

600

800

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (3dB/div)

G = +16, R

= 249

G = +8, R

= 402

See Figure 1

G = +2, R

= 523

= 500mV

G = +4, R

= 480

Frequency (MHz)

200

400

1400

1200

1000

600

800

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (3dB/div)

G = 8, R

= 442

G = 4,

= 475

See Figure 2

G = 2, R

= 499

= 500mV

G = 16, R

= 806

Frequency (100MHz/div)

1GHz

500MHz

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Gain (3dB/div)

= 7V

= 4V

G = +8, R

= 402

See Figure 1

= 1V

and 2V

Frequency (100MHz/div)

1GHz

500MHz

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Gain (3dB/div)

= 7V

= 2V

= 1V

= 4V

G = 8, R

= 442

See Figure 2

Time (1ns/div)

NONINVERTING LARGE AND SMALL-SIGNAL

PULSE RESPONSE

Output Voltage

See Figure 1

G = +8, R

= 402

125MHz Square Wave Input

Small-Signal

500mV

Large-Signal

Time (1ns/div)

INVERTING LARGE AND SMALL-SIGNAL

PULSE RESPONSE

Output Voltage

See Figure 2

G = +8, R

= 402

125MHz Square Wave Input

Small-Signal

500mV

Large-Signal

OPA695

SBOS293B

www.ti.com

TYPICAL CHARACTERISTICS: V

G = +8, R

= 402

, R

= 100

unless otherwise noted.

100

10MHz HARMONIC DISTORTION

vs LOAD RESISTANCE

Load Resistance (

)

100

500

Harmonic Distortion (dBc)

2nd-Harmonic

3rd-Harmonic

= 2V

G = 8V/V

See Figure 1

10MHz HARMONIC DISTORTION

vs SUPPLY VOLTAGE

Supply Voltage (

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Harmonic Distortion (dBc)

See Figure 1

= 2V

, G = 8V/V

= 100

2nd-Harmonic

3rd-Harmonic

100

HARMONIC DISTORTION vs FREQUENCY

Frequency (MHz)

0.5

100

Harmonic Distortion (dBc)

See Figure 1

= 2V

, G = +8V/V

= 100

2nd-Harmonic

3rd-Harmonic

100

10MHz HARMONIC DISTORTION

vs OUTPUT VOLTAGE

Output Voltage (V

)

0.1

Harmonic Distortion (dBc)

See Figure 1

G = +8V/V
R

= 100

2nd-Harmonic

3rd-Harmonic

10MHz HARMONIC DISTORTION

vs NONINVERTING GAIN

Noninverting Gain (V/V)

Harmonic Distortion (dBc)

See Figure 1

= 2V

= 100

2nd-Harmonic

3rd-Harmonic

10MHz HARMONIC DISTORTION

vs INVERTING GAIN

Inverting Gain (|V/V|)

Harmonic Distortion (dBc)

See Figure 2

= 2V

, R

= 100

2nd-Harmonic

3rd-Harmonic

OPA695

SBOS293B

www.ti.com

TYPICAL CHARACTERISTICS: V

G = +8, R

= 402

, R

= 100

unless otherwise noted.

100

INPUT VOLTAGE AND CURRENT NOISE DENSITY

Frequency (Hz)

Current Noise (pA/

Hz)

Voltage Noise (nV/

Hz)

Noninverting Input Current Noise

Inverting Input Current Noise

19pA/

22pA/

Input Voltage Noise

1.7nV/

Frequency (MHz)

140 160

240

180 200 220

100 120

TWO-TONE, 3rd-ORDER

INTERMODULATION INTERCEPT

Output Intercept (+dBm)

OPA685

402

56.2

G = 12dB to matched load.

OPA685

402

G = 12dB to matched load.

G = +8

G = 8

Noninverting

Inverting

INPUT RETURN LOSS vs FREQUENCY (S

)

Frequency (Hz)

10M

100M

Return Loss (5dB/div)

G = +8

(see Figure 1)

G = 8

(see Figure 2)

VSWR < 1.2:1

OUTPUT RETURN LOSS vs FREQUENCY (S

)

Frequency (Hz)

10M

100M

Return Loss (5dB/div)

G =

8V/V

Without

Trim Cap

With

Trim Cap

VSWR < 1.2:1

OPA695

2.5pF

Trim Cap

vs CAPACITIVE LOAD

Capacitive Load (pF)

100

(

)

0.5dB Peaking

Allowed

SMALL-SIGNAL FREQUENCY RESPONSE

vs CAPACITIVE LOAD

Frequency (Hz)

10M

100M

Normalized Gain (dB)

OPA695

402

57.4

+5V

load is optional

= 100pF

= 10pF

= 20pF

= 50pF

OPA695

SBOS293B

www.ti.com

TYPICAL CHARACTERISTICS: V

G = +8, R

= 402

, R

= 100

unless otherwise noted.

CMRR AND PSRR vs FREQUENCY

Frequency (Hz)

Rejection Ratio (dB)

PSRR

+PSRR

CMRR

100

120

140

160

180

200

OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE

Frequency (Hz)

Open-Loop T

ransimpedance

Gain (dB

)

Open-Loop Phase (

)

20 log| Z

OUTPUT VOLTAGE AND CURRENT LIMITATIONS

(mA)

250 200

100 50

150

100

150

200

250

(V)

100

Load Line

1 Watt

Internal Power

1 Watt

Internal Power

Load Line

130

120

110

100

125

Ambient Temperature (

Output Current (mA)

Supply Current (mA)

SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

Sourcing Output Current

Supply Current

Sinking Output
Current

Left Scale

Right Scale

Time (50ns/div)

Input/Output V

oltage

NONINVERTING OVERDRIVE RECOVERY

Output

Linear Input Range

Input

See Figure 1

G = +8V/V

Time (50ns/div)

Input/Output V

oltage

INVERTING OVERDRIVE RECOVERY

Output

Linear Input Range

Input

See Figure 2

G = 8V/V

OPA695

SBOS293B

www.ti.com

TYPICAL CHARACTERISTICS: V

G = +8, R

= 402

, R

= 100

unless otherwise noted.

100

Frequency (MHz)

DISABLED FEEDTHROUGH vs FREQUENCY

Gain (dB)

See Figure 1

Forward

Reverse

G = +8V/V

1.0

0.5

1.0

100

125

Ambient Temperature (

TYPICAL DC DRIFT OVER TEMPERATURE

Input Offset Voltage (mV)

Input Bias Currents (

Left Scale

Right Scale

Inverting Input Bias Current

Right Scale

Noninverting Input Bias Current

Input Offset Voltage

2.5

3.0

3.5

4.0

4.5

5.0

6.0

5.5

6.5

2.0

Power Supplies (

) Volts

COMMON-MODE INPUT AND OUTPUT SWING

vs SUPPLY VOLTAGE

Input/Output Swing (

) Volts

Output Voltage Range

Input Voltage Range

Time (500ns/div)

olts

LARGE-SIGNAL DISABLE/ENABLE RESPONSE

See Figure 1

= 0.25V

DIS

Time (1ns/div)

SETTLING TIME

Input/Output Voltage (5mV/div)

Input

Output

G = +8V/V
V

= 2V Step

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

Number of 150

Loads

COMPOSITE VIDEO dG/d

dG/d

(%/

)

, 1k

Pulldown

dG, 1k

Pulldown

OPA695

511

Video
Loads

, optional pulldown

OPA695

SBOS293B

www.ti.com

TYPICAL CHARACTERISTICS: V

5V Differential Operation

= 10, R

= 500

, R

= 800

unless otherwise noted.

= R

|| 2R

1:1

OPA695

500

+5V

OPA695

800

500

+5V

= G

500

Frequency (MHz)

1000

100

DIFFERENTIAL SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (dB)

= 2V

= 5

= 20

= 10

21.0

20.5

20.0

19.5

19.0

18.5

18.0

17.5

17.0

16.5

16.0

Frequency (MHz)

1000

100

LARGE-SIGNAL BANDWIDTH

Gain (dB)

= 10

= 12V

= 16V

= 2V

and 4V

= 8V

100

105

Frequency (MHz)

100

DISTORTION vs FREQUENCY

Harmonic Distortion (dBc)

3rd-Harmonic

= 10V/V

= 2V

2nd-Harmonic

100

105

)

DISTORTION vs V

OUT

Harmonic Distortion (dBc)

= 10V/V

F = 20MHz
R

= 800

2nd-Harmonic

3rd-Harmonic

Center Frequency (MHz)

120

140

160

100

180

200

2-TONE, 3RD-ORDER

INTERMODULATION INTERCEPT

Intercept (dBm)

= 800

= 10

OPA695

SBOS293B

www.ti.com

TYPICAL CHARACTERISTICS: V

= +5V

= +5V, G = +8, R

= 348

, R

= 100

unless otherwise noted.

Frequency (200MHz/div)

1GHz

600

800

400

200

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (3dB/div)

G = +8, R

= 348

G = +16, R

= 162

See Figure 3

G = +4, R

= 450

G = +2, R

= 487

Frequency (200MHz/div)

1GHz

600

800

400

200

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (3dB/div)

G = 8, R

= 422

G = 4, R

= 442

G = 16, R

= 806

= 50

See Figure 4

G = 2V/V, R

= 453

NONINVERTING PULSE RESPONSE

Time (1ns/div)

Output Voltage

4.0

3.5

3.0

2.5

2.0

1.5

1.0

See Figure 3

100MHz, Square Wave Input

G = +8V/V

INVERTING PULSE RESPONSE

Time (1ns/div)

Output Voltage

4.0

3.5

3.0

2.5

2.0

1.5

1.0

See Figure 4

100MHz, Square Wave Input

G = 8V/V

vs CAPACITIVE LOAD

Capacitive Load (pF)

100

(

)

0.5dB Peaking
Allowed

SMALL-SIGNAL FREQUENCY RESPONSE

vs CAPACITIVE LOAD

Frequency (MHz)

100

Normalized Gain (dB)

OPA695

348

+5V

1000pF

load is optional

DIS

1000pF

= 100pF

= 10pF

= 20pF

= 50pF

OPA695

SBOS293B

www.ti.com

FIGURE 1. DC-Coupled, G = +8V/V, Bipolar Supply Speci-

fications and Test Circuit.

FIGURE 2. DC-Coupled, G = 8V/V, Bipolar Supply Speci-

fications and Test Circuit.

APPLICATIONS INFORMATION

WIDEBAND CURRENT FEEDBACK OPERATION

The OPA695 gives a new level of performance in wideband
current feedback op amps. Nearly constant AC performance
over a wide gain range, along with 4300V/

s slew rate, gives

a lower power and cost solution for high-intercept IF amplifier
requirements. While optimized at a gain of +8V/V (12dB to a
matched 50

load) to give 450MHz bandwidth, applications

from gains of 1 to 40 can be supported. As a gain of +2
video line driver, the bandwidth extends to 1.4GHz with
a slew rate to support the highest pixel rates. At gains
above 20, the signal bandwidth starts to decrease, but still
exceeds 180MHz up to a gain of 40V/V (26dB to a matched
50

load). Single +5V supply operation is also supported

with similar bandwidths but reduced output power capability.
For lower speed (< 250MHz) requirements with higher output
powers, consider the OPA691.

Figure 1 shows the DC-coupled, gain of +8V/V, dual power
supply circuit used as the basis of the

5V Specifications and

Typical Characteristic curves. For test purposes, the input
impedance is set to 50

with a resistor to ground and the

output impedance is set to 50

with a series output resistor.

Voltage swings reported in the specifications are taken
directly at the input and output pins while load powers (dBm)
are defined at a matched 50

load. For the circuit of Figure

1, the total effective load will be 100

|| 458

= 82

. The

disable control line (DIS) is typically left open to get normal
amplifier operation. The disable line must be asserted low to
shut off the OPA695. One optional component is included in
Figure 1. In addition to the usual power supply decoupling
capacitors to ground, a 0.01

F capacitor is included between

the two power supply pins. In practical PC board layouts, this
optional added capacitor will typically improve the 2nd-
harmonic distortion performance by 3dB to 6dB for bipolar
supply operation.

Figure 2 shows the DC-coupled, gain of 8V/V, dual power
supply circuit used as the basis of the Inverting Typical
Characteristic curves. Inverting operation offers several per-
formance benefits. Since there is no common mode signal
across the input stage, the slew rate for inverting operation
is higher and the distortion performance is slightly improved.
An additional input resistor, R

, is included in Figure 2 to set

the input impedance equal to 50

. The parallel combination

of R

and R

set the input impedance. Both the non-inverting

and inverting applications of Figures 1 and 2 will benefit from
optimizing the feedback resistor (R

) value for bandwidth

(see the discussion in

Setting Resistor Values to Optimize

Bandwidth). The typical design sequence is to select the R

value for best bandwidth, set R

for the gain, then set R

for

the desired input impedance. As the gain increases for the
inverting configuration, a point will be reached where R

will

equal 50

, where R

is removed and the input match is set

by R

only. With R

fixed to achieve an input match to 50

is simply increased, to increase gain. This will, however,

quickly reduce the achievable bandwidth, as shown by the
inverting gain of 16 frequency response in the Typical
Characteristic curves. For gains > 10V/V (14dB at the matched
load), noninverting operation is recommended to maintain
broader bandwidth.

OPA695

+5V

DIS

Load

562

54.9

6.8

0.1

6.8

0.1

Optional
0.01

Source

442

OPA695

+5V

DIS

Load

Source

56.2

402

6.8

0.1

6.8

0.1

Optional
0.01

OPA695

SBOS293B

www.ti.com

FIGURE 3. AC-Coupled, G = +8V/V, Single-Supply Specifications and Test Circuit.

FIGURE 4. AC-Coupled, G = 8V/V, Single-Supply Specifications and Test Circuit.

Figure 3 shows the AC-coupled, single +5V supply, gain of
+8V/V circuit configuration used as a basis for the +5V only
Specifications and Typical Characteristic curves. The key
requirement for broadband single-supply operation is to
maintain input and output signal swings within the useable
voltage ranges at both the input and the output. The circuit
of Figure 3 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 806

resistors) to

the noninverting input. The input signal is then AC-coupled
into this midpoint voltage bias. The input voltage can swing
to within 1.6V of either supply pin, giving a 1.8V

input

signal range centered between the supply pins. The input
impedance matching resistor (57.6

) used in Figure 3 is

adjusted to give a 50

input match when the parallel combi-

nation of the biasing divider network is included. The gain
resistor (R

) is AC-coupled, giving the circuit a DC gain of +1.

This puts the input DC bias voltage (2.5V) on the output as
well. The feedback resistor value has been adjusted from the
bipolar supply condition to re-optimize for a flat frequency
response in +5V only, gain of +8 operation (see Setting
Resistor Values to Optimize Bandwidth). On a single +5V
supply, the output voltage can swing to within 1.0V of either
supply pin while delivering more than 90mA output current
giving 3V output swing into 100

(7dBm maximum at the

matched load). The circuit of Figure 3 shows a blocking
capacitor driving into a 50

output resistor then into a 50

load. Alternatively, the blocking capacitor could be removed
with the load tied to a supply midpoint or to ground if the DC
current required by this grounded load is acceptable.

Figure 4 shows the AC-coupled, single +5V supply, gain of
8V/V circuit configuration used as a basis for the +5V only
Typical Characteristic curves. In this case, the midpoint DC
bias on the noninverting input is also de-coupled with an
additional 0.1

F decoupling capacitor. This reduces the

source impedance at higher frequencies for the noninverting
input bias current noise. This 2.5V bias on the noninverting
input pin appears on the inverting input pin and, since R

DC blocked by the input capacitor, will also appear at the
output pin. One advantage to inverting operation is that since
there is no signal swing across the input stage, higher slew
rates and operation to even lower supply voltages are pos-
sible. To retain a 1V

output capability, operation down to a

3V supply is allowed. At a +3V supply, the input common
mode range is 0V. However, for the inverting configuration of
a current feedback amplifier, wideband operation is retained
even with the input stage saturated.

OPA695

+5V

DIS

Load

806

57.6

0.1

1000pF

6.8

0.1

Source

348

1000pF

OPA695

+5V

DIS

Load

806

0.1

400

1000pF

6.8

0.1

1000pF

OPA695

SBOS293B

www.ti.com

The single-supply test circuits of Figures 3 and 4 show +5V
operation. These same circuits can be used over a single-
supply range of +5V to +12V. Operating on a single +12V
supply, with the Absolute Maximum Supply voltage specifica-
tion of +13V, gives adequate design margin for the typical

5% supply tolerance.

RF SPECIFICATIONS AND APPLICATIONS

The ultra-high, full-power bandwidth and 3rd-order intercept
of the OPA695 may be used to good advantage in IF
amplifier applications. Additional benefits to using a wideband
op amp such as the OPA695 include extremely good (and
independent) I/O impedance matching as well as very high
reverse isolation. A designer more accustomed to using
fixed-gain RF amplifiers will get almost perfect gain accuracy,
much higher I/O return loss, and 3rd-order intercept points
exceeding 30dBm (up to 110MHz) using only a 13mA supply
current for the OPA695. Using the considerable design
freedom achieved by adjusting the external resistors, the
OPA695 can replace a wide range of fixed-gain RF amplifiers
with a single part. To understand (in RF amplifier terms) how
to take advantage of this, consider first the 4-S parameters
(this will be done using the example circuits of Figures 1 and
2 on

5V supplies, but similar results can be obtained on a

single +5V to +12V supply).

INPUT RETURN LOSS (S

)

Input return loss is a measure of how nearly (over frequency)
the input impedance matches the source impedance. This is
relatively independent of gain setting for both the noninverting
and inverting configurations. The Typical Characteristic curves
show the magnitude of S

for the circuits of Figures 1 and

2 through 1GHz (noninverting gain of +8 and inverting gain
of 8 operation, respectively). Noninverting operation does
offer much better matching to higher frequencies, with the
only deviation due to the parasitic input capacitance of the
input pin. The noninverting input match is simply set by the
resistor to ground on the noninverting input, since the ampli-
fier itself shows a very high input impedance. Inverting
operation is also very good, but rises more quickly due to
loop gain roll-off effects appearing at the inverting node. The
inverting mode input match is set by the parallel combination
of R

and R

in Figure 2, since the inverting amplifier node

may be considered a virtual ground. A good, fixed-gain, RF
amplifier would have an input, Voltage Standing Wave Ratio
(VSWR) < 1.2:1. This corresponds to an S

of 21dB. The

OPA695 exceeds this performance through 100MHz for the
inverting mode of operation, and through 400MHz for the
noninverting mode.

OUTPUT RETURN LOSS (S

)

Output return loss is a measure of how nearly (over fre-
quency) the output impedance matches the load impedance.
This is relatively independent of gain setting for both the
noninverting and inverting configurations. The output match-
ing impedance, to a first order, is, simply set by adding a
series resistor to the low impedance output of the op amp.

Since the op amp itself shows a very low output impedance
that increases with frequency, an improvement in the output
match can therefore be obtained by adding a small equaliz-
ing capacitor across this output resistor. The Typical Charac-
teristic curves show the measured S

with and without this

2.5pF capacitor (across the 50

output resistor). Again, a

very good match for a fixed-gain RF amplifier would give a
VSWR of 1.2:1 (S

< 21dB). The Typical Characteristic

curves show the measured S

with and without this 2.5pF

capacitor across the 50

output resistor. The Typical Char-

acteristic curves show that a simple 50

output resistor holds

better than 21dB to 140MHz, but up to 380MHz with the
tuning capacitor.

FORWARD GAIN (S

)

In all high-speed amplifier data sheets, this is referred to as
the small signal gain which is plotted over frequency. The
difference between noninverting and inverting operation is
that the phase of S

starts out at 0

for the noninverting and

180

for the inverting. This initial phase shift for inverting

mode is inconsequential to most IF strip applications. The
phase of S

was not shown in the Typical Characteristic

curves, but is very linear with frequency and may be accu-
rately modeled as a constant time delay through the ampli-
fier.

The Typical Characteristic Curves for the OPA695 show S

over a range of signal gains where the external resistors
have been adjusted to re-optimize flatness at each gain
setting. Since this is a current feedback op amp, the signal
bandwidth can be held relatively constant as the desired gain
setting is changed. The plot of the noninverting bandwidth
versus gain shows some change in bandwidth versus gain
(due to parasitic capacitive effects on the inverting node) with
very little change showing up for the inverting mode of
operation.

Signal gains are most often referred to as V/V in op amp data
sheets. This is the voltage gain from input to output and is set
by external resistor ratios. Since the output impedance is set
by a physical series resistor, the voltage gain to the matched
load is cut in 1/2 by this resistor divider. The log gain to the
matched load for the noninverting circuit of Figure 1 is:

log

The log gain to the matched load for the inverting circuit of
Figure 2 is:

log

The specific resistor values used in Figures 1 and 2 give both
a maximally flat bandwidth and a 12dB gain to the matched
load. The design tables at the end of this section summarize
the required resistor values over a range of desired gains for
the circuits of Figures 1 and 2.

As the desired signal gain increases, the achievable band-
widths will decrease. In the noninverting case, it decreases
relatively quickly as shown in the Typical Characteristic

(1)

(2)

OPA695

SBOS293B

www.ti.com

curves. The inverting configuration holds almost constant
bandwidth (with correctly selected external resistor values)
until R

reduces to equal 50

, and remains at that value to

satisfy the input impedance matching requirement, with fur-
ther increases in gain achieved by increasing R

in Figure 2.

The bandwidth then decreases rapidly as shown by the gain
of 16V/V plot in the Typical Characteristic curves.

REVERSE ISOLATION (S

)

Reverse isolation is a measure of how much power injected
into the output pin makes it back to the source. This is rarely
specified for an op amp because it is so good. Op amps are
very nearly uni-directional signal devices. Below 300MHz,
the noninverting configuration of Figure 1 gives much better
isolation than the inverting of Figure 2. Both are well below
40dB isolation through 350MHz.

LIMITS TO DYNAMIC RANGE

The next set of considerations for RF amplifier applications
are the defined limits to dynamic range. Typical fixed-gain RF
amplifiers include:

· 1dB compression (a measure of maximum output power)

· Two-tone, 3rd-order, output intermodulation intercept (a

measure of achievable spurious-free dynamic range)

· Noise figure (a measure of degradation in signal to noise

ratio in passing through the amplifier)

1dB COMPRESSION

The definition for 1dB compression power is that output
power where the actual power is 1dB less than the input
power plus the log gain. In classic RF amplifiers, this is
typically 10dB less than the 3rd-order intercept. That relation-
ship does not hold for op amps since their intercept is
considerably improved by loop gain to be far more than 10dB
higher than the 1dB compression. A simple estimate for
1dB compression for the OPA695 is the maximum non-slew
limited output voltage swing available at the matched load
converted into a power with 1dB added to satisfy the defini-
tion. For the OPA695 on

5V supplies, its output will deliver

approximately

4.0V at the output pin or

2.0V at the matched

load. The conversion from V

to power (for a sine wave) is:

dBm

(

)

(

)

2 2

0 001 50

log

Converting this 4.0V

swing at the load to dBm gives

16dBm; adding 1dB to this (to satisfy the definition) gives a
1dB compression of 17dBm for the OPA695 operating on

5V supplies. This will be a good estimate for frequencies

that require less than the full slew rate of the OPA695.

The maximum frequency of operation given an available
slew rate and desired peak output swing (at the output pin for
a sine wave) is:

Slew Rate

MAX

0 707

( .

)

Putting in the 4600V/

s slew rate available in the inverting

mode of operation and the 4.0V peak output swing at the
output pin gives a maximum frequency of 259MHz. This is
the maximum frequency where the 1dB compression would
be 17dBm at the matched load. Higher useable bandwidths
are possible at lower output powers, as shown in the Large
Signal Bandwidth curves. As those graphs show, 7V

out-

puts are possible with almost perfect frequency response
flatness through 100MHz for both non-inverting or inverting
operation.

TWO-TONE 3rd-ORDER OUTPUT
INTERMODULATION INTERCEPT (OP

)

In narrowband IF strips, each amplifier typically feeds into a
bandpass filter that attenuates most harmonic distortion
terms. The most troublesome remaining distortion is the 3rd-
order, two-tone intermodulations that can fall very close (in
frequency) to the desired signals and cannot be filtered out.
If two test frequencies are defined at F

F and F

the 3rd-order intermodulation distortion products will fall at
F

+ 3

F and F

F. If the two test power levels (P

) are

equal, the OPA695 will produce 3rd-order spurious terms
(P

) that are at these frequencies and at a power level below

the test power levels given by:

(

)

The 3rd-order intercept plot shown in the Typical Character-
istic curves shows a very high intercept at low frequencies
that decreases with increasing frequency. This intercept is
defined at the matched load to allow direct comparison with
fixed-gain RF amplifiers. To produce a 2V

total two-tone

envelope at the matched load, each power level must be
4dBm at the matched load (1V

). Using Equation 5, and the

performance curve for inverting operation, at 50MHz (41.5dBm
intercept) the 3rd-order spurious will be 2 · (41.5 4) = 75dB
below these 4dBm test tones. This is an exceptionally low
distortion for an amplifier that only uses 13mA supply current.
Considerable improvement from this level of performance is
also possible if the output drives directly into the lighter load
of an ADC input (see

High SFDR Differential ADC driver

section).

This very high intercept versus quiescent power is achieved
by the high loop gain of the OPA695. This loop gain does,
however, decrease with frequency, giving the decreasing
OP3 performance shown in the Typical Characteristics. Ap-
plication as an IF amplifier through 200MHz is possible with
output intercepts exceeding 21dBm at 200MHz. Intercept
performance will vary slightly with gain setting decreasing at
higher gains (that is, gains greater than the 8V/V, or 12dB,
gain used in the Typical Characteristic curves) and increas-
ing at lower gains.

(3)

(4)

(5)

OPA695

SBOS293B

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FIGURE 5. IF Amplifier with Improved Noise Figure.

GAIN TO LOAD

NOISE

(dB)

(

)

(

)

FIGURE

478

159

17.20

468

134

16.55

458

113

15.95

446

15.40

433

14.91

419

14.47

402

14.09

384

13.76

363

13.23

340

13.23

314

13.03

284

12.86

252

12.72

215

12.60

174

12.51

TABLE I. Noninverting Wideband Op Amp (Figure 1).

GAIN TO LOAD

NOISE

(dB)

(

)

(

)

FIGURE

516

518

16.34

511

412

15.54

506

334

14.78

500

275

14.07

493

228

13.40

486

190

12.78

478

160

12.21

469

135

11.70

458

114

11.25

447

10.85

434

10.15

419

10.21

403

9.96

384

9.74

364

9.57

TABLE II.

Noninverting with a 1:2 Input Step-Up Trans-
former (Figure 5).

GAIN TO LOAD

OPTIMUM

INPUT

NOISE

(dB)

(

)

(

)

MATCH R

FIGURE

463.27

116

16.94

454.61

101

16.06

444.91

114

15.16

434.07

142

14.23

421.95

199

13.24

408.42

380

12.16

398.11

Infinite

11.03

446.68

Infinite

10.92

501.19

Infinite

10.83

562.34

Infinite

10.75

630.96

Infinite

10.67

707.95

Infinite

10.61

794.33

Infinite

10.55

891.25

Infinite

10.49

1000.00

Infinite

10.45

TABLE III. Inverting Wideband RF Amplifier (Figure 2).

NOISE FIGURE

All fixed-gain RF amplifiers show a very good noise figure
(typically < 5dB). For broadband amplifiers, this is achieved
by a low-noise input transistor and an input match set by
feedback. This feedback greatly reduces the noise figure for
fixed-gain RF amplifiers, but also makes the input match
dependent on the load and the output match dependent on
the source impedance at the input.

The noise figure for an op amp is always higher than for
fixed-gain RF amplifiers due to the more complex internal
circuits of an op amp (giving higher input noise voltage and
current terms). Also, for simple circuits, the input match is set
resistively. What is gained is an almost perfect I/O imped-
ance match, much better load isolation, and very high 3rd-
order intercepts versus quiescent power. These higher noise
figures can be acceptable if the OPA695 has enough gain
preceding it in the IF chain.

Op amp noise figure equations include at least six terms (see
the Noise Performance section), due to the external resis-
tors. As a point of reference, the circuit of Figure 1 has an
input noise figure of 14dB while the inverting configuration of
Figure 2 has an input noise figure of 11dB. At higher gains,
it is typical for the inverting noise figure to be slightly better
than for an equivalent gain, noninverting configuration. One
easy way to improve the noise figure for the noninverting
configuration of the OPA695 is to include a step-up, 1:2 turns
ratio transformer at the input. This configuration is shown in
Figure 5.

OPA695

+5V

DIS

Load

Supply decoupling

not shown.

200

Source

1:2

In all cases, exact computed values for resistors are shown--
in application, pick standard resistor values that are closest
to those in the tables.

The transformer provides a noiseless voltage gain at the
expense of higher source impedance for the OPA695
noninverting input current noise. The input impedance is still
set to 50

by the 200

resistor on the transformer second-

ary. A 1:2 turns ratio transformer will reflect the 200

to the

input side as a 50

impedance over the bandwidth of the

transformer. Using a 1:2 step-up transformer will also reduce
the required amplifier gain by 1/2 for any particular desired
overall gain.

Tables I - III summarize the recommended resistor values
and resulting noise figures over the desired gain setting for
three circuit options for the OPA695 operated as a precision
IF amplifier. In each case, R

and R

are adjusted for both

best bandwidth and to achieve the required gain.

OPA695

SBOS293B

www.ti.com

FIGURE 8. Dual Output LO Buffer.

SAW FILTER BUFFER

One common requirement in an IF strip is to buffer the output
of a mixer with enough gain to recover the insertion loss of
a narrowband SAW filter. Figure 6 shows one possible
configuration driving a SAW filter. Figure 7 shows the inter-
cept at the 50

load. Operating in the inverting mode at a

voltage gain of 8V/V, this circuit provides a 50

input match

using the gain set resistor, has the feedback optimized for
maximum bandwidth (700MHz in this case), and drives
through a 50

output resistor into the matching network at

the input of the SAW filter. If the SAW filter gives a 12dB
insertion loss, a net gain of 0dB to the 50

load at the output

of the SAW (which could be the input impedance of the next
IF amplifier or mixer) will be delivered in the passband of the
SAW filter. Using the OPA695 in this application will isolate
the first mixer from the impedance of the SAW filter and
provide very low two-tone, 3rd-order spurious levels in the
SAW filter bandwidth. Inverting operation will give the broad-
est bandwidth up to a gain of 12V/V (15.6dB). Noninverting
operation will give higher bandwidth at gain settings higher
than this, but will also give a slight reduction in intercept and
Noise Figure performance.

OPA695

511

LNA

Diversity Receiver

Antenna

IF1

IF2

Bandpass

Filter

Bandpass

Filter

LNA

+5V

DIS

Power supply decoupling not shown.

LO BUFFER AMPLIFIER

The OPA695 may also be used to buffer the Local Oscillator
(LO) from the mixer(s). Operating at a voltage gain of +2, the
OPA695 will provide almost perfect load isolation for the LO
with a net gain of 0dB to the mixer. Applications through
1.4GHz LOs may be considered, but best operation would be
for LOs < 1.0GHz at a gain of +2. Gain could also be easily
provided by the OPA695 to drive higher power levels into the
mixer. One unique option in using the OPA695 as an LO
buffer is shown in Figure 8. Since the OPA695 can drive
multiple output loads, two identical LO signals may be
delivered to the mixers in a diversity receiver simply by
tapping the output off through two series 50

output resis-

tors. This circuit is set up for a voltage gain of +2V/V to the
output pin for a gain of +1V/V (0dB) to the mixers, but could
easily be adjusted to deliver higher gains as well.

OPA695

SAW
Filter

+12V

Matching

Network

= 12dB (SAW Loss)

Source

400

0.1

1000pF

FIGURE 6. IF Amplifier Driving SAW Filter.

FIGURE 7. 2-Tone, 3rd-Order Intermodulation Intercept.

Center Frequency (MHz)

150

250

200

100

Output Intercept (dBm)

OPA695

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FIGURE 9. Cable Modem Upstream Driver.

WIDEBAND CABLE DRIVING
APPLICATIONS

The high slew rate and bandwidth of the OPA695 can be
used to meet the most demanding cable driving applications.

CABLE MODEM RETURN PATH DRIVER

The standard cable modem upstream driver is typically
required to drive high power over a 5MHz to 65MHz band-
width while delivering < 50dBc distortion. Highly-integrated
solutions (including programmable gain stages) often fall
short of this target due to high losses from the amplifier
output to the line. The higher gain operating capability of the
OPA695, along with its very high slew rate, provides a low-
cost solution for delivering this signal with the required
spurious-free dynamic range. Figure 9 shows one example
of using the OPA695 as an upstream driver for a cable
modem return path. In this case, the input impedance of the
driver is set to 75

by the gain resistor (R

). The required

input level from the adjustable gain stage is significantly
reduced by the 15.5dB gain provided by the OPA695. In this
example, the physical 75

output matching resistor, along

with the 3dB loss in the diplexer, will attenuate the output
swing by 9dB on the line. In this example, a single +12V
supply was used to achieve the lowest harmonic distortion
for the 6V

output pin voltage through 65MHz. Measured

performance for this example gave 600MHz small-signal
bandwidth and < 54dBc distortion through 65MHz for a
6V

output pin voltage swing.

OPA695

450

Diplexer

3dB

Receive Channel

Supply decoupling

not shown

67dBmV

+12V

PGA Output

58dBmV

0.1

1000pF

0.01

0.1

51.5dBmV

DIS

1000pF

An alternative to this circuit, giving even lower distortion, is a
differential driver using two OPA695s driving into an output
transformer. This can be used either to double the available
line power, or to improve distortion by cutting the required
output swing in half for each stage. The channel disable
required by the MCNS specification should be implemented
by using the PGA disable feature. The MCNS disable speci-
fication requires that an output impedance match be main-
tained with the signal channel shut off. The disable feature of
the OPA695 is intended principally for power savings and
puts the output and inverting input pins into a high imped-
ance mode. This will not maintain the required output imped-
ance matching. Turning off the signal at the input of Figure
9, while keeping the OPA695 active, will maintain the imped-
ance matching while putting very little noise on the line. The
line noise in disable for the circuit of Figure 9 (with the PGA
source turned off, but still presenting a 75

source imped-

ance) will be a very low 4nV/

Hz (157dBm/Hz) due to the

low input noise of the OPA695.

RGB VIDEO LINE DRIVER

The extremely high bandwidth of the OPA695 operating at a
gain of +2 will support the fastest RAMDAC outputs for
applications such as auxiliary monitor driving. The front page
of this data sheet shows measured performance for a
0

+1V input square wave at 125MHz. As a general rule,

the required full-power bandwidth for the amplifier must be at
least one-half the pixel rate. With its noninverting gain of +2,
slew rate of 2900V/

s, and a 1.4V

output pin voltage swing

for standard RGB video levels, the OPA695 will give a

OPA695

SBOS293B

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FIGURE 11. High-Resolution RGB Driver Using DAC Complementary Output Current.

bandwidth of 600MHz, which will then support up to 1.26GHz
pixel rates. Figure 10 shows an example where three
OPA695s provide an auxiliary monitor output for a high-
resolution RGB RAMDAC.

An alternative circuit that will take advantage of the higher
inverting slew rate of the OPA695 (4300V/

s) takes the

complementary current output from the RAMDAC and con-
verts it to positive video to give a very high, full-power
bandwidth RGB line driver. This will give sharper pixel edges
than the circuit of Figure 10. Most high-speed DACs are
current-steering designs where there is both an output
current signal that is used for the video, and a complemen-

OPA695

500

536

86.6

+5V

Power supply decoupling not shown.

RAMDAC

768

4.22k

0.77V

0.1

DIS

tary output that is typically discarded into a matching resistor.
The complementary current output can be used as an aux-
iliary output if it is inverted, as shown in Figure 11.

In the circuit of Figure 11, the complementary current output
is terminated by an equivalent 75

impedance (the parallel

combination of R

and R

) that also provides a current

division to reduce the signal current through the feedback
resistor, R

. This allows R

to be increased to a value which

will hold a flat frequency response. Since the complementary
current output is essentially an inverted video signal, this
circuit sets up a white video level at the output of the OPA695
for zero DAC output current (using the 0.77V DC bias on the

FIGURE 10. Gain of +2, High-Resolution RGB Monitor Output.

OPA695

511

+5V

Blue

Green

RAMDAC

Red

Addtional

OPA695

Stages

DIS

Power supply decoupling not shown.

OPA695

SBOS293B

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FIGURE 12. High Power, Wideband AC-Coupled Arbitrary Waveform Driver.

OPA695

+5V

464

66.5

0.01

200

OPA695

464

66.5

0.01

200

DAC

20mA Peak Output

Differential

Filter

Source

1.4:1

3.5V

Power supply decoupling not shown.

DIS

noninverting input), then inverts the complementary output
current to produce a signal that ranges from this 1.4V at zero
output current down to 0V at maximum output current level
(assuming a 20mA maximum output current). This will give a
very wideband (> 800MHz) video signal capability.

ARBITRARY WAVEFORM DRIVER

The OPA695 may be used as the output stage for moderate
output power Arbitrary Waveform Driver applications. Driving
out through a series 50

matching resistor into a 50

matched load will allow up to a 4.0V

swing at the matched

load (15dBm) when operating the OPA695 on a

5V power

supply. This level of power is available for gains of either

with a flat response through 100MHz. When interfacing
directly from a complementary current output DAC, consider
the circuit of Figure 11, modified for the peak output currents
of the particular DAC being considered. Where purely
AC-coupled output signals are required from a complemen-
tary current output DAC, consider a push-pull output stage
using the circuit of Figure 12. The resistor values here have
been calculated for a 20mA peak output current DAC which
produces up to a 5V

swing at the matched load (18dBm).

This approach will give higher power at the load with much
lower 2nd-harmonic distortion.

For a 20mA peak output current DAC, the mid-scale current
of 10mA will give a 2V DC output common-mode operating
voltage due to the 200

resistor to ground at the outputs.

The total AC impedance at each output is 50

, giving a

0.5V swing around this 2V common-mode voltage for the

DAC. These resistors also act as a current divider, sending
75% of the DAC output current through the feedback resistor
(464

). The blocking capacitor references the OPA695 out-

put voltage to ground, and turns the unipolar DAC output
current into a bipolar swing of 0.75 · 20mA · 464

= 7V

each amplifier output. Each output is exactly 180

out-of-

phase from the other, producing double 7V

into the match-

ing resistors. To limit the peak output current and improve
distortion, the circuit of Figure 12 is set up with a 1.4:1 step-
down transformer. This reflects the 50

load to be 100

the primary side of the transformer. For the maximum 14V

swing across the outputs of the two amplifiers, the matching
resistors will drop this to 7V

at the input of the transformer,

then down to 5V

maximum at the 50

load at the output of

the transformer. This step-down approach reduces the peak
output current to 14V

/(200

) = 70mA.

OPA695

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DIFFERENTIAL I/O
APPLICATIONS

The OPA695 offers very low 3rd-order distortion terms with
a dominant 2nd-order distortion for the single amplifier op-
eration. For the lowest distortion, particularly where differen-
tial outputs are needed, operating two OPA695s in a differ-
ential I/O design will suppress these even-order terms, deliv-
ering extremely low harmonic distortion through high fre-
quencies and powers. Differential outputs are often preferred
for high performance ADCs, twisted-pair driving, and mixer
interfaces. Two basic approaches to differential I/Os are the
noninverting or inverting configurations. Since the output is
differential, the signal polarity is somewhat meaningless--
the noninverting and inverting terminology applies here to
where the input is brought into the two OPA695s. Each
approach has its advantages and disadvantages. Figure 13
shows a basic starting point for non-inverting differential I/O
applications.

applications to include a blocking capacitor in series with R

This reduces the gain to 1 at low frequency, rising to the A

expression shown above at higher frequencies. The
noninverting input approach of Figure 13 can be used for
higher gains than the inverting input approach. It will, how-
ever, have a reduced full-power bandwidth due to the lower
slew rate of the OPA695 running noninverting vs inverting
input mode of operation.

Various combinations of single-supply or AC-coupled gain
can also be delivered using the basic circuit of Figure 13.
Common-mode bias voltages on the two noninverting inputs
pass on to the output with a gain of 1, since an equal DC
voltage at each inverting node creates no current through
R

. This circuit does show a common-mode gain of 1 from

input to output. The source connection should either remove
this common-mode signal if undesired (using an input trans-
former can provide this function), or the common-mode
voltage at the inputs can be used to set the output common-
mode bias. If the low common-mode rejection of this circuit
is a problem, the output interface may also be used to reject
that common-mode. For instance, most modern differential
input ADCs reject common-mode signals very well, while a
line driver application through a transformer will also remove
the common-mode signal at the secondary of the trans-
former.

Figure 14 shows a differential I/O stage configured as an
inverting amplifier. In this case, the gain resistors (R

)

become part of the input resistance for the source. This
provides a better noise performance than the non-inverting
configuration, but does limit the flexibility in setting the input
impedance separately from the gain.

500

OPA695

FIGURE 13. Noninverting Input Differential I/O Amplifier.

FIGURE 14. Inverting Input Differential I/O Amplifier.

500

OPA695

This approach allows for a source termination impedance
that is independent of the signal gain. For instance, simple
differential filters may be included in the signal path right up
to the non-inverting inputs without interacting with the
gain setting. The differential signal gain for the circuit of
Figure 13 is:

= 1 + 2 · R

Since the OPA695 is a current feedback amplifier, its band-
width is principally controlled with the feedback resistor
value--Figure 13 shows a typical value of 500

. However,

the differential gain may be adjusted with considerable free-
dom using just the R

resistor. In fact, R

may be a reactive

network providing a very isolated shaping to the differen-
tial frequency response. It is common for AC-coupled

(6)

The two noninverting inputs provide an easy common-mode
control input. This is particularly easy if the source is AC-
coupled through either blocking caps or a transformer. In
either case, the common-mode input voltages on the two

OPA695

SBOS293B

www.ti.com

noninverting inputs again have a gain of 1 to the output pins,
giving particularly easy common-mode control for single-
supply operation. The OPA695 used in this configuration
does constrain the feedback to the 500

region for best

frequency response. With R

fixed, the input resistors may be

adjusted to the desired gain, but will also be changing the
input impedance as well. The high-frequency common-mode
gain for this circuit from input to output will be the same as
for the signal gain. Again, if the source might include an
undesired common-mode signal, that could be rejected at
the input using blocking caps (for low-frequency and DC
common-mode) or a transformer coupling. The differential
performance plots shown in the Typical Characteristics used
the configuration of Figure 14 and an input 1:1 transformer.
The differential signal gain in the circuit of Figure 14 is:

= R

Using this configuration suppresses the 2nd-harmonics, leav-
ing only 3rd-harmonic terms as the limit to output SFDR. The
much higher slew rate of the inverting configuration also
extends the full-power bandwidth and the range of very low
intermodulation distortion over the performance bandwidth
available from the circuit of Figure 13. The Typical Charac-
teristics show that the circuit of Figure 14 operating at an
A

= 10 can deliver a 16V

signal with over 500MHz 3dB

bandwidth. Using Equation 4, this implies a differential output
slew of 18000V/

sec, or 9000V/

sec at each output. This

output slew rate is far higher than specified, and probably
due to the lighter load used in the differential tests.

This inverting input differential configuration is particularly
suited to very high SFDR converter interfaces--specifically
narrowband IF channels. The Typical Characteristics show
the 2-tone, 3rd-order intermodulation intercept exceeding
45dBm through 90MHz. Although this data was taken with an
800

load, the intercept model appears to work for this

circuit, simply treating the power level as if it were into 50

For example, at 70MHz, the differential Typical Characteristic
plots show a 48dBm intercept. To predict the 2-tone
intermodulation SFDR, assuming a 1dB below full-scale
envelope to a 2V

maximum differential input converter, the

test power level would be 9dBm 6dBm = 3dBm for each
tone. Putting this into the intercept equation, gives:

dBc = 2 · (48 3) = 90dBc

The single-tone distortion data shows approximately 72dB
SFDR at 70MHz for a 2V

output into this light 800

load.

A modest post filter after the amplifier can reduce these
harmonics (2nd at 140MHz, 3rd at 210MHz) to the point
where the full SFDR to a converter can be in the 85dB range
for a 70MHz IF operation.

FIGURE 15. Current-Feedback Transfer Function Analysis

Circuit.

(S)

ERR

BOARD

LITERATURE

PART

REQUEST

PRODUCT

PACKAGE

NUMBER

OPA695ID

SO-8

DEM-OPA68xU

MKT-351

OPA691IDBV

SOT23-6

DEM-OPA6xxN

MKT-348

DESIGN-IN TOOLS

DEMONSTRATION BOARDS

Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA695 in its two package
styles. Both of these are available free, as unpopulated PC
boards delivered with descriptive documentation. The sum-
mary information for these boards is shown below.

The board can be requested through the Texas Instruments
web site (www.ti.com).

OPERATING SUGGESTIONS

SETTING RESISTOR VALUES TO OPTIMIZE
BANDWIDTH

A current-feedback op amp such as the OPA695 can hold an
almost constant bandwidth over signal gain settings with the
proper adjustment of the external resistor values. This is
shown in the Typical Characteristic curves. The small-signal
bandwidth decreases only slightly with increasing gain. These
curves also show that the feedback resistor has been changed
for each gain setting. The resistor

values on the inverting

side of the circuit for a current-feedback op amp can be
treated as frequency response compensation elements while
their

ratios set the signal gain. Figure 15 shows the analysis

circuit for the OPA695 small-signal frequency response.

The key elements of this current feedback op amp model are:

Buffer gain from the noninverting input to the invert-

ing input

Buffer output impedance

ERR

Feedback error current signal

Z(s)

Frequency-dependent, open-loop transimpedance

gain from i

ERR

to V

(7)

(8)

OPA695

SBOS293B

www.ti.com

FIGURE 16. Recommended Feedback Resistor vs Noise

Gain.

600

500

400

300

200

100

Noise Gain (V/V)

Feedback Resistor (

)

= +5V

The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however,
set the CMRR for a single op amp differential amplifier
configuration. For the buffer gain

< 1.0, the CMRR =

20 · log (1

, the buffer output impedance, is a critical portion of the

bandwidth control equation. For the OPA695, it is typically
about 28

for

5V operation and 31

for single +5V opera-

tion.

A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error volt-
age for a voltage-feedback op amp) and passes this on to the
output through an internal frequency-dependent
transimpedance gain. The Typical Characteristic curves show
this open-loop transimpedance response. This is analogous
to the open-loop voltage gain curve for a voltage-feedback
op amp. Developing the transfer function for the circuit of
Figure 18 gives Equation 9:

( )

Where

Noise Gain

= +

This is written in a loop gain analysis format, where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z(s) were infinite over all frequencies, the
denominator of Equation 9 would reduce to 1, and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 9 determines the
frequency response. Equation 10 shows this as the loop gain
equation:

Loop Gain

( )

If 20 · log (R

+ NG · R

) were superimposed on the open-

loop transimpedance plot, the difference between the two
would be the loop gain at a given frequency. Eventually, Z(s)
rolls off to equal the denominator of Equation 10, at which
point the loop gain has reduced to 1 (and the curves have
intersected). This point of equality is where the amplifier
closed-loop frequency response given by Equation 9 will
start to roll off, and is exactly analogous to the frequency at
which the noise gain equals the open-loop voltage gain for a
voltage-feedback op amp. The difference here is that the
total impedance in the denominator of Equation 10 may be
controlled separately from the desired signal gain (or NG).

The OPA695 is internally compensated to give a maximally
flat frequency response for R

= 402

at NG = 8 on

supplies. Evaluating the denominator of Equation 7 (which is
the feedback transimpedance) gives an optimal target of
663

. As the signal gain changes, the contribution of the

NG · R

term in the feedback transimpedance will change, but

the total can be held constant by adjusting R

. Equation 11

gives an approximate equation for optimum R

over signal

gain:

NG R

663

As the desired signal gain increases, this equation will
eventually predict a negative R

. A somewhat subjective limit

to this adjustment can also be set by holding R

to a

minimum value of 10

. Lower values will load both the buffer

stage at the input and the output stage if R

gets too low,

actually decreasing the bandwidth. Figure 16 shows the
recommended R

versus NG for both

5V and a single +5V

operation. The optimum target feedback impedance for +5V
operation used in Equation 8 is 663

, while the typical buffer

output impedance is 32

. The values for R

versus gain

shown here are approximately equal to the values used to
generate the Typical Characteristic curves. In some cases,
the values used differ slightly from that shown here, in that
the values used in the Typical Characteristics are also
correcting for board parasitics not considered in the simpli-
fied analysis leading to Equation 11. The values shown in
Figure 16 give a good starting point for designs where
bandwidth optimization is desired and a flat frequency re-
sponse is needed.

(9)

(10)

The total impedance presented to the inverting input may be
used to adjust the closed-loop signal bandwidth. Inserting a
series resistor between the inverting input and the summing
junction will increase the feedback impedance (denominator
of Equation 10), decreasing the bandwidth. The internal
buffer output impedance for the OPA695 is slightly influ-
enced by the source impedance looking out of the non-
inverting input terminal. High source resistors will have the
effect of increasing R

, decreasing the bandwidth. For those

single-supply applications which develop a midpoint bias at
the non-inverting input through high-valued resistors, the
decoupling capacitor is essential for power-supply ripple
rejection, non-inverting input noise current shunting, and
minimizing the high-frequency value for R

in Figure 15.

(11)

OPA695

SBOS293B

www.ti.com

Inverting feedback optimization is somewhat complicated by
the impedance matching requirement at the input, as shown
in Figure 2. The resistor values shown in Table III should be
used in this case.

OUTPUT CURRENT AND VOLTAGE

The OPA695 provides output voltage and current capabilities
that are consistent with driving doubly-terminated 50

lines.

For a 100

load at a gain of +8 (see Figure 1), the total load

is the parallel combination of the 100

load and the 456

total feedback network impedance. This 82

load will require

no more than 45mA output current to support the

3.7V

minimum output voltage swing specified for 100

loads. This

is well below the minimum

90mA specifications.

The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage · current, or V-I, product
which is more relevant to circuit operation. Refer to the
Output Voltage and Current Limitations plot in the Typical
Characteristic curves. The X and Y axes of this graph show
the zero-voltage output current limit and the zero-current
output voltage limit, respectively. The four quadrants provide
a more detailed view of the OPA695 output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.

The minimum specified output voltage and current over-
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
specification tables. As the output transistors deliver power,
the junction temperatures will increase, decreasing the V

(increasing the available output voltage swing) and increas-
ing the current gains (increasing the available output cur-
rent). In steady-state operation, the available output voltage
and current will always be greater than that shown in the
over-temperature specifications, since the output stage junc-
tion temperatures will be higher than the minimum specified
operating ambient.

To maintain maximum output stage linearity, no output short-
circuit protection is provided. This will not normally be a
problem, since most applications include a series-matching
resistor at the output that will limit the internal power dissipa-
tion if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent
positive power supply pin will, in most cases, destroy the
amplifier. If additional short-circuit protection is required,
consider a small series resistor in the power-supply leads.
Under heavy output loads, this will reduce the available
output voltage swing. A 5

series resistor in each power-

supply lead will limit the internal power dissipation to less
than 1W for an output short circuit while decreasing the
available output voltage swing only 0.25V for up to 50mA
desired load currents. Always place the 0.1

F power supply

decoupling capacitors directly on the supply pins after these
supply current-limiting resistors.

DRIVING CAPACITIVE LOADS

One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter--including
additional external capacitance which may be recommended
to improve A/D linearity. A high-speed, high open-loop gain
amplifier like the OPA695 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier's open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.

The Typical Characteristics show the recommended R

ver-

sus capacitive load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA695. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded. Always
consider this effect carefully and add the recommended
series resistor as close as possible to the OPA695 output pin
(see

Board Layout Guidelines).

DISTORTION PERFORMANCE

The OPA695 provides good distortion performance into a
100

load on

5V supplies. Relative to alternative solutions,

the OPA695 holds much lower distortion at higher frequen-
cies (> 20MHz). Generally, until the fundamental signal
reaches very high frequency or power levels, the 2nd-
harmonic will dominate the distortion with a negligible 3rd-
harmonic component. Focusing then on the 2nd-harmonic,
increasing the load impedance improves distortion directly.
Remember, the total load includes the feedback network. In
the non-inverting configuration (Figure 1), this is the sum of
R

+ R

, while in the inverting configuration, it is just R

. Also,

providing an additional supply decoupling capacitor (0.01

between the supply pins (for bipolar operation) improves the
2nd-order distortion slightly (3dB to 6dB).

In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. The Typical Perfor-
mance Curves show the 2nd-harmonic increasing at a little
less than the expected 2x rate, while the 3rd-harmonic
increases at a little less than the expected 3x rate. Where the
test power doubles, the difference between it and the 2nd
harmonic decreases less than the expected 6dB, while the
difference between it and the 3rd decreases by less than the
expected 12dB.

OPA695

SBOS293B

www.ti.com

FIGURE 17. Op Amp Noise Figure Analysis Model.

4kT

OPA695

4kT = 1.6E 20J

at 290

4kTR

The OPA695 has extremely low 3rd-order harmonic distor-
tion. This also gives a high 2-tone, 3rd-order intermodulation
intercept, as shown in the Typical Characteristic curves. This
intercept curve is defined at the 50

load when driven

through a 50

matching resistor to allow direct comparisons

to RF MMIC devices and is shown for both gains of

8. There

is a slight improvement in intercept by operating the OPA695
in the inverting mode. The output matching resistor attenu-
ates the voltage swing from the output pin to the load by 6dB.
If the OPA695 drives directly into the input of a high imped-
ance device, such as an ADC, this 6dB attenuation is not
taken. Under these conditions, the intercept will increase by
a minimum 6dBm.

The intercept is used to predict the intermodulation products
for two closely-spaced frequencies. If the two test frequen-
cies, F

and F

, are specified in terms of average and delta

frequency, F

= (F

+ F

)/ 2 and

F = | F

| /2, the two 3rd-

order, close-in spurious tones will appear at F

3 ·

F. The

difference between two equal test-tone power levels and
these intermodulation spurious power levels is given by

dBc = 2 · (OP

), where OP

is the intercept taken from

the Typical Characteristic curve and P

is the power level in

dBm at the 50

load for one of the two closely-spaced test

frequencies. For example, at 50MHz, gain of 8, the OPA695
has an intercept of 42dBm at a matched 50

load. If the full

envelope of the two frequencies needs to be 2V

, this

requires each tone to be 4dBm. The 3rd-order intermodulation
spurious tones will then be 2 · (42 4) = 76dBc below the
test-tone power level (72dBm). If this same 2V

2-tone

envelope were delivered directly into the input of an ADC
without the matching loss or the loading of the 50

network,

the intercept would increase to at least 48dBm. With the
same signal and gain conditions, but now driving directly into
a light load, the 3rd-order spurious tones will then be at least
2 · (48 4) = 88dBc below the 4dBm test-tone power levels
centered on 50MHz. Tests have shown that, in reality, the
3rd-order spurious levels are much lower due to the lighter
loading presented by most ADCs.

NOISE PERFORMANCE

The OPA695 offers an excellent balance between voltage
and current noise terms to achieve low output noise. The
inverting current noise (22pA/

Hz) is lower than most other

current-feedback op amps while the input voltage noise
(1.8nV/

Hz) is lower than any unity-gain stable, wideband,

voltage-feedback op amp. This low-input voltage noise was
achieved at the price of a higher noninverting input current
noise (18pA/

Hz). As long as the AC source impedance

looking out of the noninverting node is less than 50

, this

current noise will not contribute significantly to the total
output noise. The op amp input voltage noise and the two
input current noise terms combine to give low output noise
under a wide variety of operating conditions. Figure 17
shows the op amp noise analysis model with all the noise
terms included. In this model, all noise terms are taken to
be noise voltage or current density terms in either nV/

Hz or

pA/

Hz.

The total output spot-noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 12 shows the general form for the
output noise voltage using the terms shown in Figure 13.

(12)

kTR

I R

kTR G

BN S

BI F

(

)

(

)

Dividing this expression by the noise gain (NG = (1+R

))

will give the equivalent input referred spot-noise voltage at
the noninverting input as shown in Equation 13:

(13)

kTR

I R

kTR

BN S

BI F

(

)

Evaluating these two equations for the OPA695 circuit and
component values shown in Figure 1 will give a total output
spot-noise voltage of 18.7nV/

Hz and a total equivalent input

spot-noise voltage of 2.3nV/

Hz. This total input referred

spot-noise voltage is higher than the 1.8nV/

Hz specification

for the op amp voltage noise alone. This reflects the noise
added to the output by the inverting current noise times the
feedback resistor. If the feedback resistor is reduced in high-
gain configurations (as suggested previously), the total input
referred voltage noise given by Equation 13 will just ap-
proach the 1.8nV/

Hz of the op amp itself. For example,

going to a gain of +20 (using R

= 200

) will give a total input

referred noise of 2.0nV/

Hz.

For a more complete discussion of op amp noise calculation,
see TI Application Note, SBOA066,

Noise Analysis for High

Speed Op Amps, available through the TI web site.

DC ACCURACY AND OFFSET CONTROL

A current-feedback op amp like the OPA695 provides excep-
tional bandwidth in high gains, giving fast pulse settling but
only moderate DC accuracy. The typical specifications show
an input offset voltage comparable to high-speed voltage-
feedback amplifiers; however, the two input bias currents are

OPA695

SBOS293B

www.ti.com

somewhat higher and are unmatched. Although bias current
cancellation techniques are very effective with most voltage-
feedback op amps, they do not generally reduce the output
DC offset for wideband current-feedback op amps. Since the
two input bias currents are unrelated in both magnitude and
polarity, matching the source impedance looking out of each
input to reduce their error contribution to the output is
ineffective. Evaluating the configuration of Figure 1, using a
worst-case +25

C input offset voltage and the two input bias

currents, gives a worst-case output offset range equal to:

(NG · V

) + (I

· R

/2 · NG)

· R

)

where NG = non-inverting signal gain

(8 · 3.0mV)

(30

A · 25

· 8)

(402

· 60

24mV

1.6mV

24mV

54mV

A fine-scale output offset null, or DC operating point adjust-
ment, is often required. Numerous techniques are available
for introducing DC offset control into an op amp circuit. Most
simple adjustment techniques do not correct for temperature
drift.

POWER SHUTDOWN OPERATION

The OPA695 provides an optional power shutdown feature
that can be used to reduce system power. If the V

DIS

control

pin is left unconnected, the OPA695 operates normally. This
shutdown is intended only as a power-saving feature. For-
ward path isolation is very good for small signals. Large
signal isolation is not ensured. Using this feature to multiplex
two or more outputs together is not recommended. Large
signals applied to the shutdown output stages can turn on
parasitic devices, degrading signal linearity for the desired
channel.

Turn-on time is very quick from the shutdown condition,
typically < 60ns. Turn-off time is strongly dependent on the
external circuit configuration, but is typically 200ns for the
circuit of Figure 1.

To shut down, the control pin must be asserted low. This
logic control is referenced to the positive supply, as shown in
the simplified circuit of Figure 18.

In normal operation, base current to Q1 is provided through
the 120k

resistor, while the emitter current through the 8k

resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1's emitter. As V

DIS

is pulled low,

additional current is pulled through the 8k

resistor, eventu-

ally turning on these two diodes (

180

A). At this point, any

further current pulled out of V

DIS

goes through those diodes

holding the emitter-base voltage of Q1 at approximately 0V.
This shuts off the collector current out of Q1, turning the
amplifier off. The supply current in the shutdown mode is only
that required to operate the circuit of Figure 18.

When disabled, the output and input nodes go to a high
impedance state. If the OPA695 is operating in a gain of +1,
this will show a very high impedance (3pF || 1M

) at the

output and exceptional signal isolation. If operating at a gain
greater than +1, the total feedback network resistance (R

) will appear as the impedance looking back into the

output, but the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (R

+ R

), giving relatively poor input to

output isolation.

THERMAL ANALYSIS

The OPA695 does not require external heatsinking for most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 150

Operating junction temperature (T

) is given by T

+ P

The total internal power dissipation (P

) is the sum of

quiescent power (P

) and additional power dissipated in the

output stage (P

) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total
supply voltage across the part. P

will depend on the

required output signal and load. However, for a grounded
resistive load, P

would be at a maximum when the

output is fixed at a voltage equal to one-half of either supply
voltage (for equal bipolar supplies). Under this condition,
P

= V

/(4 · R

), where R

includes feedback network

Note that it is the power in the output stage and not into the
load that determines internal power dissipation.

As an absolute worst-case example, compute the maximum
T

using an OPA695IDBV (SOT23-6 package) in the circuit

of Figure 1 operating at the maximum specified ambient
temperature of +85

C and driving a grounded 100

load.

= 10V · 14.1mA + 5

/(4 · (100

|| 458

)) = 217mW

Maximum T

= +85

C + (0.22W · 150

C/W) = 118

This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
since an absolute worst-case output stage power was as-
sumed in this calculation.

FIGURE 18. Op Amp Noise Figure Analysis Model.

17k

120k

Control

DIS

OPA695

SBOS293B

www.ti.com

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency am-
plifier like the OPA695 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for

all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on
the non-inverting input, it can react with the source imped-
ance to cause unintentional bandlimiting. To reduce un-
wanted capacitance, a window around the signal I/O pins
should be opened in all of the ground and power planes
around those pins. Otherwise, ground and power planes
should be unbroken elsewhere on the board.

b) Minimize the distance (< 0.25") from the power supply

pins to high frequency 0.1

F decoupling capacitors.

At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize induc-
tance between the pins and the decoupling capacitors.
The power-supply connections should always be decoupled
with these capacitors. An optional supply-decoupling ca-
pacitor across the two power supplies (for bipolar opera-
tion) will improve 2nd-harmonic distortion performance.
Larger (2.2

F to 6.8

F) decoupling capacitors, effective at

a lower frequency, should also be used on the main
supply pins. These may be placed somewhat farther from
the device and may be shared among several devices in
the same area of the PC board.

c) Careful selection and placement of external compo-

nents will preserve the high frequency performance
of the OPA695. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a
tighter overall layout. Metal-film and carbon composition,
axially-leaded resistors can also provide good high fre-
quency performance. Again, keep their leads and PC
board trace length as short as possible. Never use
wirewound-type resistors in a high frequency application.
Since the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors, should
also be placed close to the package. Where double-side
component mounting is allowed, place the feedback resis-
tor directly under the package on the other side of the
board between the output and inverting input pins. The
frequency response is primarily determined by the feed-
back resistor value, as described previously. Increasing
its value will reduce the bandwidth, while decreasing it will
give a more peaked frequency response. The 402

feedback resistor (used in the typical performance speci-
fications at a gain of +8 on

5V supplies) is a good starting

point for design. Note that a 523

feedback resistor,

rather than a direct short, is required for the unity gain
follower application. A current-feedback op amp requires
a feedback resistor--even in the unity gain follower con-
figuration--to control stability.

d) Connections to other wideband devices on the board

may be made with short direct traces or through on-
board transmission lines. For short connections, con-
sider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the total
capacitive load and set R

from the plot of

Recommended

vs Capacitive Load. Low parasitic capacitive loads

(< 5pF) may not need an R

since the OPA695 is

nominally compensated to operate with a 2pF parasitic
load. If a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is ac-
ceptable, implement a matched impedance transmission
line using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline layout
techniques). A 50

environment is usually not necessary

on board. In fact, a higher impedance environment will
improve distortion, as shown in the distortion versus load
plots. With a characteristic board trace impedance de-
fined (based on board material and trace dimensions), a
matching series resistor into the trace from the output of
the OPA695 is used. A terminating shunt resistor at the
input of the destination device is used as well. Remember
also that the terminating impedance will be the parallel
combination of the shunt resistor and the input impedance
of the destination device; this total effective impedance
should be set to match the trace impedance. The high
output voltage and current capability of the OPA695
allows multiple destination devices to be handled as
separate transmission lines, each with their own series
and shunt terminations. If the 6dB attenuation of a doubly-
terminated transmission line is unacceptable, a long trace
can be series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the series
resistor value as shown in the plot of

vs Capacitive

Load. This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal attenu-
ation due to the voltage divider formed by the series
output into the terminating impedance.

e) Socketing a high-speed part like the OPA695 is not

recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
OPA695 directly onto the board.

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