Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- OPA846 RELATED PRODUCTS
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE/ORDERING INFORMATION
- PIN CONFIGURATIONS
- ELECTRICAL CHARACTERISTICS: VS = +/-5V
- TYPICAL CHARACTERISTICS: VS = +/-5V
- APPLICATIONS INFORMATION
- WIDEBAND, NONINVERTING OPERATION
- WIDEBAND INVERTING GAIN OPERATION
- WIDEBAND, HIGH-SENSITIVITY TRANSIMPEDANCE DESIGN
- LOW-GAIN COMPENSATION FOR IMPROVED SFDR
- LOW-NOISE FIGURE, HIGH DYNAMIC RANGE IF AMPLIFIER
- NONINVERTING LOW-GAIN COMPENSATION
- DIFFERENTIAL OPERATION
- SINGLE-SUPPLY OPERATION
- DESIGN-IN TOOLS
- DEMONSTRATION BOARDS
- MACROMODELS AND APPLICATIONS SUPPORT
- OPERATING SUGGESTIONS
- SETTING RESISTOR VALUES TO MINIMIZE NOISE
- FREQUENCY RESPONSE CONTROL
- DRIVING CAPACITIVE LOADS
- DISTORTION PERFORMANCE
- DC ACCURACY AND OFFSET CONTROL
- THERMAL ANALYSIS
- BOARD LAYOUT
- PACKAGE DRAWINGS
- D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
- DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE
Wideband, Low-Noise, Voltage-Feedback
OPERATIONAL AMPLIFIER
APPLICATIONS
q
HIGH DYNAMIC RANGE ADC PREAMPS
q
LOW-NOISE, WIDEBAND, TRANSIMPEDANCE
AMPLIFIERS
q
WIDEBAND, HIGH GAIN AMPLIFIERS
q
LOW-NOISE DIFFERENTIAL RECEIVERS
q
VDSL LINE RECEIVERS
q
ULTRASOUND CHANNEL AMPLIFIERS
q
SECURITY SENSOR FRONT ENDS
q
UPGRADE FOR THE OPA686, CLC425, AND
LMH6624
FEATURES
q
HIGH BANDWIDTH: 400MHz (G = +10)
q
LOW INPUT VOLTAGE NOISE: 1.2nV/
Hz
q
VERY LOW DISTORTION: 100dBc (5MHz)
q
HIGH SLEW RATE: 625V/
s
q
HIGH DC ACCURACY: V
IO
150
V
q
LOW SUPPLY CURRENT: 12.6mA
q
HIGH GAIN BANDWIDTH PRODUCT: 1750MHz
q
STABLE FOR GAINS
7
DESCRIPTION
The OPA846 combines very high gain bandwidth and large
signal performance with very low input voltage noise, while
dissipating a low 12.6mA supply current. The classical differ-
ential input stage, along with two stages of forward gain and
a high power output stage, combine to make the OPA846 an
exceptionally low distortion amplifier with excellent DC accu-
racy and output drive. The voltage-feedback architecture
allows all standard op amp applications to be implemented
with very high performance.
The combination of low input voltage and current noise,
along with a 1.75GHz gain bandwidth product, make the
OPA846 an ideal amplifier for wideband transimpedance
stages. As a voltage gain stage, the OPA846 is optimized for
a flat response at a gain of +10 and is stable down to a gain
of +7.
High Gain, 20MHz Transimpedance Amplifier
A new external compensation technique can be used to give
a very flat frequency response below the minimum stable
gain for the OPA846, further improving its already excep-
tional distortion performance. Using this compensation makes
the OPA846 one of the premier 12- to 16-bit Analog-to-Digital
(A/D) converter input drivers. The supply current for the
OPA846 is precisely trimmed to 12.6mA at +25
C. This,
along with carefully defined supply current tempco in the
input and output stages, combine to provide exceptional
performance over the full specified temperature range.
OPA846 RELATED PRODUCTS
INPUT NOISE
GAIN BANDWIDTH
SINGLES
VOLTAGE (nV/
Hz )
PRODUCT (MHz)
OPA842
2.4
200
OPA843
2.0
800
OPA847
0.85
3900
OPA846
SBOS250C JULY 2002 REVISED MAY 2003
www.ti.com
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002-2003, Texas Instruments Incorporated
OPA846
+5V
5V
V
O
50k
0.1
F
100pF
50k
0.2pF
10pF
Photodiode
I
S
V
B
Power-supply
decoupling not shown.
100
95
90
85
80
75
70
65
60
Frequency (MHz)
WIDEBAND TRANSIMPEDANCE
0.1
1
10
100
20
log(Z
T
) [5dB/div]
20 log(50k
) = 94dB
OPA846
OPA8
46
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OPA846
2
SBOS250C
www.ti.com
PIN CONFIGURATIONS
Top View
SO
ABSOLUTE MAXIMUM RATINGS
(1)
Power Supply ...............................................................................
6.5V
DC
Internal Power Dissipation ........................ See Thermal Analysis Section
Differential Input Voltage ..................................................................
1.2V
Input Voltage Range ............................................................................
V
S
Storage Temperature Range: D, DBV ........................... 40
C to +125
C
Lead Temperature (soldering, 10s) .............................................. +300
C
Junction Temperature (T
J
) ........................................................... +150
C
ESD Rating (Human Body Model) .................................................. 2000V
(Charge Device Model) ............................................... 1500V
(Machine Model) ........................................................... 200V
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
OPA846
SO-8
D
40
C to +85
C
OPA846
OPA846ID
Rails, 100
"
"
"
"
"
OPA846IDR
Tape and Reel, 2500
OPA846
SOT23-5
DBV
40
C to +85
C
OASI
OPA846IDBVT
Tape and Reel, 250
"
"
"
"
"
OPA846IDBVR
Tape and Reel, 3000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
Top View
SOT23
1
2
3
4
8
7
6
5
NC
+V
S
Output
NC
NC
NC = No Connection
Inverting Input
Noninverting Input
V
S
1
2
3
5
4
+V
S
Inverting Input
Output
V
S
Noninverting Input
OASI
1
2
3
5
4
Pin Orientation/Package Marking
OPA846
3
SBOS250C
www.ti.com
OPA846ID, IDBV
TYP
MIN/MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
70
C
(2)
+85
C
(2)
UNITS
MAX LEVEL
(3)
ELECTRICAL CHARACTERISTICS: V
S
=
5V
Boldface limits are tested at +25
C.
R
F
= 453
, R
L
= 100
,
and G = +10, unless otherwise noted. See Figure 1 for AC performance.
AC PERFORMANCE (see Figure 1)
Closed-Loop Bandwidth
G = +7, R
G
= 50
, V
O
= 200mV
PP
500
MHz
typ
C
G = +10, R
G
= 50
, V
O
= 200mV
PP
400
270
250
225
MHz
min
B
G = +20, R
G
= 50
, V
O
= 200mV
PP
110
82
80
75
MHz
min
B
Gain Bandwidth Product (GBP)
G
+40
1750
1275
1245
1200
MHz
min
B
Bandwidth for 0.1dB Gain Flatness
G = +10, R
L
= 100
, V
O
= 200mV
PP
140
40
36
35
MHz
min
B
Peaking at a Gain of +7
dB
typ
C
Harmonic Distortion
G = +10, f = 5MHz, V
O
= 2V
PP
2nd-Harmonic
R
L
= 100
76
70
68
66
dBc
max
B
R
L
= 500
100
89
87
85
dBc
max
B
3rd-Harmonic
R
L
= 100
109
95
92
90
dBc
max
B
R
L
= 500
112
105
101
96
dBc
max
B
2-Tone, 3rd-Order Intercept
G = +10, f = 10MHz
44
41
40
38
dBm
min
B
Input Voltage Noise
f > 1MHz
1.2
1.3
1.4
1.5
nV/
Hz
max
B
Input Current Noise
f > 1MHz
2.8
3.5
3.6
3.6
pA/
Hz
max
B
Rise-and-Fall Time
0.2V Step
1.2
1.5
1.6
1.8
ns
max
B
Slew Rate
2V Step
625
500
425
350
V/
s
min
B
Settling Time to 0.01%
2V Step
15
ns
typ
C
0.1%
2V Step
10
12
14
16
ns
max
B
1%
2V Step
6
8
10
12
ns
max
B
Differential Gain
G = +10, NTSC, R
L
= 150
0.02
%
typ
C
Differential Phase
G = +10, NTSC, R
L
= 150
0.02
deg
typ
C
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
V
O
= 0V
90
82
81
80
dB
min
A
Input Offset Voltage
V
CM
= 0V
0.15
0.60
0.68
0.70
mV
max
A
Average Offset Voltage Drift
V
CM
= 0V
0.4
1.5
1.5
1.5
V/
C
max
B
Input Bias Current
V
CM
= 0V
10
19
19.8
21
A
max
A
Input Bias Current Drift
V
CM
= 0V
1
20
20
35
nA/
C
max
B
Input Offset Current
V
CM
= 0V
0.1
0.35
0.45
0.60
A
max
A
Input Offset Current Drift
V
CM
= 0V
0.7
2
2
3.5
nA/
C
max
B
INPUT
Common-Mode Input Range (CMIR)
(5)
3.2
3.0
2.9
2.8
V
min
A
Common-Mode Rejection (CMR)
V
CM
=
1V, Input Referred
110
95
93
90
dB
min
A
Input Impedance
Differential-Mode
V
CM
= 0V
6.6 || 2.0
k
|| pF
typ
C
Common-Mode
V
CM
= 0V
4.7 || 1.8
M
|| pF
typ
C
OUTPUT
Output Voltage Swing
400
Load
3.4
3.3
3.2
3.1
V
min
A
100
Load
3.3
3.2
3.0
2.9
V
min
A
Current Output, Sourcing
V
O
= 0V
80
65
61
60
mA
min
A
Current Output, Sinking
V
O
= 0V
80
65
61
60
mA
min
A
Closed-Loop Output Impedance
G = +10, f = 100kHz
0.002
typ
C
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage
6
6
6
V
max
A
Maximum Quiescent Current
V
S
=
5V
12.6
12.9
13.0
13.2
mA
max
A
Minimum Quiescent Current
V
S
=
5V
12.6
12.3
12.1
11.8
mA
min
A
Power-Supply Rejection Ratio (PSRR)
V
S
= 4.5 to 5.5 (Input Referred)
95
90
88
85
dB
min
A
THERMAL CHARACTERISTICS
Specified Operating Range: D, DBV Package
40 to +85
C
typ
C
Thermal Resistance,
JA
Junction-to-Ambient
D
SO-8
125
C/W
typ
C
DBV
SOT23-5
150
C/W
typ
C
NOTES: (1) Junction temperature = ambient for +25
C min/max specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient
+23
C at high temperature limit for over temperature min/max specifications. (3) Test Levels: (A) 100% tested at +25
C. Over temperature limits by characterization and
simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V
CM
is the input common-
mode voltage. (5) Tested < 3dB below minimum specified CMR at
CMIR limits.
OPA846
4
SBOS250C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
T
A
= 25
C, G = +10, R
F
= 453
, R
G
= 50
, and R
L
= 100
, unless otherwise noted.
6
3
0
3
6
9
12
15
18
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Normalized Gain (dB)
1
10
100
1000
G = +50
See Figure 1
V
O
= 0.2V
PP
G = +20
G = +7 G = +10
3
0
3
6
9
12
15
18
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Normalized Gain (dB)
1
10
100
1000
G = 50
See Figure 2
V
O
= 0.2V
PP
R
G
= R
S
= 50
G = 20
G = 12
23
20
17
14
11
8
5
2
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Gain (dB)
10
100
1000
V
O
= 2V
PP
See Figure 1
R
L
= 100
G = +10V/V
V
O
= 5V
PP
V
O
= 0.2V
PP
V
O
= 1V
PP
29
26
23
20
17
14
11
8
5
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Gain (dB)
10
100
1000
V
O
= 2V
PP
See Figure 2
R
L
= 100
R
G
= R
S
= 50
G = 20V/V
V
O
= 5V
PP
V
O
= 0.2V
PP
V
O
= 1V
PP
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
2.0
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
NONINVERTING PULSE RESPONSE
Time (5ns/div)
Output Voltage (400mV/div)
Output Voltage (100mV/div)
Small Signal
100mV
See Figure 1
G = +10V/V
Right Scale
Large Signal
1V
Left Scale
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
2.0
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
INVERTING PULSE RESPONSE
Time (5ns/div)
Output Voltage (400mV/div)
Output Voltage (100mV/div)
Small Signal
100mV
See Figure 2
G = 20V/V
Left Scale
Large Signal
1V
Right Scale
OPA846
5
SBOS250C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
T
A
= 25
C, G = +10, R
F
= 453
, R
G
= 50
, and R
L
= 100
, unless otherwise noted.
75
80
85
90
95
100
105
110
115
5MHz HARMONIC DISTORTION vs LOAD RESISTANCE
Load Resistance (
)
Harmonic Distortion (dBc)
100
150
200
250
300
350
400
450
500
See Figure 1
G = +10V/V
V
O
= 2V
PP
75
80
85
90
95
100
105
1MHz HARMONIC DISTORTION vs LOAD RESISTANCE
Load Resistance (
)
Harmonic Distortion (dBc)
100
150
200
250
300
350
400
450
500
See Figure 1
G = +10V/V
V
O
= 5V
PP
65
75
85
95
105
115
HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
Harmonic Distortion (dBc)
0.1
1
10
100
3rd-Harmonic
2nd-Harmonic
G = +10V/V
V
O
= 2V
PP
R
L
= 200
See Figure 1
80
85
90
95
100
105
110
115
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Output Voltage Swing (V
PP
)
Harmonic Distortion (dBc)
0.1
1
10
2nd-Harmonic
See Figure 1
G = +10V/V
F = 5MHz
R
L
= 200
3rd-Harmonic
75
85
95
105
115
HARMONIC DISTORTION vs NONINVERTING GAIN
Gain (V/V)
Harmonic Distortion (dBc)
5
10
15
20
25
30
35
40
45
50
See Figure 1
V
O
= 2V
PP
R
L
= 200
F = 5MHz
2nd-Harmonic
3rd-Harmonic
75
85
95
105
115
HARMONIC DISTORTION vs INVERTING GAIN
Gain
V/V
Harmonic Distortion (dBc)
10
15
20
25
30
35
40
45
50
See Figure 2
V
O
= 2V
PP
R
L
= 200
F = 5MHz
2nd-Harmonic
3rd-Harmonic
OPA846
6
SBOS250C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
T
A
= 25
C, G = +10, R
F
= 453
, R
G
= 50
, and R
L
= 100
, unless otherwise noted.
10
1
INPUT VOLTAGE AND CURRENT NOISE
Frequency (Hz)
Voltage Noise (nV/
Hz)
Current Voise (pA/
Hz)
10
100
1k
10k
100k
1M
10M
100M
2.8pA/
Hz
Current Noise
1.2nV/
Hz
Voltage Noise
50
45
40
35
30
25
20
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT
Frequency (MHz)
Intercept Point (+dBm)
5
10
15
20
25
30
35
40
45
50
G = +10V/V
R
F
453
R
S
50
OPA846
P
IN
P
O
50
R
L
50
R
G
50
+5V
50
Source
5V
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
NONINVERTING GAIN FLATNESS TUNE
Frequency (MHz)
Deviation from 18.06dB Gain (0.1dB)
1
10
100
1000
NG = 8.0
NG = 8.5
NG = 10.0
NG = 9.5
NG = 9.0
V
O
= 200mV
PP
A
V
= +8
R
F
= 453
R
G
= 64.9
External Compensation
See Figure 9
3
2
1
0
1
2
3
4
5
6
LOW GAIN INVERTING BANDWIDTH
Frequency (MHz)
Normalized Gain (1dB)
1
10
100
1000
G = 6
G = 4
G = 2
G = 1
V
O
= 200mV
PP
R
F
= 400
External Compensation
See Figure 5
100
10
1
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
R
S
(
)
1
10
100
1000
G = +10V/V
23
20
17
14
11
8
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (MHz)
Normalized Gain to Capacitive Load (dB)
1
10
100
1000
C = 22pF
C = 47pF
C = 100pF
C = 10pF
R
S
adjusted for capacitive load.
R
453
R
S
OPA846
V
IN
V
O
50
R
L
1k
Power-supply
decoupling not shown.
C
L
R
G
50
+5V
50
Source
5V
(1k
is optional.)
OPA846
7
SBOS250C
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
T
A
= 25
C, G = +10, R
F
= 453
, R
G
= 50
, and R
L
= 100
, unless otherwise noted.
120
110
100
90
80
70
60
50
40
30
20
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
Frequency (Hz)
CMRR and PSRR (dB)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
CMRR
+PSRR
PSRR
120
100
80
60
40
20
0
20
0
30
60
90
120
150
180
210
OPEN-LOOP GAIN AND PHASE
Frequency (Hz)
Open-Loop Gain (dB)
Open-Loop Phase (
)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
10
9
20log (A
OL
)
A
OL
4
3
2
1
0
1
2
3
4
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
V
O
(V)
150
100
50
0
50
100
150
R
L
= 100
R
L
= 25
R
L
= 50
10
1
0.1
0.01
0.001
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Frequency (Hz)
Output Impedance (
)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
453
OPA846
Z
O
50
10
8
6
4
2
0
2
4
6
8
10
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
NONINVERTING OVERDRIVE RECOVERY
Time (50ns/div)
Output Voltage (2V/div)
Input Voltage (200mV/div)
See Figure 1
G = +10V/V
R
L
= 100
Output
Input
0
50
100
150
200
250
300
350
400
450
500
10
8
6
4
2
0
2
4
6
8
10
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
INVERTING OVERDRIVE RECOVERY
Time (50ns/div)
Output Voltage (2V/div)
Input Voltage (100mV/div)
See Figure 2
G = 20V/V
R
L
= 100
Output
Input
0
50
100
150
200
250
300
350
400
450
500
OPA846
8
SBOS250C
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TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
T
A
= 25
C, G = +10, R
F
= 453
, R
G
= 50
, and R
L
= 100
, unless otherwise noted.
0.25
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
0.25
SETTLING TIME
Time (ns)
Percent of Final Value (%)
0
5
10
15
20
25
G = +10V/V
R
L
= 100
V
O
= 2V Step
See Figure 1
83
80
77
74
71
68
65
62
PHOTODIODE TRANSIMPEDANCE
FREQUENCY RESPONSE
Frequency (MHz)
Transimpedance Gain (dB
)
1
10
100
C
D
= 100pF
R
F
= 10k
C
F
Adjusted
C
D
= 50pF
C
D
= 20pF
C
D
= 10pF
See Figure 4
0.25
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
0.25
25
20
15
10
5
0
5
10
15
20
25
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (
C)
Input Offset Voltage (mV)
Input Bias and Offset Current (
A)
50
25
0
25
50
75
100
125
100 x I
OS
V
IO
I
b
150
140
130
120
110
100
90
80
70
20
18
16
14
12
10
8
6
4
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (
C)
Output Current (10mA/div)
Supply Current (2mA/div)
50
25
0
25
50
75
100
125
Sourcing Output Current
Supply Current
Sinking Output Current
6
4
2
0
2
4
6
COMMON-MODE INPUT RANGE AND OUTPUT SWING
vs SUPPLY VOLTAGE
Supply Voltage (
V)
Voltage Range (V)
2.5
3.5
3.0
4.5
4.0
5.5
5.0
6.0
+V
IN
V
IN
+V
OUT
V
OUT
10
7
10
6
10
5
10
4
10
3
10
2
COMMON-MODE AND DIFFERENTIAL
INPUT IMPEDANCE
Frequency (Hz)
Input Impedance (
)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
Common-Mode
Differential
4.7M
6.6k
OPA846
9
SBOS250C
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TYPICAL CHARACTERISTICS: V
S
=
5V
T
A
= 25
C, G
D
= 20, R
G
= 50
, and R
L
= 400
, unless otherwise noted.
R
F
1k
OPA846
+5V
V
O
V
I
R
G
50
R
F
1k
R
L
400
OPA846
5V
R
G
50
Gain =
= G
D
=
R
F
R
G
V
O
V
I
3
0
3
6
9
12
15
18
DIFFERENTIAL SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (Hz)
Normalized Gain (dB)
1
10
100
1k
G
D
= 30V/V
G
D
= 40V/V
G
D
= 10V/V
G
D
= 20V/V
29
26
23
20
17
14
DIFFERENTIAL LARGE-SIGNAL
FREQUENCY RESPONSE
Frequency (Hz)
Gain (dB)
1
10
100
1k
V
O
= 5V
PP
V
O
= 8V
PP
V
O
= 400mV
PP
G
D
= 20V/V
60
65
70
75
80
85
90
95
100
105
110
115
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
Resistance (
)
Harmonic Distortion (dBc)
50
100
150
200
250
300
350
400
450
500
2nd-Harmonic
3rd-Harmonic
G
D
= 20V/V
V
O
= 4V
PP
F = 5MHz
65
75
85
95
105
115
DIFFERENTIAL DISTORTION vs FREQUENCY
Frequency (MHz)
Harmonic Distortion (dBc)
1
10
100
2nd-Harmonic
G
D
= 20V/V
R
L
= 400
V
O
= 4V
PP
3rd-Harmonic
80
85
90
95
100
105
110
115
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
Output Voltage Swing (V
PP
)
Harmonic Distortion (dBc)
1
10
2nd-Harmonic
G
D
= 20V/V
R
L
= 400
F = 5MHz
3rd-Harmonic
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
OPA846
10
SBOS250C
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APPLICATIONS INFORMATION
WIDEBAND, NONINVERTING OPERATION
The OPA846 provides a unique combination of features. Low
input voltage noise, along with a very low distortion output
stage, gives one of the highest dynamic range op amps
available. The very high Gain Bandwidth Product (GBP) can
be used either to deliver high signal bandwidths at high gain,
or to deliver very low distortion signals at moderate frequen-
cies and lower gains. To achieve the full performance of the
OPA846, careful attention to PC board layout and compo-
nent selection is required, as discussed in the following
sections of this data sheet.
Figure 1 shows the noninverting gain of a 10V/V circuit used
as the basis of the Electrical Characteristics and most of the
Typical Characteristic curves. Most of the curves are charac-
terized using signal sources with a 50
driving impedance,
and with a 50
load impedance presented by the measure-
ment equipment. In Figure 1, the 50
resistor at the V
IN
terminal matches the source impedance of the test genera-
tor, while the 50
series resistor at the V
O
terminal provides
a matching resistor for the measurement equipment load.
Generally, the data sheet voltage swing specifications are at
the output pin (V
O
in Figure 1), while the output power (dBm)
specifications are at the matched 50
load. The total 100
load at the output, combined with the 503
total feedback
network load, presents the OPA846 with an effective output
load of 83
for the circuit of Figure 1.
guideline ensures that the noise added at the output due to
the Johnson noise of the resistors does not significantly
increase the total noise over that due to the 1.2nV/
Hz input
voltage noise for the op amp. Higher resistor values can
certainly be used where the application requires it, but can
start to add significantly to the output noise power as de-
scribed in the Setting Resistor Values to Minimize Noise
section.
WIDEBAND INVERTING GAIN OPERATION
Operating the OPA846 as an inverting amplifier has several
benefits and is particularly appropriate when a matched input
impedance is required. Figure 2 shows the inverting gain
circuit used as the basis of the inverting mode of the Typical
Characteristic curves.
OPA846
+5V
5V
V
EE
+V
CC
R
S
50
V
O
V
I
50
+
0.1
F
+
6.8
F
6.8
F
R
G
50
R
F
453
50
Source
50
Load
0.1
F
FIGURE 1. DC-Coupled, G = +10V/V, Bipolar Supply, Speci-
fication and Test Circuit.
Voltage-feedback op amps (unlike current-feedback designs)
can use a wide range of resistor values to set the gain,
although these resistors usually have low values to maintain
a low total output noise. The circuit of Figure 1, and the
specifications at other gains, use the constraint that R
G
be
set to 50
and R
F
adjusted to get the desired gain. Using this
FIGURE 2. DC-Coupled, G = 20V/V, Bipolar Supply, Speci-
fication and Test Circuit.
OPA846
+5V
5V
V
CC
V
EE
91
R
S
50
V
O
V
I
+
6.8
F
0.1
F
+
6.8
F
0.1
F
0.1
F
R
F
1k
R
G
50
50
Source
50
Load
Driving this circuit from a 50
source, and constraining the
gain resistor (R
G
) to equal 50
, gives both a signal band-
width and noise advantage. R
G
acts as both the input
termination resistor and the gain setting resistor for the
circuit. Although the signal gain (V
O
/V
I
) for the circuit of
Figure 2 is double that for Figure 1, the noise gains are in fact
equal when the 50
source resistor is included. This has the
interesting effect of doubling the equivalent GBP of the
amplifier. This can be seen by observing the 200MHz band-
width for the inverting gain of 20. This implies a GBP of
4GHz, when in fact this extended bandwidth is given by the
reduced noise gain when the matched source resistor is
included. If the signal source is actually the low impedance
output of another amplifier, R
G
is increased to the minimum
load resistance value allowed for that amplifier and R
F
is then
adjusted to achieve the desired gain. For stable operation of
the OPA846, it is critical that this driving amplifier show very
low output impedance at frequencies beyond the expected
closed-loop bandwidth for the OPA846.
OPA846
11
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WIDEBAND, HIGH-SENSITIVITY
TRANSIMPEDANCE DESIGN
The high GBP and low input voltage and current noise for the
OPA846 make it an ideal wideband transimpedance ampli-
fier. Very high transimpedance gains (> 100k
) benefit from
the low input noise current of a JFET-input op amp, such as
the OPA657. Unity-gain stability in the op amp is not required
for application as a transimpedance amplifier. One transim-
pedance design example is shown on the front page of this
data sheet. Designs that require high bandwidths from a
large area (high capacitance) detector with relatively low
transimpedance gain will benefit from the low input voltage
noise offered by the OPA846. This input voltage noise is
peaked up over frequency at the output by the diode source
capacitance, and can, in many cases, become the limiting
factor to input sensitivity. The key elements of the design are
the expected diode capacitance (C
D
) with the reverse bias
voltage (V
B
) applied, the desired transimpedance gain (R
F
),
and the GBP of the OPA846 (1750MHz). Figure 3 shows a
design using a 50pF detector diode capacitance and a 10k
transimpedance gain. With these three variables set (includ-
ing the parasitic input capacitance for the OPA846 added to
C
D
) the feedback capacitor (C
F
) value can be set to control
the frequency response. To achieve a maximally flat 2nd-
order Butterworth frequency response, set the feedback pole
as shown in Equation 1.
1
2
4
R C
GBP
R C
F
F
F
D
=
(1)
The example of Figure 3 gives approximately 23MHz flat
bandwidth using the 0.8pF feedback compensation. If the
total output noise is bandlimited to a frequency less than the
feedback pole frequency, a simple expression for the equiva-
lent input noise current is given as Equation 3.
I
I
kT
R
E
R
E
FC
EQ
N
F
N
F
N
D
=
+
+
+
(
)
2
2
2
4
2
3
(3)
Where:
I
EQ
= equivalent input noise current if the output noise is
bandlimited to F < 1/(2
R
F
C
F
)
I
N
= input current noise for the op amp inverting input
E
N
= input voltage noise for the op amp
C
D
= diode capacitance
F = bandlimiting frequency in Hz (usually a post filter prior
to further signal processing)
4kT = 1.6E 20J at T = 290K
Evaluating this expression up to the feedback pole frequency
at 16.1MHz for the circuit of Figure 3 gives an equivalent
input noise current of 4.9pA/
Hz. This is much higher than
the 2.8pA/
Hz for just the op amp. This result is dominated
by the last term in the equivalent input noise current calcu-
lation from Equation 3. It is essential in this case to use a low-
voltage noise op amp. For example, if a slightly higher input
noise voltage, but otherwise identical op amp, was used
instead of the OPA846 amplifier in this application noise
amplifier (say 2.0nV/
Hz), the total input-referred current
noise would increase to 7.0pA/
Hz.
The output DC error for the circuit of Figure 3 is minimized by
including the 10k
to ground on the noninverting input. This
reduces the impact at the output of input bias current errors
to the offset current times the feedback resistor. To minimize
the output noise contribution of this resistor, a 0.01
F capaci-
tor is included in parallel. Worst-case output DC error for the
circuit of Figure 3 at 25
C is:
V
OS
=
0.6mV (input offset voltage)
0.35
A (input offset
current) 10k
=
4.1mV
Worst-case output offset DC drift is over the 0
C to 70
C span
is dV
OS
/dT =
1.5
V/
C (input offset drift)
2nA/C (input
offset current drift) 10k
=
21.5
V/
C
Improved output DC precision and drift is possible, particu-
larly at higher transimpedance gains, using the JFET input of
the OPA657. The JFET input removes the input bias current
from the error equation (eliminating the need for the resistor
to ground on the noninverting input), leaving only the input
offset voltage and drift as an output error term.
Included in the characteristic curves are transimpedance
frequency response curves for a fixed 10k
gain over vari-
ous detector diode capacitance settings. These curves, along
with the test circuit, are repeated in Figure 4. As the photo-
FIGURE 3. Wideband, Low Noise, Transimpedance Amplifier.
Adding the common-mode and differential-mode input capaci-
tance (1.8 + 2.0)pF to the 50pF diode source capacitance of
Figure 3, with a 10k
transimpedance gain using the 1750MHz
GBP for the OPA846, requires a feedback pole set to 16.1MHz.
This requires a 1pF total feedback capacitance. Typical sur-
face-mount resistors have 0.2pF parasitic capacitance leaving
a required extrinsic 0.8pF value, as shown in Figure 3.
Equation 2 gives the approximate 3dB bandwidth, if C
F
is set
using Equation 1.
f
GBP
R C
Hz
dB
F
D
-
=
( )
3
2
(2)
R
F
10k
+5V
5V
C
D
50pF
0.01
F
10k
OPA846
V
B
I
D
V
O
=
I
D
R
F
Power-supply
decoupling not shown.
C
F
0.8pF
OPA846
12
SBOS250C
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diode capacitance changes, the feedback capacitor must
change to maintain a stable and flat frequency response.
Using Equation 1, C
F
is adjusted to give the Butterworth
frequency responses presented in Figure 4.
FIGURE 5. Broadband, Low-Gain, Inverting Amplifier.
FIGURE 4. Transimpedance Bandwidth versus C
D
.
83
80
77
74
71
68
65
62
Frequency (MHz)
PHOTODIODE TRANSIMPEDANCE
FREQUENCY RESPONSE
Tranimpedance Gain (dB
)
1
10
100
C
D
= 100pF
R
F
= 10k
C
F
Adjusted
20 log(10k
)
C
D
= 50pF
C
D
= 20pF
C
D
= 10pF
R
F
10k
C
D
0.01
F
10k
OPA846
V
B
I
D
V
O
=
I
D
R
F
C
F
LOW-GAIN COMPENSATION FOR IMPROVED SFDR
Where a low gain is desired, and inverting operation is
acceptable, a new external compensation technique may be
used to retain the full slew rate and noise benefits of the
OPA846, while giving increased loop gain and the associ-
ated improvement in distortion offered by the decompen-
sated architecture. This technique shapes the loop gain for
good stability, while giving an easily controlled 2nd-order
low-pass frequency response. Considering only the noise
gain (noninverting signal gain) for the circuit of Figure 5, the
low-frequency noise gain (NG
1
) is set by the resistor ratios,
while the high-frequency noise gain (NG
2
) is set by the
capacitor ratios. The capacitor values set both the transition
frequencies and the high-frequency noise gain. If this noise
gain (determined by NG
2
= 1 + C
S
/C
F
) is set to a value
greater than the recommended minimum stable gain for the
op amp and the noise gain pole (set by 1/R
F
C
F
) is placed
correctly, a very well controlled, 2nd-order, low-pass fre-
quency response results.
To choose the values for both C
S
and C
F
, two parameters and
only three equations need to be solved. The first parameter is
the target high-frequency noise gain (NG
2
), which should be
greater than the minimum stable gain for the OPA846. Here,
a target NG
2
of 10.5 is used. The second parameter is the
desired low-frequency signal gain (R
F
/R
G
), which also sets
the low-frequency noise gain NG
1
(= 1 + R
F
/R
G
). To simplify
this discussion, target a maximally flat 2nd-order, low-pass
Butterworth frequency response (Q = 0.707). The signal gain
of 2 shown in Figure 5 sets the low-frequency noise gain to
NG
1
= 1 + R
F
/R
G
(= 3 in this example). Then, using only these
two gains and the GBP for the OPA846 (1750MHz), the key
frequency in the compensation can be determined as:
Z
GBP
NG
NG
NG
NG
NG
O
=
-
-
-
1
2
1
2
1
2
1
1 2
(4)
R
F
500
+5V
5V
C
S
27pF
0.01
F
167
OPA846
V
O
= V
I
R
F
R
G
Power-supply
decoupling not shown.
V
I
C
F
2.9pF
R
G
250
0
Source
Physically, this Z
O
(11.6MHz for these values) is set by:
1
2
R C
C
F
F
S
+
(
)
and is the frequency at which the rising portion of the noise
gain would intersect the unity gain if projected back to a 0dB
gain. The actual zero in the noise gain occurs at NG
1
Z
O
,
and the pole in the noise gain occurs at NG
2
Z
O
. Since GBP
is expressed in Hz, multiply Z
O
by 2
, and use this to get C
F
by solving:
C
R Z NG
pF
F
F
O
=
=
(
)
1
2
2 86
2
.
(5)
Finally, since C
S
and C
F
set the high-frequency noise gain,
determine C
S
by using NG
2
= 10.5:
C
NG
C
which gives C
pF
S
F
S
=
-
(
)
=
2
1
24 9
,
.
(6)
The resulting closed-loop bandwidth is approximately equal to:
f
Z
GBP
dB
O
-
3
(7)
For the values of Figure 5, f
3dB
is approximately 142MHz.
This is less than that predicted by dividing the GBP product by
NG
1
. The compensation network controls the bandwidth to a
lower value, while providing the full slew rate at the output and
an exceptional distortion performance due to increased loop
gain at frequencies below NG
1
Z
O
. The capacitor values
shown in Figure 5 are calculated for NG
1
= 3 and NG
2
= 10.5
with no adjustment for parasitic components.
See Figure 6 for the measured frequency response for the
circuit of Figure 5. This shows the expected gain of 2 (6dB)
with exceptional flatness through 70MHz and a 3dB band-
width of 170MHz. Repeating the swept frequency distortion
measurement for a 2V
PP
output into a 200
load and
comparing to the gain of +10 data shown in the Typical
Characteristic curves illustrates the improved distortion for
this low-gain compensation circuit.
Figure 7 compares the distortion at a gain of +10 for the
circuit of Figure 1 to the distortion at a gain of 2 for the circuit
of Figure 5.
OPA846
13
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LOW-NOISE FIGURE,
HIGH DYNAMIC RANGE IF AMPLIFIER
The low input noise voltage of the OPA846, and its high
2-tone, 3rd-order intercept, can be used to good advantage as
a fixed-gain IF amplifier. While input noise figures in the 10dB
range (for a matched 50
input) are easily achieved with just
the OPA846 alone, Figure 8 shows a technique that reduces
the noise figure even further, while providing a broadband,
moderate-gain IF amplifier stage using the OPA846.
Bringing the signal in through a step-up transformer to the
inverting input gain resistor has several advantages for the
OPA846. First, grounding the noninverting input eliminates
the contribution of the noninverting input current noise to
the output noise. Second, the noninverting input voltage
noise of the op amp is actually attenuated if reflected to the
input side of R
G
. Using the 1:2 (turns ratio) step-up trans-
former reflects the 50
source impedance at the primary
through to the secondary as a 200
source impedance.
The 200
R
G
resistor is reflected through to the trans-
former primary as a 50
input matching impedance. The
noninverting signal gain (noise gain, NG) to the amplifier
output is then 1 + 1000/400 = 3.5V/V. Taking the input
voltage noise (1.2nV/
Hz ) for the OPA846 times this noise
gain to the output, then reflecting this noise term to the input
side of the R
G
resistor, divides it by 5. This gives a net gain
of 0.7 for the noninverting input voltage noise when re-
flected to the input point for the op amp circuit. This term is
further reduced when referred back to the transformer input.
The 14dB gain to the matched load, for the circuit of Figure 8,
is precisely controlled (
0.2dB) and gives a 6dB noise figure
at the input of the transformer. The DC noise gain for this
circuit (3.5) is below the specified minimum stable gain. The
amplifier portion of the circuit uses the low-gain inverting
compensation described in the previous section. Measured
results show 140MHz small-signal bandwidth for the circuit of
Figure 8 with
0.1dB flatness through 50MHz. The OPA846
easily delivers a 2V
PP
A/D converter full-scale input at the
matched 50
load. 2-tone testing at 20MHz for the circuit of
Figure 8 (1V
PP
for each test tone) shows that the 2-tone
intermodulation intercept has improved to 40dBm versus the
34dBm shown in the Typical Characteristic curves, giving a
72dBc SFDR for the two 4dBm test tones at the load. This high
SFDR comes with relatively low total power dissipation versus
fixed-gain IF amplifier alternatives. Significantly higher SFDR
is delivered at lower frequencies and/or for the lighter loads
driving A/D converter inputs directly.
FIGURE 7. Distortion Comparison at G = +10 versus G = 2.
FIGURE 8. Low-Noise Figure IF Amplifier.
OPA846
+5V
5V
R
G
200
R
F
1k
50
V
O
2pF
C
S
20pF
50
Source
NF = 6dB
50
Load
1:2
Power-supply
decoupling
not shown.
FIGURE 6. Gain of 2 Frequency Response Using External
Compensation.
10
5
0
5
10
15
20
25
30
35
Frequency (Hz)
Gain (dB)
10
5
10
6
10
7
10
8
10
9
65
70
75
85
85
90
95
Frequency (MHz)
Gain (dB)
1
10
20
G = +10
V
O
= 2V
PP
R
L
= 200
G = 2
2nd-Harmonic
G = +10
G = 2
3rd-Harmonic
NONINVERTING LOW-GAIN COMPENSATION
Decreasing the operating gain for the OPA846 from the
nominal design point of +10 decreases the phase margin.
This increases Q for the closed-loop poles, peaks up the
frequency response, and extends the bandwidth. A peaked
frequency response shows overshoot and ringing in the
pulse response, as well as a higher integrated output noise.
When operating the amplifier at a noise gain less than +7,
increased peaking and possible sustained oscillations may
OPA846
14
SBOS250C
www.ti.com
65
75
85
95
105
115
Frequency (MHz)
Gain (dB)
1
10
100
2nd-Harmonic
3rd-Harmonic
G
D
= 20
V
O
= 4V
PP
R
L
= 400
result. However, operation at low gains may be desirable to
take advantage of the higher slew rate and exceptional DC
precision of the OPA846. Numerous external compensation
techniques are suggested for operating a high-gain op amp
at low gains. Most of these give zero/pole pairs in the closed-
loop response that cause long term settling tails in the pulse
response and/or phase nonlinearity in the frequency re-
sponse. Figure 9 shows an external compensation method
for a noninverting configuration that does not suffer from
these drawbacks.
DIFFERENTIAL OPERATION
Operating two OPA846 amplifiers in a differential inverting
configuration can further suppress even-order harmonic terms.
The Typical Characteristic curves show measured perfor-
mance for this condition. For the distortion data, the output
swing is increased to 4V
PP
into 400
to allow direct compari-
son to the 2V
PP
into 200
data for single-channel operation.
Figure 11 shows the swept frequency 2nd- and 3rd-harmonic
distortion for an inverting differential configuration, where
each channel is set up for a gain of 20.
Comparing this to the single-channel distortion (at 10MHz for
instance), about the same 3rd-harmonic and about a 5dB
improvement in the 2nd-harmonic is shown.
FIGURE 10. Noninverting Gain of +2 Response Using External
Compensation.
10
5
0
5
10
15
20
25
Frequency (Hz)
Gain (dB)
10
5
10
6
10
7
10
8
10
9
FIGURE 11. Differential Distortion vs Frequency.
FIGURE 9. Noninverting Low-Gain Compensation.
OPA846
+5V
5V
R
G
402
R
S
50
Power-supply
decoupling not shown.
V
I
R
1
65
R
T
50
R
F
402
V
O
50
Source
50
Load
The R
1
resistor across the two inputs increases the noise
gain (i.e., decreases the loop gain) without changing the
signal gain. This approach retains the full slew rate to the
output but gives up some of the low-noise benefit of the
OPA846. Assuming a low source impedance is used, set R
1
so that 1 + R
F
/(R
G
|| R
1
) is > 7. This approach may also be
used to tune the flatness by adjusting R
1
. The Typical
Characteristic curves show a signal gain of +8 with the
noise gain adjusted for flatness using different values for
R
1
. Figure 10 shows the measured frequency response for
the circuit of Figure 9 showing the flat frequency response
possible with this compensation.
SINGLE-SUPPLY OPERATION
The OPA846 may be operated from a single power supply if
system constraints require it. Operation from a single +5V to
+12V supply is possible with minimal change in AC perfor-
mance. The Typical Characteristics show the input and
output voltage ranges for a bipolar supply range from
2.5V
to
6V. The Common-Mode Input Range and Output Swing
vs Supply Voltage plot shows that the required headroom on
both the input and output nodes remains at approximately
1.5V over this entire range. On a single +5V supply for
instance, this means the noninverting input should remain
centered at 2.5V
1V, as should the output pin. See Figure
12 for an example application biasing the noninverting input
at mid-supply and running an AC-coupled input to the invert-
ing gain path. Since the gain resistor is blocked off for DC,
the bias point on the noninverting input appears at the
output, centering up that node, as well on the power supply.
The OPA846 can support this mode of operation down to a
single +5V supply and up to a single +12V supply.
OPA846
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BOARD
LITERATURE
PART
REQUEST
PRODUCT
PACKAGE
NUMBER
NUMBER
OPA846ID
SO-8
DEMOPA68XU
SBOU009
OPA846IDBV
SOT23-5
DEMOPA6XXN
SBOU010
TABLE I. Demo Board Part Numbers.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA846 in its two package
styles. Both of these are available, free, as an unpopulated
PC board delivered with descriptive documentation. The
summary information for these boards is shown in Table I.
Contact your sales representative or go to the TI web site
(www.ti.com) to request these evaluation boards.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often a quick way to analyze the performance of the OPA846
and its circuit designs. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and induc-
tance can play a major role on circuit performance. A SPICE
model for the OPA846 is available through the TI web page
(www.ti.com). These models predict typical small-signal AC,
transient steps, and DC performance under a wide variety of
operating conditions. The models include the noise terms
found in the electrical specification of this data sheet. These
models do not attempt to distinguish between the package
types in small-signal AC performance.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO MINIMIZE NOISE
The OPA846 provides a very low input noise voltage while
requiring a low 12.6mA quiescent current. To take full advan-
tage of this low input noise, careful attention to the other
R
F
Power-supply decoupling
not shown.
Range
2R
F
2R
F
0.01
F
R
G
V
I
OPA846
+V
CC
+12V
+5V
V
O
=
V
I
V
CC
2
R
F
R
G
FIGURE 12. Single-Supply Inverting Amplifier.
possible noise contributors is required. Figure 13 shows the
op amp noise analysis model with all the noise terms in-
cluded. In this model, all the terms are taken to be noise
voltage or current density terms in either nV/
Hz or pA/
Hz.
The total output spot noise voltage is computed as the
square root of the squared contributing terms to the output
noise voltage. This computation adds all the contributing
noise powers at the output by superposition and then takes
the square root of the terms to get back to a spot noise
voltage. Equation 8 shows the general form for this output
noise voltage using the terms of Figure 13.
E
E
I
R
kTR NG
I R
kTR NG
O
NI
BN
S
S
BI
F
F
=
+
(
)
+
(
)
+
(
)
+
2
2
2
2
4
4
(8)
Dividing this expression by the noise gain (NG = 1 + R
F
/R
G
)
gives the equivalent input-referred spot noise voltage at the
noninverting input, as shown in Equation 9.
E
E
I
R
kTR
I R
NG
kTR
NG
N
NI
BN
S
S
BI
F
F
=
+
(
)
+
+
+
2
2
2
4
4
(9)
Setting high resistor values into Equation 9 can quickly
dominate the total equivalent input referred noise. A 90
source impedance on the noninverting input adds a Johnson
voltage noise term equal to that of the amplifier. As a
simplifying constraint, set R
G
= R
S
in Equation 9 and assume
an R
S
/2 source impedance is at the noninverting input (where
R
S
is the signal source impedance with another matching R
S
to ground on the noninverting input). This results in Equation
10, where NG > 10 is assumed to further simplify the
expression.
E
E
I R
kT
R
N
NI
B
S
S
=
+
(
)
+
2
2
5
4
4
3
2
(10)
Evaluating this expression for R
S
= 50
gives a total equiva-
lent input noise of 1.7nV/
Hz. Note that the NG has dropped
out of this expression.
This is valid only for NG > 10 as will typically be required by
stability considerations.
4kT
R
G
R
G
R
F
R
S
OPA846
I
BI
E
O
I
BN
4kT = 1.6E 20J
at 290
K
E
RS
E
NI
4kTR
S
4kTR
F
FIGURE 13. Op Amp Noise Analysis Model.
OPA846
16
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FREQUENCY RESPONSE CONTROL
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the GBP shown in the Electrical
Characteristics. Ideally, dividing GBP by the noninverting
signal gain (also called the noise gain, or NG) predicts the
closed-loop bandwidth. In practice, this only holds true when
the phase margin approaches 90
, as it does in high-gain
configurations. At low gains (increased feedback factor),
most high-speed amplifiers exhibit a more complex response
with lower phase margin. The OPA846 is compensated to
give a maximally flat 2nd-order Butterworth closed-loop re-
sponse at a noninverting gain of +10 (see Figure 1). This
results in a typical gain of +10 bandwidth of 400MHz, far
exceeding that predicted by dividing the 1750MHz GBP by
10. Increasing the gain causes the phase margin to approach
90
and the bandwidth to more closely approach the pre-
dicted value of (GBP/NG). At a gain of +50, the OPA846
shows the 35MHz bandwidth predicted using the simple
formula F
3dB
= GBP/NG.
Inverting operation offers some interesting opportunities to
increase the available GBP. When the source impedance is
matched by the gain resistor (see Figure 2), the signal gain
is ( R
F
/R
G
), while the noise gain for bandwidth purposes is
(1 + R
F
/2R
G
). This cuts the noise gain almost in half,
increasing the minimum stable gain for inverting operation
under these conditions to 12V/V and increases the equiva-
lent GBP to > 3.5GHz.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often the
capacitive load is the input of an A/D converter, including
additional external capacitance that may be recommended to
improve A/D linearity. A high-speed, high open-loop gain
amplifier like the OPA846 is susceptible to decreasing stabil-
ity with capacitive loads and results in closed-loop response
peaking when a capacitive load is placed directly on the
amplifier output pin. If the primary considerations are fre-
quency response flatness, pulse fidelity, and/or distortion,
the simplest and most effective solution is to isolate the
capacitive load from the feedback loop by inserting a series
isolation resistor between the amplifier output and the ca-
pacitive load. This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Characteristic curves help the designer pick a
recommended R
S
versus Capacitive Load. The resulting fre-
quency response curves show the flat response for a given
capacitive load. Parasitic capacitive loads greater than 2pF
can begin to degrade the performance of the OPA846. Long
PC board traces, unmatched cables, and connections to
multiple devices can easily add additional capacitance to the
existing circuit. Always consider these effects carefully and
add the recommended series resistor as close to the output
pin of the OPA846 as possible (see the Board Layout section).
The criterion for setting the R
S
resistor for maximum band-
width, flat frequency response at the load is a simple proce-
dure. For the OPA846 operating in a gain of +10V/V, the
frequency response at the output pin is very flat to begin with,
allowing relatively small values of R
S
to be used for low
capacitive loads. As the signal gain increases, the unloaded
phase margin also increases. Driving capacitive loads at
higher gain settings require lower R
S
values than those
shown for a gain of +10V/V.
DISTORTION PERFORMANCE
The OPA846 is capable of delivering an exceptionally low
distortion signal at high frequencies over a wide range of
gains. The distortion plots found in the Typical Characteristic
curves show the typical distortion under a wide variety of
conditions. Most of these plots are limited to 110dB dynamic
range. The OPA846 distortion, while driving a 500
load,
does not rise above 90dBc until either the signal level
exceeds 2.0V
PP
and/or the fundamental frequency exceeds
5MHz. Distortion in the audio band is < 120dBc.
Generally, until the fundamental signal reaches very high
frequencies or power, the 2nd-harmonic dominates the dis-
tortion with negligible 3rd-harmonic component. Focusing
then on the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network: in the noninverting configura-
tion, this is the sum of R
F
+ R
G
, while in the inverting
configuration it is just R
F
(see Figures 1 and 2). Increasing
output voltage swing increases harmonic distortion directly.
A 6dB increase in output swing generally increases the 2nd-
harmonic to 12dB and the 3rd-harmonic to 18dB. Increasing
the signal gain also increases the 2nd-harmonic distortion.
Again, a 6dB increase in gain increases the 2nd- and 3rd-
harmonic by approximately 6dB, even with constant output
power and frequency. Finally, the distortion increases as the
fundamental frequency increases, due to the roll-off in the
loop gain with frequency. Conversely, the distortion improves
going to lower frequencies down to the dominant open-loop
pole at approximately 100kHz. Starting from the 86dBc 2nd-
harmonic for a 5MHz, 2V
PP
fundamental into a 200
load at
a gain = +10V/V (from the Typical Characteristic curves), the
2nd-harmonic distortion for frequencies lower than 100KHz
is approximately 86dBc 20 log(5MHz/100kHz) = 120dBc.
The OPA846 has extremely low 3rd-order distortion. This
also gives a high 2-tone, 3rd-order intermodulation intercept,
as shown in the Typical Characteristic curves. This intercept
curve is defined at the 50
load when driven through a 50
-
matching resistor to allow direct comparisons to R
F
devices.
This matching network attenuates the voltage swing from the
output pin to the load by 6dB. If the OPA846 drives directly
into the input of a high-impedance device, such as an A/D
converter, the 6dB attenuation is not present. Under these
conditions, the intercept increases by a minimum of 6dBm.
The intercept is used to predict the intermodulation spurious
for two closely-spaced frequencies. If the two test frequen-
cies f
1
and f
2
are specified in terms of average and delta
frequency, f
O
= (f
1
+ f
2
)/2 and
f =
f
2
f
1
/2, the two 3rd-
order, close-in spurious tones appear at f
O
3
f. The
OPA846
17
SBOS250C
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difference between the two equal test-tone power levels
and these intermodulation spurious power levels is given by
dBc = 2 (IM3 P
O
) where IM3 is the intercept taken from
the typical characteristic curve and P
O
is the power level in
dBm at the 50
load for one of the two closely-spaced test
frequencies. At 5MHz for instance, the OPA846 at a gain of
+10V/V has an intercept of 48dBm at a matched 50
load.
If the full envelope of the two frequencies needs to be 2V
PP
,
this requires each tone to be 4dBm. The 3rd-order
intermodulation spurious tones are 2 (48 4) = 88dBc
below the test-tone power level (84dBm). If this same 2V
PP
,
2-tone envelope were delivered directly into the input of an
A/D converter--without the matching loss or the loading of
the 50
network--the intercept would increase to at least
54dBm. With the same signal and gain conditions, but now
driving directly into a light load, the spurious tones will then
be at least 2 (54 4) = 100dBc below the 4dBm test-tone
power levels centered on 5MHz.
DC ACCURACY AND OFFSET CONTROL
The OPA846 can provide excellent DC signal accuracy due
to its high open-loop gain, high common-mode rejection, high
power-supply rejection, and low input offset voltage and bias
current offset errors. To take full advantage of its low
0.6mV
maximum (25
C) input offset voltage, careful attention to
input bias current cancellation is also required. The low-noise
input stage for the OPA846 has a relatively high input bias
current (10
A typical into the pins), but with a very close
match between the two input currents--typically
100nA
input offset current. Figures 14 and 15 show typical distribu-
tions of input offset voltage and current for the OPA846. The
total output offset voltage can be considerably reduced by
matching the source impedances looking out of the two pins.
For example, one way to add bias current cancellation to the
circuit of Figure 1 would be to insert a 20
series resistor into
the noninverting input from the 50
terminating resistor. When
the 50
source resistor is DC-coupled, this increases the
source resistances for the noninverting input bias current to
45
. Since this is now equal to the resistance looking out of
the inverting input (R
F
|| R
G
), the circuit cancels the gains for
the bias currents to the output, leaving only the offset current
times the feedback resistor as a residual DC error term at the
output. Using the 453
feedback resistor, this output error is
now less than
600nA 453
=
272
V over the full tempera-
ture range.
A fine-scale output offset null, or DC operating point adjust-
ment, is often required. Numerous techniques are available
for introducing a DC offset control into an op amp circuit.
Most of these techniques eventually reduce to setting up a
DC current through the feedback resistor. One key consider-
ation to selecting a technique is to ensure that it has minimal
impact on the desired signal path frequency response. If the
signal path is intended to be noninverting, the offset control
is best applied as an inverting summing signal to avoid
interaction with the signal source. If the signal path uses the
inverting mode, applying an offset control to the noninverting
input can be considered. For a DC-coupled inverting input
signal, this DC offset signal sets up a DC current back into
the source that must be considered. An offset adjustment
placed on the inverting op amp input can also change the
noise gain and frequency response flatness. See Figure 16
for one example of an offset adjustment for a DC-coupled
signal path that has minimum impact on the signal frequency
response. In this case, the input is brought into an inverting
gain resistor with the DC adjustment as an additional current
summed into the inverting node. The resistor values for
setting this offset adjustment are chosen to be much larger
than the signal path resistors. This ensures that the adjust-
ment has minimal impact on the loop gain and hence, the
frequency response.
FIGURE 14. Input Offset Voltage Distribution.
600
500
400
300
200
100
0
mV
Count
<
0.70
<
0.63
<
0.56
<
0.49
<
0.42
<
0.35
<
0.28
<
0.21
<
0.14
<
0.07
0
< 0.07
< 0.14
< 0.21
< 0.28
< 0.35
< 0.42
< 0.49
< 0.56
< 0.63
< 0.70
> 0.70
Mean = 0.01
Standard Deviation = 0.17
Total Count = 2952
FIGURE 15. Input Offset Current Distribution.
800
700
600
500
400
300
200
100
0
A
Count
<
0.45
<
0.41
<
0.36
<
0.32
<
0.27
<
0.23
<
0.18
<
0.14
<
0.09
<
0.05
0
< 0.04
< 0.09
< 0.14
< 0.18
< 0.23
< 0.27
< 0.32
< 0.36
< 0.41
< 0.45
> 0.45
Mean = 0.01
Standard Deviation = 0.08
Total Count = 2952
OPA846
18
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THERMAL ANALYSIS
The OPA846 does not require heat sinking or airflow in most
applications. Maximum desired junction temperature sets the
maximum allowed internal power dissipation as described
following. In no case should the maximum junction tempera-
ture be allowed to exceed +150
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in the
output stage (P
DL
) to deliver load power. Quiescent power is
the specified no-load supply current times the total supply
voltage across the part. P
DL
depends on the required output
signal and load but would, for a grounded resistive load, be
at a maximum when the output is fixed at a voltage equal to
1/2 either supply voltage (for equal bipolar supplies). Under
this worst-case condition, P
DL
= V
S
2
/(4 R
L
), where R
L
includes the feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA846IDBV (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85
C and driving a grounded 100
load at +2.5V
DC
.
P
D
= 10V(13.9mA) + 5
2
/(4 (100
|| 500
)) = 214mW
Maximum T
J
= +85
C + (0.21W 150
C/W) = 117
C
All actual applications will operate at a lower junction tem-
perature than the 117
C computed above. Compute the
actual stage power to get an accurate estimate of maximum
junction temperature, or use the results shown here as an
absolute maximum.
BOARD LAYOUT
Achieving optimum performance with a high-frequency am-
plifier such as the OPA846 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, create a window around the signal I/O pins leave
opened in all of the ground and power planes around those
pins.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1
F decoupling capacitors. At
the device pins, the ground and power plane layout should
not be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capaci-
tors. Larger (2.2
F to 6.8
F) decoupling capacitors are
effective at lower frequencies, and are recommended on the
main supply pins. These may be placed somewhat further
from the device and shared among several devices in the
same area of the PC board.
c) Careful selection and placement of external compo-
nents preserves the high-frequency performance of the
OPA846. Use resistors that have low reactance at high
frequencies. Surface-mount resistors work best and allow a
tighter overall layout. Metal-film and carbon composition,
axially leaded resistors can also provide good high-fre-
quency performance. Again, keep their leads and PC board
trace length as short as possible. Never use wire wound type
resistors in a high-frequency application. Since the output pin
and inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series output
resistor, if any, as close as possible to the output pin. Other
network components, such as noninverting input termination
resistors, should also be placed close to the package. Where
double-feedback side component mounting is allowed, place
the feedback resistor directly under the package on the other
side of the board between the output and inverting input pins.
Even with a low parasitic capacitance shunting the external
resistors, excessively high resistor values can create signifi-
cant time constants that can degrade performance. Good
axial metal-film or surface-mount resistors have approxi-
mately 0.2pF in shunt with the resistor. For resistor values
> 1.5k
, this parasitic capacitance can add a pole and/or a
zero below 500MHz that can effect circuit operation. Keep
resistor values as low as possible consistent with load driving
considerations. It has been suggested here that a good
starting point for design would be set the R
G
be set to 50
.
Doing this automatically keeps the resistor noise terms low,
and minimizes the effect of parasitic capacitance. Transim-
pedance applications can use much higher resistor values.
The compensation techniques described in this data sheet
allow excellent frequency response control, even with very
high feedback resistor values.
FIGURE 16. DC-Coupled, Inverting Gain of 20V/V with
Output Offset Adjustment.
R
F
1k
200mV Output Adjustment
Power-supply decoupling
not shown.
5k
5k
48
0.1
F
R
G
50
V
I
20k
100
0.1
F
5V
+5V
OPA846
+5V
5V
V
CC
V
EE
V
O
= = 20V/V
V
O
V
I
R
F
R
G
OPA846
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SBOS250C
www.ti.com
d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the
trace and the input to the next device as a lumped capacitive
load. Relatively wide traces (50mils to 100mils) should be
used, preferably with ground and power planes opened up
around them. Estimate the total capacitive load and set R
S
from the plot of Recommended R
S
vs Capacitive Load. Low
parasitic capacitive loads (< 5pF) may not need an R
S
,
since
the OPA846 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an R
S
are allowed, as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated transmission
line is acceptable, implement a matched impedance trans-
mission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50
environment is normally not necessary
onboard and, in fact, a higher impedance environment im-
proves distortion, as shown in the distortion versus load
plots. With a characteristic board trace impedance defined
based on board material and trace dimensions, a matching
series resistor into the trace from the output of the OPA846
is used, as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance is the parallel combination of the shunt resistor
and input impedance of the destination device; this total
effective impedance should be set to match the trace imped-
ance. If the 6dB attenuation of a doubly-terminated transmis-
sion line is unacceptable, a long trace can be series-termi-
nated at the source end only. Treat the trace as a capacitive
load in this case and set the series resistor value as shown
in the plot of Recommended R
S
vs Capacitive Load. This
does not preserve signal integrity as well as a doubly-
terminated line. If the input impedance of the destination
device is low, there will be some signal attenuation due to the
voltage divider formed by the series output into the terminat-
ing impedance.
FIGURE 17. Internal ESD Protection.
External
Pin
+V
CC
V
CC
Internal
Circuitry
e) Socketing a high-speed part like the OPA846 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network, which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA846
onto the board.
INPUT AND ESD PROTECTION
The OPA846 is built using a very high-speed complementary
bipolar process. The internal junction breakdown voltages are
relatively low for these very small geometry devices. These
breakdowns are reflected in the Absolute Maximum Ratings
table. All device pins are protected with internal ESD protec-
tion diodes to the power supplies, as shown in Figure 17.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with
15V supply parts
driving into the OPA846), current-limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible, since high values degrade both
noise performance and frequency response.
OPA846
20
SBOS250C
www.ti.com
PACKAGE DRAWINGS
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
OPA846
21
SBOS250C
www.ti.com
PACKAGE DRAWINGS
(Cont.)
DBV (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,10
M
0,20
0,95
0
8
0,25
0,35
0,55
Gage Plane
0,15 NOM
4073253-4/G 01/02
2,60
3,00
0,50
0,30
1,50
1,70
4
5
3
1
2,80
3,00
0,95
1,45
0,05 MIN
Seating Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-178
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA846ID
ACTIVE
SOIC
D
8
100
OPA846IDBVR
ACTIVE
SOP
DBV
5
3000
OPA846IDBVT
ACTIVE
SOP
DBV
5
250
OPA846IDR
ACTIVE
SOIC
D
8
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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