PCM1608: 24-Bit 192kHz Sampling 8-Ch Enhan. Multilevel Delta-Sigma D/A Converter (Rev. A)
24-Bit, 192kHz Sampling, 8-Channel,
Enhanced Multilevel, Delta-Sigma
DIGITAL-TO-ANALOG CONVERTER
PCM1608
DESCRIPTION
The PCM1608 is a CMOS monolithic integrated circuit that
features eight 24-bit audio Digital-to-Analog Converters
(DACs) and support circuitry in a small LQFP-48 package. The
DACs utilize Texas Instrument's enhanced multi-level, delta-
sigma architecture that employs fourth-order noise shaping and
8-level amplitude quantization to achieve excellent signal-to-
noise performance and a high tolerance to clock jitter.
The PCM1608 accepts industry-standard audio data formats
with 16- to 24-bit audio data. Sampling rates up to 200kHz
(channels 1, 2, 7, and 8) or 100kHz (channels 3, 4, 5, and 6)
are supported. A full set of user-programmable functions are
accessible through a 4-wire serial control port that supports
register write and read functions.
FEATURES
q
24-BIT RESOLUTION
q
ANALOG PERFORMANCE:
Dynamic Range: 100dB typ (PCM1608Y)
105dB typ (PCM1608KY)
SNR: 100dB typ (PCM1608Y)
105dB typ (PCM1608KY)
THD+N: 0.003% typ (PCM1608Y)
0.002% typ (PCM1608KY)
Full-Scale Output: 3.1Vp-p typ
q
4x/8x OVERSAMPLING INTERPOLATION FILTER:
Stopband Attenuation: 55dB
Passband Ripple:
0.03dB
q
SAMPLING FREQUENCY:
5kHz to 200kHz (Channels 1, 2, 7, and 8)
5kHz to 100kHz (Channels 3, 4, 5, and 6)
q
ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO DATA
q
DATA FORMATS: Standard, I
2
S, and Left-Justified
q
SYSTEM CLOCK: 128, 192, 256, 384, 512, or 768f
S
q
USER-PROGRAMMABLE FUNCTIONS:
Digital Attenuation: 0dB to 63dB, 0.5dB/Step
Soft Mute
Zero Flags May Be Used As General-
Purpose Logic Output
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow
q
DUAL-SUPPLY OPERATION:
+5V Analog, +3.3V Digital
q
+5V TOLERANT DIGITAL LOGIC INPUTS
q
PACKAGE: LQFP-48
APPLICATIONS
q
INTEGRATED A/V RECEIVERS
q
DVD MOVIE AND AUDIO PLAYERS
q
HDTV RECEIVERS
q
CAR AUDIO SYSTEMS
q
DVD ADD-ON CARDS FOR HIGH-END PCs
q
DIGITAL AUDIO WORKSTATIONS
q
OTHER MULTICHANNEL AUDIO SYSTEMS
PCM1608
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SBAS164A MARCH 2001
PCM1608
2
SBAS164A
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
Power Supply Voltage, V
DD
.............................................................. +4.0V
V
CC
.............................................................. +6.5V
Ground Voltage Differences ..............................................................
0.1V
Digital Input Voltage ................................................ 0.3V to (6.5V + 0.3V)
Input Current (except power supply) ...............................................
10mA
Operating Temperature Under Bias ................................ 40
C to +125
C
Storage Temperature ...................................................... 55
C to +150
C
Junction Temperature .................................................................... +150
C
Lead Temperature (soldering, 5s) ................................................. +260
C
Package Temperature (IR reflow, 10s) .......................................... +235
C
ABSOLUTE MAXIMUM RATINGS
PACKAGE
SPECIFIED
DRAWING
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
RANGE
MARKING
NUMBER
(1)
MEDIA
PCM1608Y
LQFP-48
340
25
C to +85
C
PCM1608Y
PCM1608Y
250-Piece Tray
"
"
"
"
"
PCM1608Y/2K
Tape and Reel
PCM1608KY
LQFP-48
340
25
C to +85
C
PCM1608KY
PCM1608KY
250-Piece Tray
"
"
"
"
"
PCM1608KY/2K
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of "PCM1608Y/2K" will get a single 2000-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
ELECTRICAL CHARACTERISTICS
All specifications at T
A
= +25
C, V
CC
= 5.0V, V
DD
= 3.3V, system clock = 384f
S
(f
S
= 44.1kHz), and 24-bit data, unless otherwise noted.
PCM1608Y
PCM1608KY
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
24
Bits
DATA FORMAT
Audio Data Interface Formats
Standard, I
2
S, Left-Justified
Audio Data Bit Length
16, 18, 20, 24-Bits Selectable
Audio Data Format
MSB-First, Binary Two's Complement
Sampling Frequency (f
S
)
V
OUT
1, 2, 7, 8
5
200
kHz
V
OUT
3, 4, 5, 6
5
100
kHz
System Clock Frequency
128, 192, 256, 384, 512, 768f
S
DIGITAL INPUT/OUTPUT
Logic Family
TTL-Compatible
Input Logic Level
V
IH
2.0
VDC
V
IL
0.8
VDC
Input Logic Current
I
IH
(1)
V
IN
= V
DD
10
A
I
IL
(1)
V
IN
= 0V
10
A
I
IH
(2)
V
IN
= V
DD
65
100
A
I
IL
(2)
V
IN
= 0V
10
A
Output Logic Level
V
OH
I
OH
= 4mA
2.4
VDC
V
OL
I
OL
= +4mA
1.0
VDC
DYNAMIC PERFORMANCE
(3) (4)
PCM1608Y
THD+N at V
OUT
= 0dB
f
S
= 44.1kHz
0.003
0.01
%
f
S
= 96kHz
0.005
%
f
S
= 192Hz
0.006
%
THD+N at V
OUT
= 60dB
f
S
= 44.1kHz
1.25
%
f
S
= 96kHz
1.40
%
f
S
= 192kHz
1.65
%
Dynamic Range
EIAJ, A-Weighted, f
S
= 44.1kHz
94
100
dB
A-Weighted, f
S
= 96kHz
99
dB
A-Weighted, f
S
= 192kHz
98
dB
Signal-to-Noise Ratio
EIAJ, A-Weighted, f
S
= 44.1kHz
94
100
dB
A-Weighted, f
S
= 96kHz
99
dB
A-Weighted, f
S
= 192kHz
98
dB
Channel Separation
f
S
= 44.1kHz
91
98
dB
f
S
= 96kHz
97
dB
f
S
= 192kHz
96
dB
Level Linearity Error
V
OUT
= 90dB
0.5
dB
PCM1608
3
SBAS164A
ELECTRICAL CHARACTERISTICS
(Cont.)
All specifications at T
A
= +25
C, V
CC
= 5.0V, V
DD
= 3.3V, system clock = 384f
S
(f
S
= 44.1kHz), and 24-bit data, unless otherwise noted.
PCM1608KY
THD+N at V
OUT
= 0dB
f
S
= 44.1kHz
0.002
0.008
%
f
S
= 96kHz
0.004
%
f
S
= 192kHz
0.005
%
THD+N at V
OUT
= 60dB
f
S
= 44.1kHz
0.7
%
f
S
= 96kHz
0.9
%
f
S
= 192kHz
1.0
%
Dynamic Range
EIAJ, A-Weighted, f
S
= 44.1kHz
98
105
dB
A-Weighted, f
S
= 96kHz
103
dB
A-Weighted, f
S
= 192kHz
102
dB
Signal-to-Noise Ratio
EIAJ, A-Weighted, f
S
= 44.1kHz
98
105
dB
A-Weighted, f
S
= 96kHz
103
dB
A-Weighted, f
S
= 192kHz
102
dB
Channel Separation
f
S
= 44.1kHz
94
103
dB
f
S
= 96kHz
101
dB
f
S
= 192kHz
100
dB
Level Linearity Error
V
OUT
= 90dB
0.5
dB
DC ACCURACY
Gain Error
1.0
6
% of FSR
Gain Mismatch, Channel-to-Channel
1.0
3
% of FSR
Bipolar Zero Error
V
OUT
= 0.5V
CC
at Bipolar Zero
30
60
mV
ANALOG OUTPUT
Output Voltage
Full Scale (0dB)
62% of V
CC
Vp-p
Center Voltage
50% V
CC
VDC
Load Impedance
AC Load
5
k
DIGITAL FILTER PERFORMANCE
Filter Characteristics 1, Sharp Roll-Off
Passband
0.03dB
0.454f
S
Passband
3dB
0.487f
S
Stopband
0.546f
S
dB
Passband Ripple
0.03
dB
Stopband Attenuation
Stopband = 0.546f
S
50
dB
Stopband Attenuation
Stopband = 0.567f
S
55
Filter Characteristics 2, Slow Roll-Off
Passband
0.5dB
0.198f
S
Passband
3dB
0.390f
S
Stopband
0.884f
S
Passband Ripple
0.5
dB
Stopband Attenuation
Stopband = 0.884f
S
40
dB
Delay Time
20/f
S
sec
De-Emphasis Error
0.1
dB
ANALOG FILTER PERFORMANCE
Frequency Response
f = 20kHz
0.03
dB
f = 44kHz
0.20
dB
POWER-SUPPLY REQUIREMENTS
(4)
Voltage Range, V
DD
+3.0
+3.3
+3.6
VDC
V
CC
+4.5
+5.0
+5.5
VDC
Supply Current, I
DD
(5)
f
S
= 44.1kHz
18
25
mA
f
S
= 96kHz
40
mA
f
S
= 192kHz
40
mA
I
CC
f
S
= 44.1kHz
33
46
mA
f
S
= 96kHz
36
mA
f
S
= 192kHz
36
mA
Power Dissipation
f
S
= 44.1kHz
224
313
mW
f
S
= 96kHz
312
mW
f
S
= 192kHz
312
mW
TEMPERATURE RANGE
Operation Temperature
25
+85
C
Thermal Resistance
JA
LQFP-48
100
C/W
NOTES: (1) Pins 31, 38, 40, 41, 45-47 (DATA4, SCKI, BCK, LRCK, DATA1, DATA2, DATA3). (2) Pins 34-37 (MDI, MC, ML, RST). (3) Analog performance
specifications are tested with a Shibasoku #725 THD Meter with 400Hz HPF on, 30kHz LPF on, average mode with 20kHz bandwidth limiting. The load
connected to the analog output is 5k
,
or larger, via capacitive loading. (4) Conditions in 192kHz operation are: system clock = 128f
S
, DAC3 through DAC6
disabled in Register 8, and oversampling rate = 64f
S
in Register 12. (5) CLKO is disabled.
PCM1608Y
PCM1608KY
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PCM1608
4
SBAS164A
PIN CONFIGURATION
Top View
LQFP
BLOCK DIAGRAM
Serial
Input
I/F
Output Amp and
Low-Pass Filter
DAC
4x/8x
Oversampling
Digital Filter
with
Function
Controller
Enhanced
Multi-Level
Delta-Sigma
Modulator
Output Amp and
Low-Pass Filter
DAC
Output Amp and
Low-Pass Filter
DAC
Output Amp and
Low-Pass Filter
DAC
Output Amp and
Low-Pass Filter
DAC
Output Amp and
Low-Pass Filter
DAC
Output Amp and
Low-Pass Filter
DAC
Output Amp and
Low-Pass Filter
DAC
BCK
LRCK
DATA1 (1,2)
DATA2 (3,4)
DATA3 (5,6)
DATA4 (7,8)
Function
Control
I/F
System Clock
Manager
Zero Detect
Power Supply
TEST
RST
ML
MC
MDI
MDO
V
OUT
1
V
OUT
2
V
OUT
5
V
OUT
6
V
OUT
7
V
OUT
8
V
OUT
3
V
OUT
4
V
COM
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
ZERO7
ZERO8
V
DD
DGND
ZEROA
SCKI
System Clock
SCKO
V
CC
1-5
AGND1-6
37
38
39
40
41
42
43
44
45
46
47
48
ML
MC
MDI
MDO
ZERO8
DATA4
ZERO7
NC
V
CC
1
AGND1
V
CC
2
AGND2
RST
SCKI
SCKO
BCK
LRCK
TEST
V
DD
DGND
DATA1
DATA2
DATA3
ZEROA
V
CC
3
AGND3
V
CC
4
AGND4
V
OUT
8
AGND6
V
CC
5
AGND5
V
OUT
7
V
COM
V
OUT
1
V
OUT
2
24
23
22
21
20
19
18
17
16
15
14
13
ZERO1/GPO1
ZERO2/GPO2
ZERO3/GPO3
ZERO4/GPO4
ZERO5/GPO5
ZERO6/GPO6
NC
NC
V
OUT
6
V
OUT
5
V
OUT
4
V
OUT
3
36
35
34
33
32
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
10
11
25
12
PCM1608
PCM1608
5
SBAS164A
P I N
N A M E
I / O
DESCRIPTION
1
ZERO1/GPO1
O
Zero Data Flag for V
OUT
1. Can also be used as GPO pin.
2
ZERO2/GPO2
O
Zero Data Flag for V
OUT
2. Can also be used as GPO pin.
3
ZERO3/GPO3
O
Zero Data Flag for V
OUT
3. Can also be used as GPO pin.
4
ZERO4/GPO4
O
Zero Data Flag for V
OUT
4. Can also be used as GPO pin.
5
ZERO5/GPO5
O
Zero Data Flag for V
OUT
5. Can also be used as GPO pin.
6
ZERO6/GPO6
O
Zero Data Flag for V
OUT
6. Can also be used as GPO pin.
7
NC
--
No Connection
8
NC
--
No Connection
9
V
OUT
6
O
Voltage Output of Audio Signal Corresponding to Rch on DATA3. Up to 96kHz.
10
V
OUT
5
O
Voltage Output of Audio Signal Corresponding to Lch on DATA3. Up to 96kHz.
11
V
OUT
4
O
Voltage Output of Audio Signal Corresponding to Rch on DATA2. Up to 96kHz.
12
V
OUT
3
O
Voltage Output of Audio Signal Corresponding to Lch on DATA2. Up to 96kHz.
13
V
OUT
2
O
Voltage Output of Audio Signal Corresponding to Rch on DATA1. Up to 192kHz.
14
V
OUT
1
O
Voltage Output of Audio Signal Corresponding to Lch on DATA1. Up to 192kHz.
15
V
COM
O
Common Voltage Output. This pin should be bypassed with a 10
F capacitor to AGND.
16
V
OUT
7
O
Voltage Output for Audio Signal Corresponding to Lch on DATA4. Up to 192kHz.
17
AGND5
--
Analog Ground
18
V
CC
5
--
Analog Power Supply, +5V
19
AGND6
--
Analog Ground
20
V
OUT
8
--
Voltage Output for Audio Signal Corresponding to Rch on DATA4. Up to 192kHz.
21
AGND4
--
Analog Ground
22
V
CC
4
--
Analog Power Supply, +5V
23
AGND3
--
Analog Ground
24
V
CC
3
--
Analog Power Supply, +5V
25
AGND2
--
Analog Ground
26
V
CC
2
--
Analog Power Supply, +5V
27
AGND1
--
Analog Ground
28
V
CC
1
--
Analog Power Supply, +5V
29
NC
--
No Connection
30
ZERO7
--
Zero Data Flag for V
OUT
7
31
DATA4
--
Serial Audio Data Input for V
OUT
7 and V
OUT
8
(2)
32
ZERO8
--
Zero Data Flag for V
OUT
8
33
MDO
O
Serial Data Output for Serial Control Port
(3)
34
MDI
I
Serial Data Input for Serial Control Port
(1)
35
MC
I
Shift Clock for Serial Control Port
(1)
36
ML
I
Latch Enable for Serial Control Port
(1)
37
RST
I
System Reset, Active LOW
(1)
38
SCKI
I
System Clock Input. Input frequency is 128, 192, 256, 384, 512, or 768f
S
.
(2)
39
SCKO
O
Buffered Clock Output. Output frequency is 128, 192, 256, 384, 512, or 768f
S
, or one-half of 128, 192, 256, 384, 512, or 768f
S.
40
BCK
I
Shift Clock Input for Serial Audio Data. Clock must be 32, 48, or 64f
S
.
(2)
41
LRCK
I
Left and Right Clock Input. This clock is equal to the sampling rate, f
S
.
(2)
42
TEST
--
Test Pin. This pin should be connected to DGND.
(1)
43
V
DD
--
Digital Power Supply, +3.3V
44
DGND
--
Digital Ground
45
DATA1
I
Serial Audio Data Input for V
OUT
1 and V
OUT
2
(2)
46
DATA2
I
Serial Audio Data Input for V
OUT
3 and V
OUT
4
(2)
47
DATA3
I
Serial Audio Data Input for V
OUT
5 and V
OUT
6
(2)
48
ZEROA
O
Zero Data Flag. Logical "AND" of ZERO1 through ZERO6.
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output.
PIN ASSIGNMENTS
PCM1608
6
SBAS164A
TYPICAL CHARACTERISTICS
All specifications at T
A
= +25
C, V
CC
= 5.0V, V
DD
= 3.3V, system clock = 384f
S
(f
S
= 44.1kHz), and 24-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off, f
S
= 44.1kHz)
De-Emphasis and De-Emphasis Error
0
20
40
60
80
100
120
140
FREQUENCY RESPONSE (Sharp Roll-Off)
0
1
2
3
4
Frequency (x f
S
)
Amplitude (dB)
0.05
0.04
0.03
0.02
0.01
0
0.01
0.02
0.03
0.04
0.05
FREQUENCY RESPONSE PASSBAND
(Sharp Roll-Off)
0
0.1
0.2
0.3
0.4
0.5
Frequency (x f
S
)
Amplitude (dB)
0
20
40
60
80
100
120
140
FREQUENCY RESPONSE (Slow Roll-Off)
0
1
2
3
4
Frequency (x f
S
)
Amplitude (dB)
5
4
3
2
1
0
1
2
3
4
5
TRANSITION CHARACTERISTICS (Slow Roll-Off)
0
0.1
0.2
0.3
0.4
0.5
Frequency (x f
S
)
Amplitude (dB)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
DE-EMPHASIS (f
S
= 32kHz)
0
2
4
6
8
10
12
14
Frequency (kHz)
Level (dB)
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
DE-EMPHASIS ERROR (f
S
= 32kHz)
0
2
4
6
8
10
12
14
Frequency (kHz)
Error (dB)
PCM1608
7
SBAS164A
TYPICAL CHARACTERISTICS
(Cont.)
All specifications at T
A
= +25
C, V
CC
= 5.0V, V
DD
= 3.3V, system clock = 384f
S
(f
S
= 44.1kHz), and 24-bit input data, unless otherwise noted.
De-Emphasis and De-Emphasis Error
(Cont.)
ANALOG DYNAMIC PERFORMANCE
All specifications at T
A
= +25
C, V
CC
= 5.0V, V
DD
= 3.3V, and 24-bit input data, unless otherwise noted. Conditions in 192kHz operation are: system clock = 128f
S
,
DAC3 through DAC6 = disable of Register 8, and oversampling rate = 64f
S
of Redister 12.
Supply-Voltage Characteristics
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
DE-EMPHASIS (f
S
= 44.1kHz)
0
2
4
6
8
10
12
14
16
18
20
Frequency (kHz)
Level (dB)
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
DE-EMPHASIS ERROR (f
S
= 44.1kHz)
0
2
4
6
8
10
12
14
16
18
20
Frequency (kHz)
Error (dB)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
DE-EMPHASIS (f
S
= 48kHz)
Frequency (kHz)
Level (dB)
0
2
4
6
8
10
12
14
16
18
22
20
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
0.5
DE-EMPHASIS ERROR (f
S
= 48kHz)
0
2
4
6
8
10
12
14
16
18
22
20
Frequency (kHz)
Error (dB)
10
1
0.1
0.01
0.001
0.0001
THD+N vs V
CC
(V
DD
= 3.3V)
4
4.5
5
5.5
6
V
CC
(V)
THD+N (%)
60dB/96kHz, 384f
S
60dB/44.1kHz, 384f
S
60dB/192kHz, 384f
S
0dB/96kHz, 384f
S
0dB/192kHz, 384f
S
0dB/44.1kHz, 384f
S
110
108
106
104
102
100
98
96
DYNAMIC RANGE vs V
CC
(V
DD
= 3.3V)
4
4.5
5
5.5
6
V
CC
(V)
Dynamic Range (dB)
44.1kHz, 384f
S
192kHz, 384f
S
96kHz, 384f
S
PCM1608
8
SBAS164A
TYPICAL CHARACTERISTICS
(Cont.)
All specifications at T
A
= +25
C, V
CC
= 5.0V, V
DD
= 3.3V, and 24-bit input data, unless otherwise noted. Conditions in 192kHz operation are: system clock = 128f
S
,
DAC3 through DAC6 = disable of Register 8, and oversampling rate = 64f
S
of Redister 12.
Supply-Voltage Characteristics
(Cont.)
Temperature Characteristics
110
108
106
104
102
100
98
96
SNR vs V
CC
(V
DD
= 3.3V)
4
4.5
5
5.5
6
V
CC
(V)
SNR (dB)
96kHz, 384f
S
44.1kHz, 384f
S
192kHz, 384f
S
110
108
106
104
102
100
98
96
CHANNEL SEPARATION vs V
CC
(V
DD
= 3.3V)
4
4.5
5
5.5
6
V
CC
(V)
Channel Separation (dB)
96kHz, 384f
S
44.1kHz, 384f
S
192kHz, 384f
S
10
1
0.1
0.01
0.001
0.0001
THD+N vs T
A
50
25
0
25
50
75
100
Temperature (
C)
THD+N (%)
60dB/192kHz, 384f
S
60dB/96kHz, 384f
S
60dB/44.1kHz, 384f
S
0dB/192kHz, 384f
S
0dB/96kHz, 384f
S
0dB/44.1kHz, 384f
S
110
108
106
104
102
100
98
96
DYNAMIC RANGE vs T
A
50
25
0
25
50
75
100
Temperature (
C)
Dynamic Range (dB)
44.1kHz, 384f
S
96kHz, 384f
S
192kHz, 384f
S
110
108
106
104
102
100
98
96
SNR vs T
A
50
25
0
25
50
75
100
Temperature (
C)
SNR (dB)
44.1kHz, 384f
S
96kHz, 384f
S
192kHz, 384f
S
110
108
106
104
102
100
98
96
CHANNEL SEPARATION vs T
A
50
25
0
25
50
75
100
Temperature (
C)
Channel Separation (dB)
44.1kHz, 384f
S
192kHz, 384f
S
96kHz, 384f
S
PCM1608
9
SBAS164A
FIGURE 2. Power-On Reset Timing.
1024 System Clocks
Reset
Reset Removal
V
DD
Internal Reset
2.4V
2.0V
1.6V
0V
System Clock
Don't Care
FIGURE 1. System Clock Timing.
SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1608 requires a system clock for operating the
digital interpolation filters and multilevel delta-sigma modu-
lators. The system clock is applied at the SCKI input (pin 38).
Table I shows examples of system clock frequencies for
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. The PLL1700 multi-
clock generator from Texas Instruments is an excellent
choice for providing the PCM1608 system clock.
The 192kHz sampling frequency operation is available on
DATA1 for V
OUT
1 and V
OUT
2, and DATA4 for V
OUT
7 and
V
OUT
8. It is recommended that V
OUT
3, V
OUT
4, V
OUT
5, and
V
OUT
6 be disabled when operating with f
S
= 192kHz. This
is done by setting the DAC3, DAC4, DAC5, and DAC6 bits
of Register 9 to a "1" state.
SYSTEM CLOCK OUTPUT
A buffered version of the system clock input is available at
the SCKO output (pin 39). SCKO can operate at either full
(f
SCKI
) or half (f
SCKI
/2) rate. The SCKO output frequency
may be programmed using the CLKE bit of Register 9. If the
SCKO output is not required, it is recommended to disable
it using the CLKE bit. The default is SCKO enabled.
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1608 includes a power-on reset function, as shown
in Figure 2. With the system clock active, and V
DD
> 2.0V
(typical, 1.6V to 2.4V), the power-on reset function will be
enabled. The initialization sequence requires 1024 system
clocks from the time V
DD
> 2.0V. After the initialization
period, the PCM1608 will be set to its reset default state, as
described in the Mode Control Register section of this data
sheet.
The PCM1608 also includes an external reset capability
using the RST input (pin 37). This allows an external
SAMPLING
FREQUENCY
128f
S
192f
S
256f
S
384f
S
512f
S
768f
S
8kHz
--
--
2.0480
3.0720
4.0960
6.1440
16kHz
--
--
4.0960
6.1440
8.1920
12.2880
32kHz
--
--
8.1920
12.2880
16.3840
24.5760
44.1kHz
--
--
11.2896
16.9344
22.5792
33.8688
48kHz
--
--
12.2880
18.4320
24.5760
36.8640
96kHz
--
--
24.5760
36.8640
49.1520
(1)
192kHz
24.5760
36.8640
(2)
(2)
(2)
(2)
NOTES: (1) The 768f
S
system clock rate is not supported for f
S
> 64kHz. (2) This system clock is not supported for the given sampling frequency.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
SYSTEM CLOCK FREQUENCY (f
SCLK
) (MHz)
t
SCKH
t
SCKL
System Clock Pulse Width HIGH t
SCKH
: 7ns (min)
System Clock Pulse Width LOW t
SCKL
: 7ns (min)
NOTE: (1) 1/128f
S
, 1/256f
S
, 1/384f
S
, 1/512f
S
, and 1/768f
S
.
2.0V
0.8V
System Clock
System Clock
Pulse Cycle Time
(1)
PCM1608
10
SBAS164A
controller or master reset circuit to force the PCM1608 to
initialize to its reset default state. For normal operation,
RST should be set to a logic "1".
The external reset operation and timing is shown in Figure 3.
The RST pin is set to logic "0" for a minimum of 20ns.
After the initialization sequence is completed, the PCM1608
will be set to its reset default state, as described in the
Mode Control Registers section of this data sheet.
During the reset period (1024 system clocks), the analog
outputs are forced to the bipolar zero level (or V
CC
/2).
After the reset period, the internal registers are initialized
in the next 1/f
S
period and, if SCKI, BCK, and LRCK are
provided continuously, the PCM1608 provides proper ana-
log output with unit-group delay, as specified in this data
sheet.
The external reset is especially useful in applications
where there is a delay between PCM1608 power-up and
system clock activation. In this case, the RST pin should
be held at a logic "0" level until the system clock has been
activated.
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1608 is comprised of
a 5-wire synchronous serial port. It includes LRCK (pin 41),
BCK (pin 40), DATA1 (pin 45), DATA2 (pin 46), DATA3
(pin 47), and DATA4 (pin 31). BCK is the serial audio bit
clock, and is used to clock the serial data present on
DATA1, DATA2, DATA3, and DATA4 into the audio
interface's serial shift register. Serial data is clocked into
the PCM1608 on the rising edge of BCK. LRCK is the
serial audio left/right word clock. It is used to latch serial
data into the serial audio interface's internal registers.
Both LRCK and BCK must be synchronous to the system
clock. Ideally, it is recommended that LRCK and BCK be
derived from the system clock input, SCKI. LRCK is
operated at the sampling frequency (f
S
). BCK may be
operated at 32, 48, or 64 times the sampling frequency (I
2
S
format does not support BCK = 32f
S
).
Internal operation of the PCM1608 is synchronized with
LRCK. Accordingly, it is held when the sampling rate clock
of LRCK is changed, or SCKI and/or BCK is broken at least
for one clock cycle. If SCKI, BCK, and LRCK are provided
continuously after this hold condition, the internal operation
will be resynchronized automatically, less than 3/f
S
period. In
this resynchronize period, and following 3/f
S
, the analog
outputs are forced to the bipolar zone level (or V
CC
/2).
External resettling is not required.
AUDIO DATA FORMATS AND TIMING
The PCM1608 supports industry-standard audio data formats,
including Standard, I
2
S, and Left-Justified (see Figure 4).
Data formats are selected using the format bits, FMT[2:0], in
Register 9. The default data format is 24-bit Standard. All
formats require Binary Two's Complement, MSB-first audio
data. See Figure 5 for a detailed timing diagram of the serial
audio interface.
DATA1, DATA2, DATA3, and DATA4 each carry two audio
channels, designated as the Left and Right channels. The Left
channel data always precedes the Right channel data in the
serial data stream for all data formats. Table II shows the
mapping of the digital input data to the analog output pins.
DATA INPUT
CHANNEL
ANALOG OUTPUT
DATA1
Left
V
OUT
1
(1)
DATA1
Right
V
OUT
2
(1)
DATA2
Left
V
OUT
3
(2)
DATA2
Right
V
OUT
4
(2)
DATA3
Left
V
OUT
5
(2)
DATA3
Right
V
OUT
6
(2)
DATA4
Left
V
OUT
7
(1)
DATA4
Right
V
OUT
8
(1)
NOTES: (1) Up to 192kHz. (2) Up to 96kHz, forced to bipolar zero when
f
S
= 96kHz.
TABLE II. Audio Input Data to Analog Output Mapping.
FIGURE 3. External Reset Timing.
1024 System Clocks
Reset
Reset Removal
System Clock
Internal Reset
RST
PCM1608
11
SBAS164A
FIGURE 4. Audio Data Input Formats.
1/f
S
L-Channel
R-Channel
LRCK
BCK
(= 48f
S
or 64f
S
)
18-Bit Right-Justified
DATA
DATA
(2) I
2
S Data Format: L-Channel = LOW, R-Channel = HIGH
(3) Left-Justified Data Format: L-Channel = HIGH, R-Channel = LOW
(1) Standard Data Format: L-Channel = HIGH, R-Channel = LOW
1/f
S
L-Channel
R-Channel
LRCK
BCK
(= 32f
S
, 48f
S
or 64f
S
)
1
2
3
N-2 N-1 N
1
2
1
2
3
N-2 N-1 N
1/f
S
L-Channel
R-Channel
LRCK
BCK
(= 32f
S
, 48f
S
or 64f
S
)
2
1
1
2
3
N-2 N-1 N
1
2
3
N-2 N-1 N
14 15 16
16 17 18
18 19 20
14 15 16
1
2
3
DATA
22 23 24
22 23 24
1
2
3
DATA
18 19 20
1
2
3
DATA
16 17 18
1
2
3
DATA
24-Bit Right-Justified
14 15 16
1
2
3
22 23 24
1
2
3
18 19 20
1
2
3
17 18
1
2
20-Bit Right-Justified
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
14 15 16
14 15 16
1
2
3
DATA
16-Bit Right-Justified, BCK = 32f
S
14 15 16
1
2
3
LSB
MSB
LSB
MSB
16-Bit Right-Justified, BCK = 48f
S
or 64f
S
SERIAL CONTROL INTERFACE
The serial control interface is a 4-wire synchronous serial
port that operates asynchronously to the serial audio inter-
face. The serial control interface is utilized to program and
read the on-chip mode registers. The control interface in-
cludes MDO (pin 33), MDI (pin 34), MC (pin 35), and ML
(pin 36). MDO is the serial data output, used to read back the
values of the mode registers; MDI is the serial data input,
used to program the mode registers; MC is the serial bit
clock, used to shift data in and out of the control port; and
ML is the control port latch clock.
PCM1608
12
SBAS164A
REGISTER WRITE OPERATION
All Write operations for the serial control port use 16-bit
data words. Figure 6 shows the control data word format.
The most significant bit is the Read/Write (R/W) bit. When
set to "0", this bit indicates a Write operation. There are
seven bits, labeled IDX[6:0], that set the register index (or
address) for the Write operation. The least significant eight
bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
Figure 7 shows the functional timing diagram for writing the
serial control port. ML is held at a logic "1" state until a
register needs to be written. To start the register write cycle,
ML is set to logic "0". Sixteen clocks are then provided on
MC, corresponding to the 16-bits of the control data word on
MDI. After the sixteenth clock cycle has completed, ML is
set to logic "1" to latch the data into the indexed mode
control register.
SINGLE REGISTER READ OPERATION
Read operations utilize the 16-bit control word format shown
in Figure 6. For Read operations, the R/W bit is set to "1".
Read operations ignore the index bits, IDX[6:0], of the
control data word. Instead, the REG[6:0] bits in Control
Register 11 are used to set the index of the register that is to
be read during the Read operation. Bits IDX[6:0] should be
set to 00
H
for Read operations.
FIGURE 5. Audio Interface Timing.
SYMBOL
PARAMETER
MIN
MAX
UNITS
t
BCY
BCK Pulse Cycle Time
32, 48, or 64f
S
(1)
t
BCH
BCK High Level Time
35
ns
t
BCL
BCK Low Level Time
35
ns
t
BL
BCK Rising Edge to LRCK Edge
10
ns
t
LB
LRCK Falling Edge to BCK Rising Edge
10
ns
t
DS
DATA Set Up Time
10
ns
t
DH
DATA Hold Time
10
ns
NOTE: (1) f
S
is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
LRCK
BCK
DATA1,DATA2,
DATA3, DATA4
50% of V
DD
50% of V
DD
50% of V
DD
t
BCH
t
BCL
t
LB
t
BL
t
DS
t
DH
t
BCY
FIGURE 6. Control Data Word Format for MDI.
IDX5
IDX6
R/W
IDX4
IDX2
IDX3
IDX1
IDX0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
Register Index (or Address)
Read/Write Operation
0 = Write Operation
1 = Read Operation (register index is ignored)
Register Data
LSB
FIGURE 7. Write Operation Timing.
R/W
D7
D6
D5
D4
D3
D2
RW IDX6
D1
D0
X
X
X
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
ML
MC
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