49%

FPO

PCM1801

FEATURES

DUAL 16-BIT MONOLITHIC

ADC

SINGLE-ENDED VOLTAGE INPUT

64X OVERSAMPLING DECIMATION FILTER:
Passband Ripple:

0.05dB

Stopband Attenuation: 65dB

ANALOG PERFORMANCE:
THD+N: 88dB (typ)
SNR: 93dB (typ)
Dynamic Range: 93dB (typ)
Internal High-Pass Filter

PCM AUDIO INTERFACE: Left Justified, I

SAMPLING RATE: 4kHz to 48kHz

16-Bit, Stereo, Audio

ANALOG-TO-DIGITAL CONVERTER

PCM1801

Clock/Timing Control

BYPAS

AGND

Reference

Format
Control

FMT

SCKI

Serial Data

Interface

DOUT

BCK

LRCK

REF

Power Supply

DGND

()

(+)

x1/64

Decimation

and

High-Pass Filter

5th-Order

Modulator

5th-Order

Modulator

PCM1801

(+)

()

Single-Ended-

to-Differential

Converter

Single-Ended-

to-Differential

Converter

www.ti.com

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SBAS131A MAY 2001

SYSTEM CLOCK: 256f

, 384f

, or 512f

SINGLE +5V POWER SUPPLY

SMALL SO-14 PACKAGE

DESCRIPTION

PCM1801 is a low-cost, single chip stereo Analog-to-Digital
Converter (ADC) with single-ended analog voltage inputs.
The PCM1801 uses a delta-sigma modulator with 64x
oversampling, a digital decimation filter, and a serial inter-
face which supports Slave mode operation and two data
formats. The PCM1801 is suitable for a wide variety of cost-
sensitive consumer applications where good performance is
required.

PCM1801

SBAS131A

PIN CONFIGURATION

PIN

NAME

I/O

DESCRIPTION

Analog Input, Lch.

Analog Input, Rch.

DGND

Digital Ground

Digital Power Supply

SCKI

System Clock Input; 256f

, 384f

, or 512f

BCK

Bit Clock Input

LRCK

Sampling Clock Input

DOUT

OUT

Audio Data Output

BYPAS

HPF Bypass Control

(1)

L: HPF Enabled

H: HPF Disabled

FMT

Audio Data Format

(1)

L: MSB-First, Left-Justified

H: MSB-First, I

Analog Power Supply

AGND

Analog Ground

REF

Reference 2 Decoupling Capacitor

REF

Reference 1 Decoupling Capacitor

NOTE: (1) With 100k

typical pull-down resistor.

PIN ASSIGNMENTS

Top View

Supply Voltage: +V

DD,

.............................................................. +6.5V

Supply Voltage Differences ...............................................................

0.1V

GND Voltage Differences ..................................................................

0.1V

Digital Input Voltage ................................................. 0.3V to (V

+ 0.3V)

Analog Input Voltage ................................................ 0.3V to (V

+ 0.3V)

Input Current (any pin except supplies) ..........................................

10mA

Power Dissipation .......................................................................... 300mW
Operating Temperature Range ......................................... 25

C to +85

Storage Temperature ...................................................... 55

C to +125

Lead Temperature (soldering, 5s) .................................................. +260

(reflow, 10s) ..................................................... +235

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled
withappropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE

SPECIFIED

DRAWING

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE

NUMBER

RANGE

MARKING

NUMBER

(1)

MEDIA

PCM1801U

SO-14

235

C to +85

PCM1801U

Rails

PCM1801U/2K

Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of "PCM1801U/2K" will get a single 2000-piece Tape and Reel.

PACKAGE/ORDERING INFORMATION

DGND

SCKI

BCK

LRCK

REF

AGND

FMT

BYPAS

DOUT

PCM1801U

PCM1801

SBAS131A

ELECTRICAL CHARACTERISTICS

All specifications at +25

C, +V

= +V

= +5V, f

= 44.1kHz, and 16-bit data, SYSCLK = 384f

, unless otherwise noted.

PCM1801U

PARAMETER

CONDITIONS MIN

TYP MAX UNITS

RESOLUTION

16 Bits

DIGITAL INPUT/OUTPUT
Input Logic Level:

(1)

2.0

(1)

0.8 V

Input Logic Current:

(2)

(3)

+100

Output Logic Level:

(4)

= 1.6mA 4.5

(4)

= +3.2mA

0.5 V

Sampling Frequency

44.1 48 kHz

System Clock Frequency

256f

1.024

11.2896 12.2880 MHz

384f

1.536

16.9344 18.4320 MHz

512f

2.024

22.5792 24.5760 MHz

DC ACCURACY
Gain Mismatch Channel-to-Channel

1.0

2.5 % of FSR

Gain Error

2.0

5.0 % of FSR

Gain Drift

20 ppm of FSR/

Bipolar Zero Error

High-Pass Filter Bypass

2.0 % of FSR

Bipolar Zero Drift

High-Pass Filter Bypass

20 ppm of FSR/

DYNAMIC PERFORMANCE

(5)

THD+N at FS (0.5dB)

88 80 dB

THD+N at 60dB

90 dB

Dynamic Range

EIAJ, A-weighted 90

93 dB

Signal-To-Noise Ratio

EIAJ, A-weighted 90

93 dB

Channel Separation

91 dB

ANALOG INPUT
Input Range

FS (V

= 0dB)

2.828 Vp-p

Center Voltage

2.1 V

Input Impedance

30 k

Anti-Aliasing Filter Frequency Response

3dB

170 kHz

DIGITAL FILTER PERFORMANCE
Passband

0.454f

Stopband

0.583f

Passband Ripple

0.05 dB

Stopband Attenuation

Delay Time (Latency)

17.4/f

sec

High Pass Frequency Response

3dB

0.019f

mHz

POWER SUPPLY REQUIREMENTS
Voltage Range

+4.5

+5.0 +5.5 VDC

+4.5

+5.0 +5.5 VDC

Supply Current

(6)

= +V

= +5V

18 25 mA

Power Dissipation

= +V

= +5V

90 125 mW

TEMPERATURE RANGE
Operation

+85

Storage

+125

Thermal Resistance,

100

C/W

NOTES: (1) Pins 5, 6, 7, 9, and 10 (SCKI, BCK, LRCK, BYPAS, FMT). (2) Pins 5, 6, 7 (SCKI, BCK, LRCK) Schmitt-Trigger input. (3) Pins 9, 10 (BYPAS, FMT)
Schmitt-Trigger input with 100k

typical pull-down resistor). (4) Pin 8 (DOUT). (5) f

= 1kHz, using Audio Precisions System II, r ms Mode with 20kHz LPF

and 400Hz HPF enabled. (6) No load on DOUT (pin 8).

PCM1801

SBAS131A

TYPICAL CHARACTERISTICS

At T

= +25

C, +V

= +V

= +5V, f

= 44.1kHz, and SYSCLK = 384f

, unless otherwise noted.

ANALOG DYNAMIC PERFORMANCE

TOTAL HARMONIC DISTORTION + NOISE

vs TEMPERATURE

Temperature (

THD+N at

0.5dB (%)

0.006

0.005

0.004

0.003

0.002

100

THD+N at

60dB (%)

3.0

2.8

2.6

2.4

2.2

60dB

0.5dB

SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE

vs TEMPERATURE

Temperature (

SNR (dB)

75 85

100

Dynamic Range (dB)

SNR

Dynamic Range

TOTAL HARMONIC DISTORTION + NOISE

vs SUPPLY VOLTAGE

Supply Voltage

(V)

THD+N at

0.5dB (%)

0.006

0.005

0.004

0.003

0.002

4.5

4.75

5.0

5.25

5.5

THD+N at

60dB (%)

3.0

2.8

2.6

2.4

2.2

60dB

0.5dB

SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE

vs SUPPLY VOLTAGE

SNR (dB)

Dynamic Range (dB)

SNR

Supply Voltage

(V)

4.5

4.75

5.0

5.25

5.5

Dynamic Range

TOTAL HARMONIC DISTORTION + NOISE

vs SAMPLING RATE

Sampling Rate (kHz)

THD+N at

0.5dB (%)

0.006

0.005

0.004

0.003

0.002

44.1

THD+N at

60dB (%)

3.0

2.8

2.6

2.4

2.2

60dB

0.5dB

SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE

vs SAMPLING RATE

Sampling Rate (kHz)

SNR (dB)

44.1

Dynamic Range (dB)

Dynamic Range

SNR

PCM1801

SBAS131A

TYPICAL CHARACTERISTICS

(Cont.)

At T

= +25

C, +V

= +V

= +5V, f

= 44.1kHz, and SYSCLK = 384f

, unless otherwise noted.

DIGITAL FILTER

OVERALL CHARACTERISTICS

Normalized Frequency (x f

Hz)

Amplitude (dB)

100

150

200

STOPBAND ATTENUATION CHARACTERISTICS

Normalized Frequency (x f

Hz)

Amplitude (dB)

100

0.25

0.50

0.75

1.00

PASSBAND RIPPLE CHARACTERISTICS

Normalized Frequency (x f

Hz)

Amplitude (dB)

0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.1

0.3

0.2

0.4

0.5

TRANSITION BAND CHARACTERISTICS

Normalized Frequency (x f

Hz)

Amplitude (dB)

0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55

0.45

HIGH PASS FILTER RESPONSE

Normalized Frequency (x f

/1000Hz)

Amplitude (dB)

100

0.1

0.05

0.2

0.15

0.3

0.25

0.4

-0.35

HIGH PASS FILTER RESPONSE

Normalized Frequency (x f

/1000Hz)

Amplitude (dB)

0.2

0.0

0.2

0.4

0.6

0.8

1.0

0.5

2.0

1.5

3.0

2.5

4.0

3.5

PCM1801

SBAS131A

THEORY OF OPERATION

PCM1801 consists of a bandgap reference, two channels of
a single-to-differential converter, a fully differential 5th-
order delta-sigma modulator, a decimation filter (including
digital high pass), and a serial interface circuit. The Block
Diagram illustrates the total architecture of PCM1801, the
Analog Front-End diagram illustrates the architecture of the
single-to-differential converter, and the anti-aliasing filter is
illustrated in the Block Diagram. Figure 1 illustrates the
architecture of the 5th-order delta-sigma modulator and
transfer functions.

An internal high precision reference with two external capaci-
tors provides all reference voltages which are required by the
converter, and defines the full-scale voltage range of both
channels. The internal single-ended to differential voltage
converter saves the design, space and extra parts needed for
external circuitry required by many delta-sigma converters.
The internal full differential architecture provides a wide
dynamic range and excellent power supply rejection perfor-
mance.

The input signal is sampled at 64x oversampling rate,
eliminating the need for a sample-and-hold circuit, and
simplifying anti-alias filtering requirements. The 5th-order
delta-sigma noise shaper consists of five integrators which
use a switched-capacitor topology, a comparator and a
feedback loop consisting of a 1-bit DAC (Digital-to-Analog
Converter). The delta-sigma modulator shapes the quantiza-
tion noise, shifting it out of the audio band in the frequency
domain. The high order of the modulator enables it to
randomize the modulator outputs, reducing idle tone levels.

The 64f

, 1-bit stream from the modulator is converted to

, 16-bit digital data by the decimation filter, which also

acts as a low-pass filter to remove the shaped quantization
noise. The DC components are removed by a digital high-
pass filter, and the filtered output is converted to time-
multiplexed serial signals through a serial interface which
provides flexible serial formats.

SYSTEM CLOCK

The system clock for PCM1801 must be either 256f

, 384f

or 512f

, where f

is the audio sampling frequency. The

system clock must be supplied on SCKI (pin 5).

PCM1801 also has a system clock detection circuit which
automatically senses if the system clock is operating at
256f

, 384f

, or 512f

When 384f

and 512f

system clock are used, the PCM1801

automatically divides these clocks down to 256f

internally.

This 256f

clock is used to operate the digital filter and the

modulator. Table I lists the relationship of typical sampling
frequencies and system clock frequencies. Figure 2 illus-
trates the system clock timing.

FIGURE 1. Simplified Diagram of the PCM1801 5th-Order Delta-Sigma Modulator.

FIGURE 2. System Clock Timing.

SYSTEM CLOCK FREQUENCY

(MHz)

256f

384f

512f

8.1920

12.2880

16.3840

44.1

11.2896

16.9340

22.5792

12.2880

18.4320

24.5760

TABLE I. System Clock Frequencies.

SAMPLING RATE FREQUENCY

(kHz)

5th SW-CAP

Integrator

4th SW-CAP

Integrator

3rd SW-CAP

Integrator

2nd SW-CAP

Integrator

1st SW-CAP

Integrator

1-Bit
DAC

H(z)

Qn(z)

Analog In

X(z)

Digital Out

Y(z)

Y(z) = STF(z) · X(z) + NTF(z) · Qn(z)
Signal Transfer Function
Noise Transfer Function

STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1/ [1 + H(z)]

Comparator

CLKIH

System Clock Pulse Width High

CLKIH

12ns (min)

System Clock Pulse Width Low

CLKIL

12ns (min)

CLKIL

SCKI

2.0V

0.8V

PCM1801

SBAS131A

RESET

PCM1801 has an internal power-on reset circuit, which ini-
tializes (resets) when the supply voltage (V

) exceeds

4.0V (typ). The PCM1801 stays in the reset state and the
digital output is forced to zero. The digital output is valid after
reset state release and 18436f

periods. During reset, the logic

circuits and the digital filter stop operating. Figure 3 illustrates
the internal power-on reset timing.

FIGURE 3. Internal Power-On Reset Timing.

1024 System Clock Periods

Reset

Reset Removal

4.4V
4.0V
3.6V

Internal Reset

System Clock

FMT

DATA FORMAT

0 (L)

16-Bit, Left-Justified

1 (H)

16-Bit, I

TABLE II. Data Format.

FIGURE 4. Audio Data Format.

Lch

Rch

FMT = L

FMT = H

16-Bit, MSB-First, Left-Justified

MSB

LSB

LRCK

BCK

DOUT

MSB

LSB

14 15 16

L-ch

R-ch

16-Bit, MSB-First, I

MSB

LSB

LRCK

BCK

DOUT

MSB

LSB

14 15 16

SERIAL AUDIO DATA INTERFACE

The PCM1801 interfaces the audio system through BCK (pin
6), LRCK (pin 7), and DOUT (pin 8).

DATA FORMAT

PCM1801 supports two audio data formats in Slave Mode,
and are selected by the FMT control input (pin 10) as shown
in Table II.

PCM1801

SBAS131A

SYNCHRONIZATION WITH
DIGITAL AUDIO SYSTEM

PCM1801 operates with LRCK synchronized to the system
clock (SCKI). PCM1801 does not require a specific phase
relationship between LRCK and SCKI, but does require the
synchronization of LRCK and SCKI. If the relationship
between LRCK and SCKI changes more than 6 bit clocks
(BCK) during one sample period due to LRCK or SCKI
jitter, internal operation of the ADC halts within 1/f

and the

digital output is forced to BPZ until resynchronization be-
tween LRCK and SCKI is completed. In case of changes less
than 5 bit clocks (BCK), resynchronization does not occur
and above digital output control and discontinuity does not
occur. During undefined data, it may generate some noise in
the audio signal. Also, the transition of normal to undefined
data and undefined or zero data to normal makes a discon-
tinuity of data on the digital output, and may generate some
noise in the audio signal.

BOARD DESIGN AND LAYOUT
CONSIDERATIONS

, V

PINS

The digital and analog power supply lines to the PCM1801
should be bypassed to the corresponding ground pins with both
0.1

F and 10

F capacitors as close to the pins as possible to

maximize the dynamic performance of the ADC. Although
PCM1801 has two power lines to maximize the potential of
dynamic performance, using one common power supply is
recommended to avoid unexpected power supply problems,
such as latch-up due to power supply sequencing.

LRCK

1.4V

0.5V

BCK

DOUT

BCKH

LRCP

CKDO

LRDO

BCKP

BCKL

LRHD

LRSU

DESCRIPTION

SYMBOL

MIN

TYP

MAX

UNITS

BCK Period

BCKP

300

BCK Pulse Width HIGH

BCKH

120

BCK Pulse Width LOW

BCKL

120

LRCK Set Up Time to BCK Rising Edge

LRSU

LRCK Hold Time to BCK Rising Edge

LRHD

LRCK Period

LRCP

Delay Time BCK Falling Edge to DOUT Valid

CKDO

Delay Time LRCK Edge to DOUT Valid

LRDO

Rising Time of All Signals

RISE

Falling Time of All Signals

FALL

NOTE: Timing measurement reference level is (V

)/2. Rising and falling time is measured from 10% to

90% of I/O signals' swing. Load capacitance of DOUT signal is 20pF.

FIGURE 5. Audio Data Interface Timing.

AGND, DGND PINS

To maximize the dynamic performance of the PCM1801,
the analog and digital grounds are not internally connected.
These points should have very low impedance to avoid
digital noise feedback into the analog ground. They should
be connected directly to each other under the PCM1801
package to reduce potential noise problems.

PINS

A 1.0

F tantalum capacitor is recommended as an AC-

coupling capacitor which establishes a 5.3Hz cut-off fre-
quency. If a higher full-scale input voltage is required, the
input voltage range can be increased by adding a series
resistor to the V

pins.

REF

INPUTS

A 4.7

F tantalum capacitor is recommended between the

REF

1, V

REF

2, and AGND references to ensure low source

impedance. These capacitors should be located as close as
possible to the V

REF

1 or V

REF

2 pins to reduce dynamic errors

on the ADC's references.

SYSTEM CLOCK

The quality of the system clock can influence dynamic
performance in the PCM1801. The duty cycle, jitter, and
threshold voltage at the system clock input pin must be
carefully managed. When power is supplied to the part, the
system clock, bit clock (BCK), and word clock (LRCK)
should also be supplied simultaneously. Failure to supply
the audio clocks will result in a power dissipation increase
of up to three times normal dissipation and may degrade
long-term reliability if the maximum power dissipation limit
is exceeded.

PCM1801

SBAS131A

DGND

SCKI

BCK

LRCK

REF

AGND

FMT

BYPAS

DOUT

System Clock

Data Clock

Latch Enable

Data Out

(1)

(2)

(3)

(2)

+5V

Format

Bypass

Audio Data

Processor

Pin Program

or Control

Lch IN

Rch IN

NOTES: (1) C1 and C2: A 1

F capacitor gives 5.3Hz (

= 1

F * 30k

) cut-off frequency for input HPF in

normal operation and requires power-on setting time of 6ms at power up. (2) C3 and C4: Bypass
capacitor 0.1

F ceramic and 30

F tantalum or aluminum electrolytic, depending on layout and power

supply. (3) C5 and C6: 4.7

F tantalum or aluminum electrolytic capacitor.

FIGURE 6. Typical Circuit Connection.

PACKAGING INFORMATION

ORDERABLE DEVICE

STATUS(1)

PACKAGE TYPE

PACKAGE DRAWING

PINS

PACKAGE QTY

PCM1801U

ACTIVE

SOIC

PCM1801U/2K

ACTIVE

SOIC

2000

(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

www.ti.com

3-Oct-2003

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