SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
'ALS174 and 'AS174 Contain Six Flip-Flops
With Single-Rail Outputs
D
'ALS175 and 'AS175B Contain Four
Flip-Flops With Double-Rail Outputs
D
Buffered Clock and Direct-Clear Inputs
D
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
D
Fully Buffered Outputs for Maximum
Isolation From External Disturbances
('AS Only)
SN54ALS175 . . . J OR W PACKAGE
SN54AS175B . . . J PACKAGE
SN74ALS175, SN74AS175B . . . D, N, OR NS PACKAGE
(TOP VIEW)
SN54ALS174 . . . J OR W PACKAGE
SN54AS174 . . . J PACKAGE
SN74ALS174, SN74AS174 . . . D , N, OR NS PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
6D
5D
NC
5Q
4D
1D
2D
NC
2Q
3D
SN54ALS174, SN54AS174 . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
CLK
4Q
6Q
3Q
GND
NC
NC No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1D
2D
2Q
3D
3Q
GND
V
CC
6Q
6D
5D
5Q
4D
4Q
CLK
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4Q
4D
NC
3D
3Q
1Q
1D
NC
2D
2Q
SN54ALS175 . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
CLK
3Q
4Q
2Q
GND
NC
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
V
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a
direct-clear (CLR) input. The 'ALS175 and 'AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low
level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SN74ALS174N
SN74ALS174N
PDIP
N
Tube
SN74AS174N
SN74AS174N
PDIP N
Tube
SN74ALS175N
SN74ALS175N
SN74AS175BN
SN74AS175BN
Tube
SN74ALS174D
ALS174
Tape and reel
SN74ALS174DR
ALS174
Tube
SN74AS174D
AS174
0
C to 70
C
SOIC
D
Tape and reel
SN74AS174DR
AS174
0
C to 70
C
SOIC D
Tube
SN74ALS175D
ALS175
Tape and reel
SN74ALS175DR
ALS175
Tube
SN74AS175BD
AS175B
Tape and reel
SN74AS175BDR
AS175B
SN74ALS174NSR
ALS174
SOP
NS
Tape and reel
SN74AS174NSR
74AS174
SOP NS
Tape and reel
SN74ALS175NSR
ALS175
SN74AS175BNSR
74AS175B
SNJ54ALS174J
SNJ54ALS174J
CDIP
J
Tube
SNJ54AS174J
SNJ54AS174J
CDIP J
Tube
SNJ54ALS175J
SNJ54ALS175J
SNJ54AS175BJ
SNJ54AS175BJ
55
C to 125
C
CFP
W
Tube
SNJ54ALS174W
SNJ54ALS174W
CFP W
Tube
SNJ54ALS175W
SNJ54ALS175W
SNJ54ALS174FK
SNJ54ALS174FK
LCCC FK
Tube
SNJ54AS174FK
SNJ54AS174FK
SNJ54ALS175FK
SNJ54ALS175FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
This orderable is not recommended for new designs.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLR
CLK
D
Q
Q
L
X
X
L
H
H
H
H
L
H
L
L
H
H
L
X
Q0
Q0
'ALS175 and 'AS175B only
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagrams (positive logic)
1D
C1
R
To Five Other Channels
1
9
3
2
CLR
CLK
1D
1Q
1Q
1
9
C1
1D
CLK
CLR
1D
R
1Q
To Three Other Channels
4
2
3
'ALS174, 'AS174
'ALS175, 'AS175B
Pin numbers shown are for the D, J, N, NS, and W packages.
absolute maximum ratings over operating free-air temperature range, SN54/74ALS174,
SN54/74ALS175 (unless otherwise noted)
Supply voltage, V
CC
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 1): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
0.4
0.4
mA
IOL
Low-level output current
4
8
mA
TA
Operating free-air temperature
55
125
0
70
C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = 4.5 V,
II = 18 mA
1.5
1.5
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = 0.4 mA
VCC 2
VCC 2
V
VOL
VCC = 4 5 V
IOL = 4 mA
0.25
0.4
0.25
0.4
V
VOL
VCC = 4.5 V
IOL = 8 mA
0.35
0.5
V
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
All others
VCC = 5 5 V
VI = 0 4 V
0.1
0.1
mA
IIL
CLK
VCC = 5.5 V,
VI = 0.4 V
0.15
mA
IO
VCC = 5.5 V,
VO = 2.25 V
20
112
30
112
mA
ICC
'ALS174
VCC = 5 5 V
See Note 3
11
19
11
19
mA
ICC
'ALS175
VCC = 5.5 V,
See Note 3
8
14
9
14
mA
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
NOTE 3: ICC is measured with D inputs and CLR grounded, and CLK at 4.5 V.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN
MAX
MIN
MAX
fclock
Clock frequency
40
50
MHz
CLR low
15
10
tw
Pulse duration
CLK high
12.5
10
ns
CLK low
12.5
10
t
Set p time before CLK
Data
15
10
ns
tsu
Setup time before CLK
CLR inactive
8
6
ns
th
Hold time, data after CLK
0
0
ns
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN
MAX
MIN
MAX
fmax
40
50
MHz
tPLH
CLR
Any Q
3
20
5
18
ns
tPHL
CLR
y
(or Q, 'ALS175)
5
30
8
23
ns
tPLH
CLK
Any Q
3
20
3
15
ns
tPHL
CLK
y
(or Q, 'ALS175)
5
24
5
17
ns
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range, SN54/74AS174,
SN54/74AS175B (unless otherwise noted)
Supply voltage, V
CC
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 1): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
SN54AS174
SN54AS175B
SN74AS174
SN74AS175B
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
2
2
mA
IOL
Low-level output current
20
20
mA
TA
Operating free-air temperature
55
125
0
70
C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54AS174
SN54AS175B
SN74AS174
SN74AS175B
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = 2 mA
VCC 2
VCC 2
V
VOL
VCC = 4.5 V,
IOL = 20 mA
0.35
0.5
0.35
0.5
V
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
VCC = 5.5 V,
VI = 0.4 V
0.5
0.5
mA
IO
VCC = 5.5 V,
VO = 2.25 V
30
112
30
112
mA
ICC
'AS174
VCC = 5 5 V
See Note 4
30
45
30
45
mA
ICC
'AS175B
VCC = 5.5 V,
See Note 4
22.5
34
22.5
34
mA
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
NOTE 4: ICC is measured with D inputs, CLR, and CLK grounded.
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
SN54AS174
SN54AS175B
SN74AS174
SN74AS175B
UNIT
MIN
MAX
MIN
MAX
fclock*
Clock frequency
100
100
MHz
CLR low
5.5
5
t *
Pulse duration
CLK high
4
4
ns
tw*
Pulse duration
CLK low
'AS174
6
6
ns
CLK low
'AS175B
5
5
Data
'AS174
4
4
tsu*
Setup time before CLK
Data
'AS175B
3
3
ns
CLR inactive
6
6
th*
Hold time, data after CLK
1
1
ns
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data, but is not production tested.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
(INPUT)
(OUTPUT)
SN54AS174
SN74AS174
MIN
MAX
MIN
MAX
fmax*
100
100
MHz
tPHL
CLR
Any Q
5
15
5
14
ns
tPLH
CLK
Any Q
3.5
9.5
3.5
8
ns
tPHL
CLK
Any Q
4.5
11.5
4.5
10
ns
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data, but is not production tested.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
(INPUT)
(OUTPUT)
SN54AS175B
SN74AS175B
MIN
MAX
MIN
MAX
fmax*
100
100
MHz
tPLH
CLR
A
Q
Q
4
10
4
9
ns
tPHL
CLR
Any Q or Q
4.5
15
4.5
13
ns
tPLH
CLK
Any Q or Q
3
8.5
3
7.5
ns
tPHL
CLK
Any Q or Q
3
11
3
10
ns
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data, but is not production tested.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/ 74ALS AND 54AS/ 74AS DEVICES
tPHZ
tPLZ
tPHL
tPLH
0.3 V
tPZL
tPZH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
CL
(see Note A)
7 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
VOL
VOH
VOH
VOL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
0 V
VOH
VOL
3.5 V
In-Phase
Output
0.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
R2
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
CL
(see Note A)
RL
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
5962-9553701Q2A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
5962-9553701QEA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
83019012A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
8301901EA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
8301901FA
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
83019022A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
8301902EA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
8301902FA
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
JM38510/37201B2A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
JM38510/37201BEA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
JM38510/37202B2A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
JM38510/37202BEA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SN54ALS174J
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SN54ALS175J
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SN54AS174J
OBSOLETE
CDIP
J
16
TBD
Call TI
Level-NC-NC-NC
SN54AS175BJ
ACTIVE
CDIP
J
16
1
TBD
Call TI
Call TI
SN74ALS174D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS174DE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS174DG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS174DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS174DRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS174DRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS174N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74ALS174N3
OBSOLETE
PDIP
N
16
TBD
Call TI
Call TI
SN74ALS174NE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74ALS174NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS174NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS175D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS175DE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS175DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS175DRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS175N
ACTIVE
PDIP
N
16
25
Pb-Free
CU NIPDAU
Level-NC-NC-NC
PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2005
Addendum-Page 1
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
(RoHS)
SN74ALS175NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALS175NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS174D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74AS174DE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74AS174DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74AS174DRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74AS174N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74AS174NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS174NSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS175BD
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS175BDE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS175BDR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS175BDRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS175BN
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74AS175BNE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74AS175BNSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AS175BNSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54ALS174FK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ALS174J
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ALS174W
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ALS175FK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ALS175J
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SNJ54ALS175W
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
SNJ54AS174FK
NRND
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54AS174J
NRND
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SNJ54AS175BFK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54AS175BJ
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2005
Addendum-Page 2
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2005
Addendum-Page 3
MECHANICAL DATA
MLCC006B OCTOBER 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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Post Office Box 655303 Dallas, Texas 75265
Copyright
2005, Texas Instruments Incorporated
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