SN54LVT125, SN74LVT125
3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS
SCBS133D MAY 1992 REVISED JULY 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
D
Support Live Insertion
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs
description
These bus buffers are designed specifically for low-voltage (3.3-V) V
CC
operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The
LVT125 feature independent line drivers with 3-state outputs. Each output is in the high-impedance state
when the associated output-enable (OE) input is high.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT125 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT125 is characterized for operation over the full military temperature range of 55
C to 125
C. The
SN74LVT125 is characterized for operation from 40
C to 85
C.
Copyright
1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
SN54LVT125 . . . J PACKAGE
SN74LVT125 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3OE
1Y
NC
2OE
NC
2A
1A
1OE
NC
3Y
3A
V
4OE
2Y
GND
NC
SN54LVT125 . . . FK PACKAGE
(TOP VIEW)
CC
NC No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVT125, SN74LVT125
3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS
SCBS133D MAY 1992 REVISED JULY 1995
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE
A
Y
L
H
H
L
L
L
H
X
Z
logic symbol
logic diagram (positive logic)
EN
1
1OE
2
1A
1Y
3
4
5
2A
10
9
3A
13
12
4A
2Y
6
3Y
8
4Y
11
2OE
3OE
4OE
1
4
5
6
2A
2Y
2OE
1
2
3
1A
1Y
1OE
10
9
8
3A
3Y
3OE
13
12
11
4A
4Y
4OE
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, and PW packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state or power-off state, V
O
(see Note 1)
0.5 V to 7 V
. . . .
Current into any output in the low state, I
O
: SN54LVT125
96 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT125
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): SN54LVT125
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT125
64 mA
. . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air) (see Note 3): D package
1.25 W
. . . . . . . . . . . . . . . . . . . .
DB or PW package
0.5 W
. . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150
C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
SN54LVT125, SN74LVT125
3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS
SCBS133D MAY 1992 REVISED JULY 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LVT125
SN74LVT125
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2.7
3.6
2.7
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t /
v
Input transition rise or fall rate
Outputs enabled
10
10
ns / V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVT125
SN74LVT125
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 2.7 V,
II = 18 mA
1.2
1.2
V
VCC = MIN to MAX, IOH = 100
A
VCC 0.2
VCC 0.2
VOH
VCC = 2.7 V,
IOH = 8 mA
2.4
2.4
V
VOH
VCC = 3 V
IOH = 24 mA
2
V
VCC = 3 V
IOH = 32 mA
2
VCC = 2 7 V
IOL = 100
A
0.2
0.2
VCC = 2.7 V
IOL = 24 mA
0.5
0.5
VOL
IOL = 16 mA
0.4
0.4
V
VOL
VCC = 3 V
IOL = 32 mA
0.5
0.5
V
VCC = 3 V
IOL = 48 mA
0.55
IOL = 64 mA
0.55
VCC = 0 or MAX,
VI = 5.5 V
10
10
II
VI = VCC or GND
Control inputs
1
1
A
II
VCC = 3.6 V
VI = VCC
Data inputs
1
1
A
VI = 0
Data inputs
5
5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
100
A
II(h ld)
VCC = 3 V
VI = 0.8 V
Data inputs
75
75
A
II(hold)
VCC = 3 V
VI = 2 V
Data inputs
75
75
A
IOZH
VCC = 3.6 V,
VO = 3 V
5
5
A
IOZL
VCC = 3.6 V,
VO = 0.5 V
5
5
A
Outputs high
0.12
0.19
0.12
0.19
ICC
VCC = 3.6 V,
IO = 0,
Outputs low
4.5
7
4.5
7
mA
ICC
VI = VCC or GND
Outputs
disabled
0.12
0.19
0.12
0.19
mA
ICC
VCC = 3 V to 3.6 V,
One input at VCC 0.6 V,
Other inputs at VCC or GND
0.3
0.2
mA
Ci
VI = 3 V or 0
4
4
pF
Co
VO = 3 V or 0
8
8
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT125, SN74LVT125
3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS
SCBS133D MAY 1992 REVISED JULY 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT125
SN74LVT125
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
0.3 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
tPLH
A
Y
1
4.2
4.7
1
2.7
4
4.5
ns
tPHL
A
Y
1
4.1
5.1
1
2.9
3.9
4.9
ns
tPZH
OE
Y
1
4.9
6.2
1
3.4
4.7
6
ns
tPZL
OE
Y
1.1
4.9
6.7
1.1
3.4
4.7
6.5
ns
tPHZ
OE
Y
1.8
5.3
5.9
1.8
3.7
5.1
5.7
ns
tPLZ
OE
Y
1.3
4.7
4.2
1.3
2.6
4.5
4
ns
All typical values are at VCC = 3.3 V, TA = 25
C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT125, SN74LVT125
3.3-V ABT QUADRUPLE BUS BUFFERS
WITH 3-STATE OUTPUTS
SCBS133D MAY 1992 REVISED JULY 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
6 V
Open
GND
500
500
Data Input
Timing Input
1.5 V
2.7 V
0 V
1.5 V
1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH 0.3 V
[
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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